JPS6267856A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To shorten the required period of time from writing data in a semiconductor storage device storing multiple-value data up to completion of the device, by constructing a memory cell with a plurality of MISFET's having different transconductances while connecting the MISFET's in parallel. CONSTITUTION:A memory cell M is provided in a region surrounded by word lines WL, a bit line BL and a ground line GL. The memory cell M is constituted by two N-channel MISFET's Q1 and Q2 having different transconductances. The gate electrodes of the MISFET's Q1 and Q2 are both connected to the word lines WL, while the drain regions of the MISFET's Q1 and Q2 are connected to the bit lines BL. The MISFET's Q1 and Q2 are connected in parallel with each other. The MISFET Q2 herein has a transconductance (gm) corresponding to a half of the transconductance of the MISFET Q2. Data is written in the memory cell by introducing a P-type impurity such as boron into the channel regions of the MISFET's for increasing the threshold value.

Description

[Detailed description of the invention] [Technical field] The present invention relates to a semiconductor memory device.

In particular, the present invention relates to a technique that is effective when applied to semiconductor memory devices that store nonvolatile information.

[Background technology] In order to increase the integration density of mask ROMs, a technology for storing multi-valued information has been published in the magazine Electronics, March 24, 1984, pages 121-123 (Electr.
onics March24.1984 pp12
1 to 123). In this technique, the gate length and gate width of the memory cell, that is, the MISFET, is changed for each memory cell, or the threshold value of the MISFXT is changed for each memory cell.

As a result of studying the multilevel storage technology, the present inventor found that it takes a long time from writing information to completing the manufacturing process. A technique for storing multilevel information by changing gate length and gate width.

Information is written in the process of forming the field isolation IIk film. However, since the field insulating film is formed at the initial stage of the manufacturing process, it takes a long time from writing information to completing the product. On the other hand, in order to store multilevel information by changing the threshold value, impurities that change the threshold value must be introduced into the channel region of the MIS FET multiple times. The process is repeated multiple times, and it takes a long time from writing information to completing the product.

[Object of the Invention] An object of the present invention is to provide a technique for shortening the time required from writing information to a semiconductor memory device that stores multivalued information to completing a product.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, a memory cell is configured by a plurality of MISFETs having different mutual conductances, and the MISFETs are
This is a parallel connection of ETs.

Hereinafter, the configuration of the present invention will be explained along with examples.

[Embodiment] FIG. 1 is a detailed circuit diagram of a memory cell array of a mask ROM of this embodiment.

In FIG. 1, WL is a word line. Word line WL
Bit lines BL, ground, and aGL are alternately arranged to intersect with each other. Word line WL, bit line BL and ground line G
A memory cell M is provided in a portion surrounded by L.

Memory cell M is composed of two n-channel MISFETs QI and Q2 having different mutual conductances. The gate electrodes of these two MI 5FETs Q+ and Q2 are both connected to the word line WL. On the other hand, the drain regions of the two MI 5FETQI, Q2 are connected to the bit line BL, and the source regions are connected to the ground gGL. That is, MISFET Q1 and Q2 are connected in parallel.In this embodiment, MISFET
The mutual conductance of Q2 is M I S FETQ
It is 1/2 of l. This is the mask RO of this example.
Since M is a multi-level memory, there are a plurality of potential levels read from each memory cell M, but this is to make these potential levels uniform.

Information is written by introducing a p-type impurity, such as boron (B), into the channel region of the 1Ml5FETQ to increase the threshold value, as will be described later. In FIG. 1, the p-type impurity in the channel region is indicated by a dotted line. In the memory cell M1, p-type impurities are introduced into the channel regions of both the M I S F E TQ layer and Q*.
Threshold is high. i.e. 1Ml5FETQ
凰 and Q2 both maintain a non-conductive state when reading information (when the word line WL is at a high level). A p-type impurity is introduced only into the memory cell array il MISFETQ2 to increase the threshold value. That is,
The MISFE maintains the non-conducting state during reading.
T Q 2 only, M I S F E T Q
t is conductive. Memory cell M3 is MIS at the time of reading.
Only FETQI remains non-conductive. Memory cell M4 is MI 5FETQ at the time of reading.
Both n and Q2 become conductive. The other memory cells M are similar to any of the memory cells M s "" M 4 .

A ground switch Qg made of an MI S FET is connected to the ground line GL. By this ground switch Qg, the ground line GL is set to the circuit ground potential 1, for example, 0 [V] during reading.

That is, one end of the ground switch Qg is connected to the power supply terminal of the circuit's ground potential Vss. A bit line switch Qb is connected to the bit @BL. By selecting bit line switch Qb, bit line BL and sense amplifier SA are connected to read information.

That is, the power supply potential Vc is applied only to the selected bit line BL.
c, for example, 5 [v] is applied.

Next, a method of manufacturing the mask ROM of this embodiment will be explained.

2 to 16 are plan views or cross-sectional views of memory cells in the mask ROM manufacturing process.

Note that insulating films other than the field insulating film are not shown in the entire plan view.

First, as shown in FIG. 2 and FIG. 3, which is a cross-sectional view taken along the line A-A, the surface of a semiconductor substrate l made of P-type single crystal silicon is selectively oxidized to form a field insulating film 2. Form. That is, the field insulating film 2 is made of a silicon oxide film.

Furthermore, a p-type channel stopper region 3 is formed on the surface below the field insulating film 2. In fig.

A region where one memory cell M consisting of two MISFETs is provided is shown surrounded by a two-dot chain line. As will be described later, the word line WL is provided extending in the same direction as the AA cutting line. In addition, the bit line BL and the ground line G
L is provided extending in a direction intersecting the AA cutting line. In the field insulating film 2, the field insulating film 2
A is for partitioning the memory cells M, and the field insulating film 2B is for dividing the two MIs constituting the memory cell M.
This is to separate S F E T Q * and Q2.

As can be understood from FIG. 2, for example, the distance between the field insulation film 2 A s and the field insulation 112 B s.

Field insulating film 2B1 and field insulating film 2A2
is different from the distance of This is because it defines field extinction.

Next, the entire surface of the semiconductor substrate 1 is oxidized to form the gate insulating film 4 of the memory cell M on the surface between the field insulating films 2. That is, the gate insulating film 4 is made of a silicon oxide film.

Next, as shown in FIG. 4 and FIG. 5, which is a cross-sectional view taken along the line AA of FIG. 4, a polycrystalline silicon layer 5 is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD. In addition,
FIG. 4 is the same as the plan view used in the following description, in which the channel stopper region 3 is not shown. In order to lower the resistance of the polycrystalline silicon film 5, an n-type impurity (for example, phosphorus CP) is introduced into the polycrystalline silicon film 5 by, for example, ion implantation.Next, a resist film 6 is formed as a mask for patterning the polycrystalline silicon film S. form. This resist film 6 is formed in a pattern of word lines WL.

Next, as shown in FIG. 6 and FIG. 7, which is a cross-sectional view taken along the line A--A, the polycrystalline silicon M5 exposed from the resist film 6 is patterned, for example, by dry etching. After this etching, the resist film 6 is removed. The polycrystalline silicon film 5 becomes the word line WL on the field insulating film 2, and becomes the gate electrode G of the memory cell M on the gate insulating film 4. That is, the word line WL and the gate electrode G are integrally formed.

In addition, in the gate electrode G, the gate electrode G1 is the one having the larger mutual conductance as shown in FIG.
It is a gate electrode of I S F E T Q s, and the gate voltage ti G 2° is the same as the length of the smaller mutual conductance, but the gate width of gate electrode G1 is 2° of the gate width of gate electrode G2. It's doubled. M.I.
MIS the mutual conductance of S F E T Q I
This is to make the mutual conductance twice that of FETQ2. Note that the word line WL and the gate voltage tli! G is not limited to the polycrystalline silicon film 5. For example, high melting degree, @
(Mo, W, Ta, Ti) film or a silicide film of the high melting point metal, or a laminated film in which the high melting point metal or the silicide film thereof is provided on a polycrystalline silicon layer. It's okay.

Next, as shown in FIG. 8 and FIG. 9, which is a cross-sectional view taken along the line A-A, n-type impurities such as arsenic (As
) is introduced into the surface of the semiconductor substrate 1 by ion implantation to form a type semiconductor region 7 that will become the source and drain regions of the memory cell M.

The gate electrode G serves as a mask for ion implantation. That is, the n0 type semiconductor region 7 is formed in a self-aligned manner with respect to the gate electrode 7.

Note that memory cell M, that is, MISFETQl, Q2
is essentially completed through the steps up to this point.

That is, MISFETQ has a gate electrode G consisting of a gate insulating film 4 and a polycrystalline silicon layer 5 and a semiconductor region 7.
It is made up of.

Further, among the semiconductor regions 7, the semiconductor region 7A with the subscript A becomes the drain region of the MI 5FETQi, Q2, but the MIFETQ! .

The drain region of G2 is integrated, and as described later, the semiconductor region 7A is connected to the bit line BL. Similarly, the semiconductor region 7B with the subscript B is MISFETQ□,
It becomes the source region of G2 and is formed integrally. Semiconductor region 7B will later be connected to ground line GL. In other words, M I S F E T Q constituting the memory cell M
t and G2 are connected in parallel to the bit line BL and the ground line GL. Furthermore, the semiconductor regions 7A, which are drain regions, and the semiconductor regions 7B, which are source regions, are arranged alternately in the direction in which the bit lines BL and the ground lines GL extend.

Next, as shown in FIGS. 10 to 14, a resist mask 8 for writing information is formed over the entire surface of the semiconductor substrate 1. Then, as shown in FIGS. In addition, FIG. 11 is a cross-sectional view taken along the line A-A in FIG. 10, and FIG. 12 is a cross-sectional view taken along the line B-B in FIG.
Figure 3 is a cross-sectional view taken along the line C-C, and Figure 14 is a cross-sectional view taken along the line C-C.
FIG. 3 is a cross-sectional view taken along a cutting line. Resist mask 8 includes
An opening 9 for introducing impurities is provided. At aperture 9.

The opening 9A is formed large so that the gate electrodes G□ and G2 are exposed. The opening 9B is formed so that the gate electrode G2 having the smaller gate width is exposed. Opening 9
C is formed so that the gate electrode G1 having a larger gate width is exposed.

After forming the resist mask 9, the openings 9A, 9B,
9C into the channel region of vi I5FETQ. Note that in FIGS. 10 to 14, the channel region into which the p-type impurity is introduced is shown as the p-type semiconductor region 10. The channel region into which no p-type impurity is introduced is p-type like the semiconductor substrate 1. The p-type impurity is introduced through the gate electrode G and the gate insulating film 4. M whose channel region is a p-type semiconductor region 10
ISFETQ has a high threshold value and maintains a non-conductive state even when the gate electrode G is at a high level, that is, the electric potential Vcc. Therefore, in the memory cell M shown in FIG.
T Q s (No code attached, same applies below)
and M I S F E T Q 2 both maintain a non-conducting state. In the memory cell M shown in FIG. 12, the M I S with the smaller mutual conductance
Only FETQ2 remains non-conducting. In the memory cell M shown in FIG. 13, the MS I FET Q! with the larger mutual conductance is the one with the larger mutual conductance. only remains non-conductive.

However, in the memory cell M shown in FIG.

Since the entire area is covered with the resist mask 8, MI5FETQ! , G2 both become conductive. In this way, in this embodiment, four types of information can be stored by writing the information - times. Also,
Ion implantation for writing information is performed on MI 5F.
Since it is sufficient to make ETQi and G2 non-conductive, 1. For example, when making MI S FET Q s non-conductive, the influence of ion implantation 1. There is no change in the mutual conductance of FETQ2. In other words, the reliability of writing can be improved.

After the information writing, ie, ion implantation, the resist mask 8 is removed.

The following steps are explained in FIG. 15, which shows the completed plane of the memory cell array, and in FIG.
This will be explained using Figure 6.

After writing the information, an insulating film 11 is formed by sequentially stacking a silicon oxide film and a phosphosilicate glass film on the semiconductor substrate 1 by, for example, CVD. Note that in the first step, the insulating film 11 is not shown in FIG. 15, in the first step in which the insulating film 11 is selectively removed to form the connection hole 12, an aluminum layer is formed on the semiconductor substrate 1 by sputtering, for example. This aluminum layer is selectively removed to form bit lines BL and ground lines GL. As described above, in this embodiment, the bit line BL and the ground line GL are made of an aluminum layer having a low resistance value. As shown in Figure 15,
The bit line BL and the @GL extend in a direction intersecting the word line WL. Furthermore, bit line BL and ground line O
L are arranged alternately. A memory cell M is located in an area surrounded by this bit line BL, ground line GL, and word line WL.
is configured. Note that after the connection hole 12 is formed, an n-type impurity 1 such as phosphorus is reintroduced through the connection hole 12.

After forming the bit line BL and ground line GL, although not shown, a final protective film is formed by sequentially stacking a silicon oxide film, a PSG film, and a silicon nitride film, for example, by CVD.

[Effects] According to the new technology disclosed by the present application, the following effects can be obtained.

(1) By configuring each memory cell with two MISFETs with different mutual conductances, multi-level information can be obtained with a single ion implantation, reducing the time required from writing information to completing the product. be able to.

(2) Since the bit line and the ground line are made of an aluminum layer having a low resistance value, the read speed can be increased.

(3) Ion implantation for writing information is M
Since it is sufficient to make the I S FET non-conductive, the mutual conductance of other MISFETs does not change due to the ion implantation, and therefore reliability of information writing can be improved.

Above, the present invention was specifically explained using examples.
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

[Brief explanation of drawings]

FIG. 1 is a detailed circuit diagram of a memory cell array of a mask ROM according to an embodiment of the present invention. 2 to 16 are plan views or cross-sectional views for explaining the manufacturing process of the mask ROM. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2.2A, 2B... Field insulating film, 3... Channel stopper region, 4... Gate insulating film, 5... Polycrystalline silicon film, 6.8... Resist mask, 7.7A, 7B, 10... Semiconductor region, 9.9A, 9B, 9C... Opening, 11... Insulating film, 12... Connection hole, WL... Word line, BL ...
Bit line, GL...ground line, M...memory cell, Q
s, Q,... MISFET, Qg, Qb... switch, SA... sense amplifier, G... gate electrode. Figure 1

Claims (1)

Claims: 1. A semiconductor memory device characterized in that each memory cell for storing nonvolatile information is composed of a plurality of MISFETs, and the plurality of MISFETs are connected in parallel. 2. The semiconductor memory device according to claim 1, wherein each of the plurality of MISFETs constituting the memory cell has a different mutual conductance. 3. The semiconductor memory device according to claim 1, wherein the memory cell stores nonvolatile information by introducing impurities into a channel region.