JPS6266172A - Self-diagnostic device for controller for faulty section detecting device - Google Patents

Abstract

PURPOSE:To detect an abnormality of a diagnostic device by adding an opening/closing means, etc. for showing a state that a power source of a distribution line exists or not, to the self-diagnostic device which is provided on a controller for a faulty section detecting device of the distribution line, and controlling the opening and closing by a CPU contained in the diagnostic device. CONSTITUTION:An opening/closing means m6a for forming a charging circuit from a primary control power source at the time of a diagnosis is provided on an energy storing power source circuit 25a which is charged by an output of a Y timer 17 when a Z2 time limiting circuit 25 is steady. A opening/closing means m7b which can reset a storing circuit 24 by opening and closing an inhibiting signal to an inhibiting circuit INH4 by an output of a Y timer 17 and an output of a Z2 timer 25, and cutting off the inhibiting signal of the circuit INH4 instantaneously when an output of a power source side voltage detecting circuit 22 is generated at the time of a diagnosis is provided. Also, opening/closing means m8b, m9b for showing simulatively a state that a power source of a distribution line exists or not are provided. In this way, the opening/closing means m6a, m7b, m8b, and m9b are controlled by a CPU of a self-diagnostic device, by which whether an abnormality exists or not can be detected.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a device for arbitrarily, automatically and regularly checking whether or not its own circuit function is normal in a controller for a fault section detection device. It is something.

[Prior art and its problems]

The fault section detection device controller is installed with the purpose of responding to abnormal conditions that occur in power lines or power equipment in distribution lines, minimizing damage, and preventing any negative impact on other healthy sections. be done. As described above, the role of the controller for the failure section detection device is important, and it must be able to operate reliably even in rare abnormal conditions.

Therefore, it is necessary to periodically inspect the controllers to see if they are functioning properly, but conventionally this has been difficult due to the large number of units installed and work problems caused by installation on a pole. . Also, even if periodic inspections are carried out, if the controller breaks down between one periodic inspection and the next,
If the detection is delayed and an actual ground fault or short circuit occurs, the controller will not operate, causing damage such as widespread power outages and power transmission to the point of the fault.

[Purpose of the invention]

The present invention solves these conventional problems by providing the controller itself with a self-diagnosis function for the circuit status, so that when an abnormality occurs in the circuit, an alarm can be issued and repairs can be carried out promptly. The purpose is to improve the reliability of the controller.

[Conventional embodiment]

Figure 3 shows the integrated circuit diagram of the fault section detection and disconnection device.
1) is the section switch, (2) is its main contact, (3) is the closing electromagnetic coil, (4), (5) is the section switch (1
) is an operating transformer whose primary side is connected to the power supply side and load side distribution lines (6) and (7), respectively, which are connected to the main contactor (2) of the controller (8), and which supplies operating power to the controller (8). do.

One terminal on the secondary side of the operation transformers (4) and (5) is connected to terminals A and D, respectively, the other terminal is connected to common terminal B, and the coil (
3) Connect the -10,000 terminal to terminal C and the other terminal to terminal B, respectively.

FIG. 4 is a block diagram showing an example of a circuit of a conventional controller for a fault section detection device. In the figure, A is the power supply side (hereinafter A
D is the load side (hereinafter referred to as the down side), and B is the common voltage input terminal.

C is an output terminal for driving the input electromagnet. (11) is a power supply selection circuit which selects and outputs either the A side or D side number power supply, and selects the side to which power is supplied first when both sides are in a power outage state.

The secondary side output terminals E and F of the power supply selection circuit (11) are connected to the control power supply circuit (12) via the C8b contact of the operation switch C8 and the control transformer T, and the control circuit is connected from the secondary side terminal G of the power supply selection circuit (11). Supplies control power to each part.

The operation switch C8 has three control positions: "Returner", "On", and "Off", and "On" is the position during normal operation, "
"OFF" is the position where the control circuit is disconnected and the operation is stopped, "RETURN ON"
is the position temporarily assumed when the control circuit is returned to the operating state after a locking operation, and returns to the human state after the operation. The switch C8 has three contacts, and the CSB contact is return ON, the ON notch is ON, the OFF notch is OFF, and the other two
Contacts C3a and C3a2 are both turned on at the return entry notch,
People turn off at Kirinotsuchi. C3a from terminal E.

Connect to output terminal C via contact.

Reference numeral (13) denotes a first memory circuit which permanently stores the operation history of the controller circuit, selects whether lock operation is possible or not according to the memory state, and controls the operation of detecting a faulty section of the power distribution line.

When control power is supplied under normal conditions, the first memory port "1. (13) immediately outputs an output. This output is
The voltage is applied to the X timer (15) through the time setting circuit (14), the X timer (15) starts counting, and after the predetermined X time has elapsed, the X timer (15) outputs the signal through the inhibit circuit INH2. and gives a signal to the output circuit (16). The output circuit (16) immediately outputs an output, and the output relay M
energize C. Output relay MC contact MCa from terminal E
is connected to output terminal C via Ru.

The output of the output circuit (16) also gives a signal to the Y timer (17) of the output circuit (16), the Y timer (17) starts counting, and after a predetermined Y time elapses, the Y timer (17)
outputs. The output of the Y timer (17) provides an inhibit signal to the inhibit circuit INH1 to stop the reset signal, and also provides a set signal to the first storage circuit (13) to set it.

The first memory circuit (13) enters an output state, maintains this state, and enters a steady closing state. When power is retransmitted after a power outage in this state, the first memory circuit (13) immediately outputs an output and repeats the above operation.

The output signal of the output circuit (16) also outputs the z1 timer (
18), and in the event of a momentary power outage, the output output is maintained for Z1 hours using a 2-timer, and when the power is restored, the output circuit is driven to continue the output. From the output terminal G of the control power supply circuit (12), C8a is connected to the output circuit (16) through a contact point.
) gives a signal to the input terminal of the output circuit (
16) is forcibly driven.

A signal is applied from the input terminal of the X time setting circuit (14) to the X indicator lamp (19) via the inhibit circuit INH, and an inhibit signal of one circuit INH is applied from the output terminal of the output circuit (16). The X indicator light (19) is the X timer (15
) is in operation. Y timer (17)
A signal is applied from the input terminal of the Y indicator lamp (20) via the inhibit circuit INH, and an inhibit signal of the circuit INH is applied from the output terminal of the Y timer. Y indicator light (2
0) indicates that the Y timer (17) is in operation.

The terminals A and B are connected to the A voltage control detection circuit (21) via the control transformer T2, and output to its secondary output terminal H.

The terminal B is connected to the D voltage control detection circuit (22) via the control transformer T3, and is output to its secondary output terminal J.

When the terminal is input, it is input from J to the loop prevention circuit (23), and this circuit (23) outputs when the A side and D side power supplies are applied at the same time, and passes through the inhibit circuit INH to the first memory circuit (13). Apply a reset signal to lock the closing control circuit. The inhibit signal of the circuit INH, is given from the output terminal of the Y timer (17) as described above, and the inhibit signal of the circuit INH,
When the timer is output, the above reset operation is blocked.

An input signal is input from the output terminal J of the D control voltage detection circuit (22) to the circuit INH1 via the inhibit circuit INH3, and the circuit I
Give an inhibit signal to NH. (24) is the second
The memory circuit stores the power transmission status of the A side and D control power source (2!, 22), the operation history of the controller (8), especially the Y timer (17)
The output state of the memory is stored, and depending on the stored state, it is determined whether or not a lock signal can be output, and the reverse feed lock operation is controlled.

The storage circuit (24) receives a set signal from the Y timer output terminal P2, and the inhibit circuit INH from the output terminal H of the A voltage control detection circuit (21).

A reset signal is given to each via. Memory circuit (2
The output of 4) provides an inhibit signal to the inhibit circuit INH through the changeover switch SW.

The inhibit signal of the inhibit circuit INH4 is input from the Y timer output terminal P2, and also from the D control voltage detection circuit (22
) are respectively given from the output terminals J.

The switch SW is used to select whether or not to make the reverse feed lock conditional. When it is opened, the switch SW operates according to the storage state of the storage circuit (24), that is, when the storage circuit (24) is in the reset state. When it is released, if a reverse transmission signal is issued, it will be locked unconditionally. When the power goes out after the Y timer (17) outputs, the Z timer supplies the output to the inhibit circuit INH4 for a predetermined period of time to provide an insensitive time period for reverse lock, and after the power distribution line condition has stabilized. It is designed to make a detection judgment.

Next, the operation of the device configured as above will be explained.

First, the state during normal power transmission is selected by the power source selection circuit (11) by the power source to which power was transmitted first, and power is supplied to each part, and power is supplied from the power source side and the load side, respectively. The parts that output the output at this time are the A limiting voltage detection circuit (21), the D limiting voltage detecting circuit (22),
Control power supply circuit (12), loop prevention circuit (23), first
memory circuit (13), second memory circuit (24), output circuit (16), Y timer (17), Z timer (18)
), Z, and timer (25).

(1) Sequential transmission operation When power is transmitted from the A power supply side, power is supplied to the control power supply circuit (12) from the power supply selection circuit t4 (11), and the control power supply circuit (12) outputs an output from the transformer T. Circuit (13)
Since the memory circuit (13) stores the output state, the memory circuit (13) also outputs an output. As a result, one transformer T2 → A side low voltage detection circuit (21) → engineering NH
,→Memory circuit (24) reset 1-→Stop X timer (15) Memory circuit (24) Reset input stop @X tie v-(15) →I NH.

The X timer maintains its output, but its output signal is INH
The state cut by step 2 is maintained.

(2) Reverse feed operation When power is simply transmitted from the load side (D side) after a power outage.

Since the memory circuit (13) stores the output state, when the rectifier circuit (12) outputs an output, the memory circuit (13) also outputs an output.

, →INH, → Memory circuit (13) reset → X time clocking stopped → Locked (switch (1) not closed), and an instantaneous input is input to the X timer, but it is immediately reset, locked, and does not close. .

In the case of sn type (SW open) The memory circuit (24) stores the output state, and as soon as the control power supply circuit (12) outputs an output, the memory circuit (24) also resets the output.

D control voltage detection circuit (22) → INH, → output stop ↑ The following operation is the same as the sequential transmission operation, and power is transmitted from the D side to the A side.

(3) During the detection time power failure closing operation restraining operation During sequential operation, if the output circuit (16) is ON and there is a power outage due to a track accident etc. during Y time, the operation below θ will stop.

Therefore, the memory circuit (13) remains in a reset state, and even if power is transmitted next time, the memory circuit (13) does not output an output, so the control circuit does not enter the operating state, that is, it is locked, and the switch (1) is closed. Not done.

(4) Dual power supply ON restriction operation memory circuit (13) → X timer (X time clock) In this state, the other power supply is also transmitted and becomes dual power supply (Switch (1) is not turned on) (5) Short time power transmission Progressive operation If power is transmitted from the power supply side and there is a power outage during X hours, a power outage will occur →
Retransmission of power from the power supply side (memory circuit (13) has not been reset) → Same operation as progressive operation (6) Power failure during X hours Transfer restriction operation Power transmission from the power supply side (A side) → Power failure during X hours → Memory circuit (
24) is reset → power is transmitted from the load side (D side) → → If it is sn type (SW opening/closing (memory circuit (24) has been reset) → D control voltage detection circuit (22) → INH, → INH□ →Memory circuit (13) reset-lock (open/close W (1) not turned on) (until the reset signal is input to the memory circuit (13), the memory circuit (13) will output an output and the X indicator light will turn on momentarily) (7) Insensitive operation for locking in power outage for x hours If power is retransmitted from the power source within 22 hours after a power outage during normal power transmission, the output will stop → the memory circuit (24) will not be reset, Therefore, even if power is transmitted from the load side next time, the conditions in item (6) above will not be satisfied and the lock will not occur. → The same operation as the reverse feed operation. → A human power signal enters the output circuit (16) and turns it on → Go to the above (1) → ----- → Y timer (17) (clocking Y time) → Y timer (17) output after Y time ends → Turn on Restraint release completed (9) Release delay operation When the controller (8) is in the closed state, the output circuit outputs an output and is self-maintained with the 2-timer (18).If the power fails in this state, the z1 timer will be activated for 21 hours. If the power is restored within 71 hours, the output circuit will immediately operate due to the Z□ timer output, outputting an output and closing the switch (1).

When the power is restored after 70 hours or more have elapsed, the output of the Z1 timer has disappeared and the forward or reverse operation begins. In this case, the output relay MG is activated by the control power supply circuit (
12) The circuit is temporarily opened when the output disappears.

(10) When manual operation/operation switch C5 is set to the "on/return" side, contact C3
a1. C8a is closed. Contact C3a is the output circuit (
16) is driven by applying a direct input signal to release the closing restraint, contact C882 bypasses output contact MCa, and even if the controller is out of order, it outputs an output to terminal C and closes the switch (16).
).

- When the operation switch O8 is turned to the "off" side, the power supply circuit is cut off at the contact csb and the output of the control power supply circuit (12) disappears, so the output of the controller circuit disappears and the switch (1) is opened.

- When the operation switch C8 is turned on, the contact C8b is closed, and the contact C3a1. C3a2 opens, and the above (1) to (9)
).

(11) Others (a) The ffi pressure detection circuits (21, 22) detect the minimum voltage for restricting both types of source input (15■ to 25v) and the minimum voltage for reversing restriction (15v to 25v), and exceed the minimum voltage. Outputs to the secondary side when voltage is applied.

(b) The loop prevention circuit (23) has a built-in dual-type source input restraint minimum time timer, and becomes a dual-type source and outputs an output after a predetermined time.

[Example of the present invention]

FIG. 1 is an integrated circuit diagram of the fault section detection and disconnection device of the present invention;
FIG. 2 is a block diagram showing an embodiment of the present invention, and has a partially similar configuration to FIGS. 3 and 4, and the same or equivalent parts are designated by the same reference numerals and the explanation thereof will be omitted.

To explain the difference between Fig. 1 and Fig. 3, there is a group of inspection relays (81) in the circuit of the fault section detection controller (8).
, an operating state detection means group (82) is added, and a self-diagnosis device (9) and a self-diagnosis operating device (10) are separately provided.

Inside the self-diagnosis device (9) is a central processing unit (hereinafter referred to as CP).
U) (91), CPU U (91) and controller (
8), an interface (92) between the CPU (91
) and other circuits in the self-diagnosis device (9) (93), a group of output relays (94), and a circuit abnormality display device (95). The operating device (10) has a circuit abnormality output bag [1l (101), an arbitrary diagnosis input device (102)
Built-in.

The controller (8) has an input terminal Mi for a group of relays (81).
(i=1.2.----9), operating state detection means group (8
2) Output terminal Pj (j=1.2.3)
In the self-diagnosis bag [(9), terminals with the same symbols corresponding to the above Mi and Pj are connected to each other, and further connected to the CPU (91) via the interface (92) in the device (9). . Interface (93) from CPU (91)
) via internal terminal Mk' (k=lO, 11,----
14) to a group of output relays (94), and further via a group of output relays to an output terminal Mk (k=10.11.-
---14). Also, corresponding to the terminal Mk', a terminal with the same symbol is connected to the circuit abnormality display device (95). In this case, M14' is excluded. An input terminal S is provided from a microcomputer (91) via an interface (93). The operating device (10) is provided with terminals with the same symbols corresponding to the terminals Mk and S, and connected to the terminals Mk and S in the operating device (10).
k (k=10.11.-'---14) is connected to the circuit abnormality output device (101), and terminal S is connected to the optional diagnostic input device (10
2), respectively.

A group of inspection relays (81) constitutes inspection circuit conditions when inspecting the internal control circuit of the controller (8), and connects auxiliary relays mi (i=1.2.---1-9). Each mi corresponds to a terminal Mi, and a relay mi is operated by an input to the terminal Mi. The operating state detection means group (82) has built-in means for deriving the operating state of each element circuit that requires inspection in the internal control circuit of the controller (8) as a signal, and these derived signals are sent to the terminal Pj (j =1.2.3) and is input to the CPU (91). For example, in this case, "
"X time ends", "7 hours end", "lock operation", etc. are targeted.

The CPU (91) operates a group of inspection relays (81) according to a predetermined program, drives the controller circuit in a simulated manner, receives signals indicating the operating status of each element circuit, and checks whether the operation is performed normally. judge whether When driving this simulated circuit, measures must be taken to avoid affecting the actual operation of the circuit. Judgments of circuit abnormalities by the CPU (91) are outputted via the interface (93) and displayed on the circuit abnormality display device (95), and when an arbitrary diagnosis is input, they are sent to the self-diagnosis operating device ( 10
) is output. The self-diagnosis operating device (10) can send and receive signals from the circuit abnormality output device (101) to external control devices (not shown) to perform remote automatic control and the like.

The optional diagnostic input device (102) inputs a command to the microcomputer (91) when forcibly re-executing the inspection operation during remote control. If the inspection operation is to be re-executed, the previous defect diagnosis results are first erased and then executed.

The circuit abnormality display device (95) is provided with, for example, "X time circuit abnormality display", "Y time circuit abnormality display", "lock circuit abnormality display", and "2 hour circuit abnormality display".

The circuit abnormality output device tff (101) is provided with five signals, for example, "X time circuit abnormal output", rYY time circuit abnormal display, "lock circuit abnormal output", "2 hour circuit abnormal output", and "normal output". "Normal output" is output if all inspections have been passed and there is no abnormality at the time of arbitrary diagnosis input.

The display in the circuit abnormality display bag m (95), the output signal of the circuit abnormality output bag [(101), or the external display based on that signal, if the abnormality contents are displayed individually as described above, the failure contents can be determined at a glance. Therefore, it is convenient, but if there is no need to display them individually, it is sufficient to display "abnormality" all at once. Although an indicator light may be used as the display means, a more reliable display is possible if a mechanical or magnetic indicator end is used so that the display can be displayed without any trouble even during a power outage.

Next, the differences between FIG. 2 and FIG. 4 will be explained. Below are the a contacts of each relay mi (i=1.2.---9).

B contact and C contact are contacts mia, mib, and mic, respectively.
If there are two or more contacts, number them sequentially. In FIG. 2, the control Ml source for each element unit is G' from the output terminal G of the control power supply circuit (12) through the contact m1b.
Some parts are directly supplied from terminal G. Contact m1a
gives a timed circuit reset signal to the X timer. Terminal G
A drive signal is directly applied to output relay MC via contact m2a. Contact m3 from terminal G, z1 timer input terminal
Connect to the energy storage power supply (18a) of the Z etimer (18) via the a terminal and l) terminal of Q1, respectively, and the C terminal. Terminal G.

From the X timer output terminal, via the a terminal and b terminal of contact m3c2, respectively, and from the C terminal E, the Z for Y timer, the energy storage power supply (17b) of the timer (hereinafter referred to as Y-Zi timer) (j7a), Y-Z, X via timer (17a)
Give a signal to the timer (]7).

When the output circuit (16) is in the output state and there is a momentary power outage, the Z1 timer (18) stores the output signal for a predetermined time (Z, time), and if the power is restored within that time, the signal is immediately sent to the output circuit (
16) to return to the output state, and the storage power source (18a) is charged by the output of the output circuit (16) during normal operation, but the output circuit (16) may be turned off during diagnosis. Therefore, in that case, in order to ensure the stored power supply that is open during Z operation, charging is performed from the primary control power supply terminal G through the m3c1 contact. The Y-21 timer (17a) is the Zi timer (18
), in the event of a momentary power outage while the X timer is output, the output signal is memorized for a predetermined time (Y/Z time), and if the power is restored within that time, a signal is immediately given to output the X timer (17). In practice, if the output circuit (16) can maintain the output state as described above, the first memory circuit (13) has already been set by the output of the X timer (17) before the power is stopped. The X timer (
There will be no problem even if 17) is operated for a limited time again, but by providing this Y-Z□ timer (]7a), it is possible to restore the output of the X timer in the event of a momentary power outage, and the unnecessary Y time is I try to omit side movements. Y-Z,
The energy storage power source (L7b) of the timer (17a) is X during normal operation.
It is charged by the output of the timer (17), but the Y-timer output may be turned off during diagnosis, and in that case, the Y-2
In order to secure a one-hour storage power supply, charge from the one-number control power supply terminal G through the m3Q2 contact.

The contact m2a connects the memory circuit (
13) and (24).

A signal is applied from terminal G to the output terminal of the output circuit (16) via contact m-. This is to omit the waiting time (X hours) of the X timer at the time of diagnosis.

In Z2 timer, residual voltage remains for a while after the accidental power outage, and when the power is restored, the same phenomenon occurs as when an A-side accident is detected, resulting in D.
Because there is a risk of locking during side power transmission,
The input to the second memory circuit is disconnected for a predetermined time (22 hours) for the residual voltage to disappear, that is, the input to the inhibit circuit INH4 is applied, and
This is to restore the lock circuit after waiting for a certain amount of time. This 2
Two hours is the reverse lock insensitivity time.

A power storage power source (25) is connected from terminal G to a power storage power source (25a) for clocking the Z2 timer (25) via contact m2a.
a) is charged by the output of the Y timer (17), and when the output of the Y timer (17) disappears in the event of a power outage, the Z2 timer (25) clocks 72 hours by this stored energy power source (25a), but the diagnostic Since the Y timer (I7) may be turned off during the operation, charging is ensured from the primary control power supply terminal G through the contact mGa at that time, so that it is possible to shift to normal operation at any time. Contacts m and b are inserted into the inhibit signal circuit to the inhibit circuit INH, which is given from the output terminal P2 of the Y timer (17) and the output terminal of the Z2 timer, and when the first diagnosis is made, the A side mold pressure is opened by opening the contacts m and b. The second storage circuit (24) uses the output signal of the detection circuit (21).
) to conduct the reset signal circuit to enable reset.

This shows the state that the Z2 timer has completed waiting for 72 hours, and it becomes possible to check the operation of the reverse feed lock and the double mold source lock.

Contacts msb and mgb are inserted into the power input circuits of the voltage detection circuits (21, 22) on the A side and D side, respectively, and during diagnosis, the A side and D
Displays the presence or absence of power on the side.

Next, the operation of the device configured as described above will be explained.

The normal operation of the controller (8) of the original fault section detection device in this circuit is exactly the same as the operation in the circuit shown in FIG.
Here, different parts, especially diagnostic operations, will be explained.

The diagnosis section includes a self-diagnosis device (9) and a self-diagnosis operating device (10).
) and a group of inspection relays (8) built into the controller (8).
1) It is composed of a group of operating state detection means (82), and is comprehensively controlled by the CPU (91) in the self-diagnosis device (9). The diagnostic operation starts when the distribution line feeder to which the failure detection device belongs reaches a stable operation state and normal power transmission state.

For example, set the controller (8) of the failure detection device to start inspection 5 minutes after the completion of X time, and
Diagnosis of each item is carried out in a certain order according to the program set in advance in (91), and is repeated cyclically.

The content of the diagnosis is to reveal typical operation in the same pattern as the actual operating condition, check whether the function of each element circuit is within the specified range, and judge whether it is pass or fail. The display device (
95) and the operation bag fi! Output to (LO). Display bag fi! By displaying (95), abnormalities can be detected and corrected during patrol inspection.

The operation bag ff (10) cooperates with a remote control solid device (master station) to enable remote monitoring and control. If the diagnosis determines that there is an abnormality, the diagnosis is stopped by a command from the CPU (91), and the control circuit returns to a normal operating state. Further, the diagnostic operation is immediately interrupted when a change such as a power outage or an accident occurs in the circuit, shifts to normal operation, and then resumes the diagnosis when the feeder becomes stable.

Generally, it is desirable that the order of diagnostic items follows the order of normal operations, but since there may be unexpected cases, the order of operations is programmed and stored in advance, and the operation is performed according to that program. To give a specific example, the diagnostic items and order of diagnosis are as follows.

■X time function ■Y time function ■Lock function to turn on power outage within Y time ■Lock function to reverse power failure during X time ■Lock function to turn on medium-sized power at XX time The operations and functions are as follows.

ml...Contacts m and b forcefully open and close the secondary control power supply circuit from the primary control power supply, and reveal the presence/absence of the control power supply due to transmission/outage of the power distribution line.

At the same time, m2a takes over the X timer reset function when the power is lost.

ml...During diagnosis (m1 is in operation), contact m2a forces the output relay MG into the on state, and the main circuit is in the steady operating state (
(power transmission state) so that even if the control circuit is operated arbitrarily, the actual main circuit will not be affected.

m3... Energy storage power source (18a) for operating after power loss in Y-Z etimer and Z□ timer.

(17b) to supply and store power both during normal operation and during diagnosis, and contacts m3゜4. m3c, the output of the output circuit (16) and the Y timer (1
7) is charged by the output of 1 water control power supply terminal G during diagnosis.
Switch to and charge. This ensures that the operating power for the Y timer and Z timer is always maintained even after the power is turned off.

m4: At the time of diagnosis, the first and second memory circuits (13) and (24) are forcibly set by the contact m4a, and the power recovery state after a power failure during normal power transmission appears. This is to forcefully return the control circuit to a normal state when it becomes locked due to diagnosis.

m...During diagnosis, output circuit (16) is activated by contact m2a.
A signal is applied to the output circuit of the circuit to forcibly generate an output signal, and a state in which the output circuit outputs an output is generated by the X timer signal.

ms...During diagnosis, the stored energy power source (25a) is charged from terminal G by contact mGa to compensate for loss of Y timer output due to diagnostic operation.

m7: By opening contacts m and b, the inhibit signal sent from the storage power supply (25a) for the reverse lock insensitivity time (22 hours) is cut, and the second storage circuit (24)
enable resetting.

That is, it is possible to check the operation of the reverse feed lock by displaying the 22:00 wait completion state of the z2 timer. In this state A
When the second memory circuit (24) is reset by the output of the voltage detection circuit (21) by applying the control power, the inhibit signal of the inhibit circuit INH, is cut, and the inhibit signal D(
1111? When the voltage detection circuit (22) outputs an output by applying the jl source, the first memory circuit is reset by that output and the output from the loop blocking circuit (23), and the switch (1)
appears in an open state. (In this case, the output of the Y timer is off due to the previous power outage.

m8...Contact m. A voltage control detection circuit (2]) by b
The input circuit of A is disconnected, and a power outage condition of the A control power source appears.

D control voltage detection circuit (22) by m,...contact mgb
The input circuit of the D-side power source is disconnected, and a power outage condition of the D-side power source appears.

Next, the diagnostic operation will be explained in sequence.

(21) First, in the state during normal power transmission, the power source to which power is transmitted first is selected by the power source selection circuit (11), power is supplied to each part, and voltage is detected from the power source side and the load side. signal is being supplied. At this time, the first memory circuit (13) stores the output state and outputs the output at the same time as power is supplied. ), control power supply circuit (12), loop prevention circuit (23), first and second memory circuits (13), (24), output circuit (16)
, Y timer (17), Z1 timer (18), Y・Z
1 timer (17a) and Z2 timer (25).

If you want to create a simulated power outage state from this state,
ml is energized, the output relay MC is forcibly held, and the control circuit is disconnected at the contact m1b. This opens all circuits after the m1b contact, resulting in a power outage state.

(22) Progressive operation (■, ■) m, when the relay is opened and contacts m and b are closed, the memory circuit (
13) remembers the output state, so it outputs the output immediately. (P,: ON) (In this case, relay m9 is energized and contact mBb is opened.) As a result, (P3:0FF) → Stops X timer (15) Memory circuit (24) Reset input stops @X Timer (15) → INH.

The X timer maintains its output, but its output signal is INH,
The state that was cut by is continued. If a predetermined period of time has elapsed in this state, it is assumed that a normal power transmission state has been entered, and the functions of ■■ are determined to be normal.

(23) Locking operation for turning on power outage within Y time (■) During sequential operation, output circuit (16) is ON and relay m is activated during Y time schedule.
1 is deenergized and contact m is opened to indicate a power outage state, and the following operations stop. In this state, P3 remains OFF, and when relay m1 is deenergized and contact m□b is closed,
If the timer does not operate, that is, remains Pl: OFF even after X time has elapsed, it is determined that the lock operation, that is, the function (2) is normal.

(24) During power outage transfer lock operation during X time (■) During progressive operation, during clocking of X time, contact m, ) + open, contact m1lb open (contacts m and b are left open from the beginning) and the power outage state is established. Then, power is transmitted from the power source side (A side) -> power outage during X time -> memory circuit (24) is reset.

Next, when contact mBb is closed and contacts m, , b are closed to create a reverse feeding state, D control voltage detection circuit (22) → IN■-(, → INH engineering →
Memory circuit (13) Reset-lock (P, :0FF) P
3: Detects locking due to OFF and determines that locking operation is normal.

(25) Power-on lock operation during X time (■) Progressive operation During X time clocking (at this time, m1b closes, contact mBb closes), contact mBb closes 6P3: OFF detects that it is locked. , it is determined that the lock operation is normal.

(26) Z time operation Sequential feeding operation is completed and power is being transmitted normally, contacts m1b, mBb.

When m and b are respectively opened and each contact is returned to closed after Z time, signal P□ p2. If the state of p does not change, it is determined that the Z time operation is normal.

After the above diagnosis (21) to (26) is completed, the diagnosis is further repeated cyclically at predetermined time intervals.

If any of the above diagnostic items deviates from the predetermined result and is determined to be abnormal, it is output from the microcomputer (91) and displayed on the display bag fi (95), and the relay mi (i=10
．． 11. -13) and output to the operating device (10).

To reconfirm the diagnosis result, operate the arbitrary diagnosis input device (102) of the operating device (10) to return the abnormal output and display to blank and repeat the diagnosis, and if there is an abnormality, it will be displayed and output again. In this case, if the diagnosis in (21) to (26) is completed and there is no abnormality, it is determined that the relay m1 is normal.
．． After that, it is output to "normal output".

In addition, in the above, what is expressed as a relay or a relay contact may be a non-contact system such as a semiconductor, a magnetic amplifier, a magnetic storage device, etc., and what is generally used as a circuit opening/closing means can be used.

〔Effect of the invention〕

In the fault section detection controller installed in the distribution line, there is a means to automatically diagnose the self-function at regular intervals, a means to automatically diagnose the self-function by inputting the diagnosis from the outside, and a means to determine whether the function is normal or abnormal based on the diagnosis result. It is equipped with a means for outputting and displaying external information, and a means for functioning in place of the circuit in the event of an abnormality, so that when an abnormality occurs in the circuit, an alarm will be issued so that it can be easily discovered during patrols, and it can be quickly repaired and inspected. control) (:) to improve reliability,
It is possible to minimize damage caused by abnormal conditions occurring in power lines, power equipment, etc. in the distribution line, and to prevent adverse effects on other healthy sections.

[Brief explanation of drawings]

Fig. 1 is an integrated circuit diagram of the fault section detection device of the present invention;
FIG. 3 is a block diagram showing an embodiment of the present invention, FIG. 3 is an integrated circuit diagram of a conventional fault section detection device, and FIG. 4 is a block diagram showing a circuit example of a conventional fault section detection device controller (8). ,
FIG. S is an explanatory diagram of some elemental circuits. (1) Two-section switch, (2): Main contactor, (3): Closing electromagnetic coil, (4), (5): Operation transformer, (
6):f! ! Source side distribution line, (7): Load side distribution line,
(8): Controller, (81): Relay group, (82)
: Operating state detection means group, (9): Self-diagnosis device, (91
): Central processing unit (CPU), (92), (93
): Interface, (10): Self-diagnosis operation device, (101,): Circuit abnormality output device, (102):
Arbitrary diagnostic input device, CS: operation switch, SW: changeover switch, INH1 to INH,: inhibit circuit, C
S al, CS a2. CS b: Operation switch contact, m, b, m2a, m, 1 al, m3 c2.
m4a, mS al mS al m7 b p m
@ b Hrn g b : Opening/closing means (relay contact,
MC: Output relay, L: Indicator light, T, 'L'2.
T: Control transformer, A: Power supply side operation terminal, D: Load side operation terminal, B: Common operation terminal, C: Output operation terminal, E
, F: @operation power supply terminal, G: Primary control power supply terminal, G': 2
Next control power supply terminal, H: A voltage control voltage detection circuit output terminal JzD side voltage voltage detection circuit output terminal: X timer output terminal, P2: Y timer output terminal, P: first memory circuit output terminal.

Claims (1)

[Claims] 1. A power supply selection circuit that selects either the power supply side or the load side of the distribution line sectional switch, and is operated by the control power supplied from the power supply selection circuit to drive and control the sectional switch. The controller for the failure section detection device stores its own output state, and when a power outage occurs in the output state, the first memory circuit (13) outputs the output when the power is restored. X timer (15) that clocks a predetermined period of time
, an output circuit (16) that operates with the X timer output and drives the sectional switch, and a Y timer ( 17), each component circuit includes a first Z time circuit, that is, a Z_1 timer circuit (18), which temporarily stores the output of the output circuit (16) and restores the output in the event of a momentary power outage; 13) is reset by the output of the output circuit (16) and set by the output of the Y timer (17) so that it outputs in the set state, and each of the power supply side distribution line (6) and load side distribution line (7) Voltage detection circuit (2
1, 22), a second memory circuit (24) that is set by the output of the Y timer (17), reset by the output of the power supply side voltage detection circuit (21), and outputs the set state;
The inhibit circuit INH_4 is inserted into the reset signal circuit of the second storage circuit (24) and is given an inhibit signal by the output of the load side voltage detection circuit (22) and the output of the Y timer, which temporarily stores the inhibit signal output from the Y timer. and a second Z-time circuit, Z_, which supplies an output to the inhibit circuit INH_4 for a predetermined time after the power outage.
a 2-hour circuit (25), an inhibit circuit inserted into a reset signal circuit from the load-side voltage detection circuit (22) to the first storage circuit (13), and to which an inhibit signal is given by the output of the second storage circuit; INH_3, a fault section detection circuit equipped with a loop prevention circuit (23) that outputs a signal to reset the first storage circuit when receiving input from both the power supply side and load side voltage detection circuits (21, 22). In the equipment controller, an opening/closing means (m_1b
), opening/closing means (m_2a) that directly connects the output relay MC for closing the sectional switch to the primary control power source and forcibly maintains the closed state.
, an opening/closing means (m_3c_1) forming a diagnostic charging circuit in the energy storage power supply circuit (18a) of the Z_1 time circuit (18);
Opening/closing means (m_4a) for forcibly setting the memory circuit (13) using the stored energy power supply as a power supply; opening/closing means (m_4a) for forcibly giving a signal to the output terminal of the output circuit (16) from the primary control power supply;
m_5a), when the Z_2 time limit circuit (25) is in steady state, the energy storage power supply circuit (25a) is charged by the Y timer output,
At the time of diagnosis, the inhibit signal to the inhibit circuit INH_4 is opened and closed by the opening/closing means (m_6a) forming the charging circuit from the primary control power supply, the Y timer output, and the Z_2 timer output, and the moment the output of the power supply side voltage detection circuit is generated at the time of diagnosis. The opening/closing means (m_7b) is inserted into the voltage detection circuits (21, 22) on the power supply side and the load side to cut off the inhibit signal of the short-time inhibit circuit INH_4 and enable the reset of the second memory circuit (24). , the circuit (21,
22), opening/closing means (m_8b, m_9b) for forcibly opening/closing the output of the power supply side and load side distribution lines (6, 7), and these opening/closing means (m_1b,
m_2a, m_3c_1, m_3c_2, m_4a, m
_5a, m_6a, m_7b, m_8b, m_9b) A self-diagnosis device for a controller for a failure section detection device, characterized in that it is equipped with a central processing control unit (91) that performs program control. 2. A Z time circuit (17a) is attached to the Y timer (17) and restores its output in the event of a momentary power outage.
Opening/closing means (m_3) forming a charging circuit from the next control power source
c_2) and the second claim characterized in that
A self-diagnosis device for a controller for a failure section detection device according to item 1. 3. X timer output signal P_1, Y timer output signal P
_2. The fault section according to claim 1, characterized in that the output signal P_3 of the first storage circuit (13) is inputted to the central processing control unit (91) as data indicating the state of the fault section detection device. Self-diagnosis device for the controller for the detection device. 4. The controller for a fault section detection device according to claim 1, characterized in that it is equipped with a circuit abnormality display device (101) that displays diagnostic results based on the output of the central processing control device (91). Diagnostic equipment. 5. The controller for a failure section detection device according to claim 1, characterized in that it is equipped with a circuit abnormality output device (101) that outputs the diagnosis result to the outside based on the output of the central processing control device (91). self-diagnosis device. 6. For the failure section detection device according to claim 1, characterized in that the self-diagnosis device (9) is provided with an optional diagnostic input device (102) for arbitrarily providing an input for diagnostic operation from the outside. Controller self-diagnosis device. 7. A self-diagnosis device for a controller for a failure section detection device according to claim 1, characterized in that the self-diagnosis device is provided with switching means SW for switching and selecting the output of the second storage circuit (24).