JPS6265565A - Vertical deflection circuit - Google Patents

Abstract

PURPOSE:To always make agree the phase of a sawtooth voltage with a synchronizing signal and to attain an automatic synchronization with no adjustment even against the synchronizing signal, the cycle of which is changing, by using the voltage in proportion to the cycle of the synchronizing signal and making change the average value of a reference potential. CONSTITUTION:By controlling the charging/discharging operation of a capacitor 4 corresponding to the compared result by a comparator 6 between the first and the second reference potentials generate at a connecting point A between bleeder resistances 2 and 3 and the terminal voltage of the capacitor 4, the sawtooth voltage is generated and a sawtooth current Is is flowed from a vertical deflection circuit 11 to a deflecting coil 12. The voltage being proportional to the cycle of a synchronization signal Ps generated at a cascade connection circuit between a frequency voltage conversion circuit 13 and a buffer amplifier 14 is overlapped on the voltage on the connecting point A between the bleeder resistances 2 and 3 and the average value of the reference voltage is made change corresponding to the cycle of the synchronizing signal Ps. Even when the cycle of the synchronizing signal Ps is varied in a considerable wide range, the sawtooth voltage generated at the vertical deflection circuit 11 is automatically synchronized with the synchronizing signal Ps.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a vertical deflection circuit for deflecting an electron beam of a picture tube.

(Prior Art) A capacitor that generates a sawtooth voltage between its terminals when charging and discharging is performed, and a capacitor that rapidly a charging circuit that charges the capacitor; a discharging circuit that discharges the capacitor at a constant rate when the terminal voltage of the capacitor reaches a second reference potential higher than the first reference potential; a reference potential generation circuit that generates a first reference potential and a second reference potential;
In order to match the phase of the sawtooth wave voltage generated in the capacitor with the synchronization signal, means for superimposing the synchronization signal on the first reference potential described above, and means for amplifying the sawtooth wave voltage generated in the capacitor. FIG. 9 shows a conventional vertical deflection circuit in which a sawtooth wave current is passed through the deflection coil in addition to the deflection coil of the picture tube.

In FIG. 9, 31 is an input terminal for the synchronization signal Ps, 1 is a coupling capacitor, and 2 and 3 are bleeder resistors for determining the first reference potential Vl. 3 is connected between the operating power supply Vcc and ground, and the connection point A of the resistors 2 and 3 is connected to the inverting input terminal of the comparator 6, and to one contact of the electronic switch IO. It is connected. Further, the other contact point of the electronic switch 10 described above is connected to the power supply Vcc via a resistor 8 (oscillation acceleration resistor 8).

Further, the non-inverting input terminal of the comparator 6 described above is connected to one contact of the electronic switch 9, and the non-inverting input terminal of the comparator 6 described above is connected to A constant current source 5 and a vertical deflection circuit (2) are also connected to a capacitor 4 (hereinafter simply referred to as capacitor 4) which generates a sawtooth wave voltage between its terminals.

The other contact of the electronic switch 9 described above is connected to the power source cc via the charging resistor 7. Vertical deflection circuit 11
A vertical deflection coil 12 is connected to the output side of.

In the conventional vertical deflection circuit shown in FIG. 9, since there is no charge in capacitor 4 when the power is turned on, the terminal voltage of capacitor 4 is zero, and the voltage at the non-inverting input terminal of comparator 6 is zero. *IE is also zero. On the other hand, since the connection point A of the bleeder resistors 2 and 3 connected to the inverting input terminal No. 2 of the comparator 6 becomes the first reference voltage v1 when the power is turned on, the comparator 6 in this state Electronic switches 9 and 10 are turned on by the output of By connecting the resistor 8 in parallel to the bleeder resistor 2 by the electronic switch IO turned on, the voltage at point A has a relationship of Vl<V2 with respect to the first reference potential 1. The voltage is increased by 1 to a certain second reference potential (2). Time 11 in FIG. 1θ is the time point at which the power is turned on.

Capacitor 4 being charged by the charging circuit described above
, that is, the voltage at the non-inverting input terminal is the second
When the voltage at the inverting input terminal, which is the reference potential v2 of the electronic switch 9, is reached, the output of the comparator 6 is inverted, and the electronic switch 9. t
o are both turned off, so that the potential at point A becomes the first reference potential Vl determined by the bleeder resistor 2°3, and the voltage at the inverting input terminal of the comparator 6 becomes the first reference potential. The potential is set to Vt. In FIG. 10, time t2 is the point in time when the potential at point A changes from the second reference potential v2 to the second reference potential v2.

On the other hand, the accumulated charge of the capacitor 4, which has been charged by the above-described charging circuit until the terminal voltage reaches the second reference potential v2, is accumulated by the constant current source 5 from the time t2 when the electronic switch 9 is turned off as described above. Since the capacitor 4 is discharged at a constant rate, the terminal voltage of the capacitor 4 decreases linearly at a constant slope as shown in the period from time t2 to time t3 in FIG.

When the terminal voltage of the capacitor 4, that is, the voltage at the non-inverting input terminal of the comparator 6, reaches the voltage at the inverting input terminal of the comparator 6, that is, the first reference potential v1 at time t3,
At time t3, the output of comparator 6 is inverted and electronic switch 9.
10 both change to the on state at time t3.

Electronic switch after time t39. The on/off operation of the IO is the same as that described for the period from time 11 to t3 above, and the terminal voltage of the capacitor 4 becomes the sawtooth wave voltage Vs as shown in FIG. 10, which is the vertical deflection circuit. Vertical deflection circuit 1 by being supplied to 11
A sawtooth wave current Is flows through the deflection coil 12 connected to the output side of the deflection coil 12.

The period Tf of free-running oscillation in the circuit described above changes depending on the magnitude of the first reference potential v1, as can be seen from Fig. 1θ, and therefore, the period of the sawtooth wave voltage in this type of circuit can be adjusted. is usually a bleeder resistance 2,
This is done by changing the resistance value of No. 3.

Next, the operation when the periodic signal Ps is supplied to the input terminal 31 of the synchronizing signal Ps in the vertical deflection circuit shown in FIG. 9 will be described.

When the synchronizing signal Ps with the period Ts supplied to the input terminal 31 of the synchronizing signal Ps is applied to the point A via the coupling capacitor 1, the potential at the point A has a period similar to the first reference potential ■1 described above. Ts and the synchronization signal Ps are superimposed.

Now, Taru I! If the period Tf of the free-running oscillation in the IOi direction circuit is set to be slightly shorter than the period of the synchronization < d Ps, the #1
The period of the tooth wave voltage Vs is the input terminal 31 of the synchronization signal Ps.
It is well known that the cycle is made to match the period 1'S of the synchronizing signal Ps supplied to the point A via the coupling capacitor 1.

That is, as shown in FIG. 11, the period Tf of free-running oscillation in the vertical deflection circuit is equal to the period Tf of the synchronizing signal Ps.
s, the sawtooth wave voltage Vs generated in the vertical deflection circuit at the free-running oscillation period Tf is synchronized with the first reference potential V1 by the synchronizing signal Ps.
Since the output of the comparator 6 is inverted when the voltage value reaches the voltage value plus the peak value of Synchronization (i
It is made to match the period Ts of the f-number Pg.

However, if the period 1's of the synchronizing signal Ps is too long or too short compared to the free-running oscillation period Tf in the vertical deflection circuit, the fIIA tooth generated in the vertical deflection circuit The period of the wave voltage Vs cannot be made to match the period Ts of the synchronization signal Pg supplied from the input terminal 31 of the No. 1 Ps to the point A via the coupling capacitor l.

That is, if the period Tf of free-running oscillation in the vertical deflection circuit is too long compared to the period Ta of the synchronizing signal Ps, as shown in FIG. The voltage is the first reference potential ■1 and the synchronization signal Ps
fl which is oscillating at the free-running oscillation period Tf in the vertical deflection circuit in a state where the voltage value is the sum of the peak value of fl.
The voltage of the Aa wave voltage Vs is the ratio 624! i! 6
The voltage value of the inverting input terminal of , that is, the first reference potential v
1 plus the peak value of the synchronizing signal Ps, the output of the comparator 6 is not inverted, and the period of the sawtooth wave voltage Vs output from the vertical deflection circuit is , the original free-running oscillation period of 1゛f remains.

Also, contrary to the above case, if the period '1'f of free-running oscillation in the vertical deflection circuit is shorter than the period 1'S of the synchronous ffi signal Ps, as shown in FIG. Even if the voltage at the inverting input terminal of comparator 6 is
The sawtooth wave voltage ■s generated in the vertical deflection circuit at the free-running oscillation period Tf in a state where the voltage value is the sum of the reference potential Vl and the peak value of the synchronizing signal Ps is:
Since the voltage value at the inverting input terminal of the comparator 6 described above is higher than the voltage value obtained by adding the peak value of the synchronizing signal Ps to the first reference potential V1, the comparator 6 The output of the vertical deflection circuit is not inverted, and the period of the sawtooth wave voltage Vs output from the vertical deflection circuit remains the original free-running oscillation period of 1°f.

Therefore, the synchronizing signal P's is fully supplied from the input terminal 31 of the synchronizing signal I's to the point A via the coupling capacitor 1.
If the period Ts of s is too long or too short compared to the period Tf of free-running oscillation of the sawtooth voltage generated in the vertical deflection circuit, adjust the bleeder resistors 2 and 3. It is necessary to bring the free-running oscillation period 'l'I' of the sawtooth voltage generated in the vertical deflection circuit close to the period Ts of the synchronous signal qPs, and for this purpose, the ninth Any of the rotary variable resistors 2.3 in the figure is used as a vertical synchronization regulator to change the first reference potential (2).

(Problem to be Solved by the Invention) The solution described above is such that when the vertical scanning period is fixed to a specific value, for example, the system is configured to operate according to a specific standard television format. However, in recent years, for example, it has become possible to achieve good vertical synchronization adjustment when applied to television receivers that are When various frequencies are used in a wide frequency range such as the vertical scanning frequency of 5011z to 9011z, such as a display device in computer-related equipment that has become widespread, the above-mentioned wide frequency Even if you try to adjust the free-running oscillation frequency in the vertical deflection circuit by applying the above-mentioned solution to the range, it will be difficult to adjust within the variable range of adjustment, so it is difficult to adjust the free-running oscillation frequency in the vertical deflection circuit. It is necessary to set different circuit constants for each different vertical scanning frequency. Therefore, when producing the above-mentioned equipment, it is necessary to adopt the production mode of multi-product sunset view production to improve the equipment's performance. Production had to be carried out, which inevitably led to higher costs.

(Means for Solving the Problems) The present invention provides a capacitor that generates a sawtooth voltage between terminals when charging and discharging is performed, and a voltage between the terminals of the capacitor that reaches a first reference potential. a charging circuit that rapidly charges the capacitor when
a discharge circuit that discharges the capacitor at a constant rate when the terminal voltage of the capacitor reaches a second reference potential higher than the first reference potential;
A reference potential generation circuit generates a reference potential and a second reference potential, and a synchronization signal is applied to the first reference potential in order to match the phase of the sawtooth wave voltage generated in the capacitor with the synchronization signal. and a vertical deflection circuit which amplifies the 11M tooth wave voltage generated in the capacitor and causes a saw tooth wave current to flow through the deflection coil in addition to the deflection coil of the picture tube. Provided is a vertical deflection circuit that generates a voltage proportional to , changes the 1V average value of the first reference potential, and always matches the phase of the sawtooth wave voltage generated in the capacitor with the synchronization signal. It is something to do.

(Example) Hereinafter, specific details of the vertical deflection circuit of the present invention will be explained.
A detailed description will be given with reference to the accompanying drawings.

FIG. 1 is a block diagram of an embodiment of the vertical deflection circuit of the present invention, and in FIG. 1, each component corresponds to the conventional vertical deflection circuit described with reference to FIG. The same drawing numerals as those used in FIG. 9 are used for each component.

In the first episode, 31 is an input terminal for the synchronization signal Ps, 1 is a coupling capacitor, and 2 and 3 are bleeder resistors, and the bleeder resistors 2 and 3 are connected to the operating power supply Vcc.
and ground, and the connection point A of the resistors 2 and 3 is connected to the inverting input terminal of the comparator 6, as well as the output side of the buffer amplifier wI+4 and the electronic switch 10, which will be described later. is also connected to one of the contacts. The other contact of the electronic switch IO described above is connected to the power supply Vcc via a resistor 8 (oscillation acceleration resistor 8).

Further, the non-inverting input terminal of the comparator 6 described above is connected to one contact of the electronic switch 9, and the non-inverting input terminal of the comparator 6 described above.

A capacitor 4 (hereinafter simply referred to as capacitor 4), which generates a tlA tooth wave voltage between terminals by charging and discharging, is also connected to a constant current source 5 and a vertical deflection circuit 11. The other contact of the electronic switch 9 described above is connected to the voltage gvcc via the charging resistor 7. A vertical deflection coil 12 is connected to the output side of the vertical deflection circuit 11 .

In FIG. 1, reference numeral 13 denotes a frequency-voltage conversion circuit, and this frequency-voltage conversion circuit 13 is supplied with a synchronization signal Ps from an input terminal 31 for the synchronization signal Ps, and the output from the frequency conversion circuit 13 is The signal is applied to the buffer amplifier 14, and the output signal from the buffer amplifier 14 is applied to the connection point A of the bleeder resistor 2.3 as described above.

As can be readily understood by comparing the vertical deflection circuit of the present invention shown in FIG. 1 with the conventional vertical deflection circuit described with reference to FIG. This corresponds to a cascade connection circuit of a frequency-voltage conversion circuit 13 and a buffer amplifier 14 connected between the connection point A of the bleeder resistors 2 and 3 in the vertical deflection circuit and the input terminal 31 of the synchronization signal Ps. However, in the vertical deflection circuit of the present invention, the frequency-voltage conversion circuit 13 and the buffer amplifier 14 are connected in cascade between the connection point A between the bleeder resistors 2 and 3 and the input terminal 31 of the synchronization signal Ps. By superimposing a voltage proportional to the period TS of the synchronizing signal Ps generated in the circuit on the voltage being generated at the connection point A between the bleeder resistors 2 and 3, Even if the average value of the reference voltage is changed and the period of the synchronization signal Ps supplied to the input terminal 31 of the synchronization signal Ps of the vertical deflection circuit changes over a predetermined considerable range, the signal generated in the vertical deflection circuit will not be affected. The sawtooth wave voltage Vs automatically becomes synchronized with the synchronization signal Ps.

In other words, in the conventional vertical deflection circuit shown in FIG. 9, the first . second reference potential V
In the vertical deflection circuit of the present invention shown in which 1.l and V2 are respectively predetermined, the first . Of the second reference potentials Vl and V2, the first reference potential Vl is
It is automatically changed in accordance with the period Ts of the synchronizing signal Ps supplied to the input terminal 31 of the synchronizing signal Ps of the vertical deflection circuit. However, in both the vertical deflection circuit shown in FIG. 1 and the vertical deflection circuit shown in FIG. 9, the first . The charging/discharging operation of the capacitor 4 is controlled according to the comparison result between the second reference potential and the terminal voltage of the capacitor 4.

Since the sawtooth wave voltage Vs is still generated, a general description of the operation of generating the sawtooth wave voltage ■s in the vertical deflection circuit of the present invention shown in FIG. 1 will be omitted.

Figure 2 shows that the free-running oscillation period Tf in the vertical deflection circuit is
When the period Ts of the synchronizing signal Ps supplied to the input terminal 31 of the synchronizing signal P8 is approximately equal to the period Ts, the vertical deflection is 3 is a diagram showing that the period Ts of the sawtooth wave voltage Vs generated in the circuit is made equal to the period Ts of the synchronization signal Ps supplied to the input terminal 31 of the synchronization signal Ps, and FIG. 9 is a conventional vertical deflection circuit shown in FIG. If the period of the sawtooth wave voltage Vs output from the vertical deflection circuit is too high, as explained with reference to FIGS. The period Tf of the free-running oscillation in the vertical deflection circuit is determined by the synchronization signal P5 so that the period Tf of the free-running oscillation in the vertical deflection circuit remains the same regardless of the period Ta of the signal Ps.
The period T of the synchronizing signal P5 supplied to the input terminal 31 of
Taking as an example a case where the length is too long compared to s' (same as the case in FIG. 12), this is described for comparison with FIG. 4, which is shown to explain the operating principle of the vertical deflection circuit of the present invention. It is.

FIGS. 5 and 7 are circuit diagrams showing different configuration examples of the frequency-voltage conversion circuit 13 and the buffer amplifier 14, respectively. In the frequency-voltage conversion circuit 13 and buffer amplifier 14 shown in FIG. is a smoothing capacitor, 22 is an emitter follower stage transistor, 23 is an emitter resistor, 2
4 is a next-stage input resistor, 25 is an inverting film transistor, and 32 is a resistor.

In the frequency conversion circuit No. 13 shown in FIG. 5, when the synchronizing signal Ps is supplied to the base of the switching transistor 17 via the coupling capacitor 15, the switching transistor 17 operates during the period of the synchronizing signal Ps. The switching transistor 17 becomes conductive, and the charge accumulated in the charging/discharging capacitor 19 connected between the collector and ground is discharged by the switching transistor 17 which is in the conductive state.
The potential of the collector of the switching transistor 17, that is, the voltage at point B becomes approximately zero.

When the synchronization signal Ps period has passed, the charging/discharging capacitor 19 is connected to the resistor 1 via the resistor 18 connected to the power supply vCC.
8 and the charging/discharging capacitor 4, and the voltage at point B gradually rises as shown in FIG. 6(a). The voltage at point B mentioned above is suddenly brought to zero as described above by supplying the next synchronizing signal Ps to the frequency-voltage conversion circuit 13 and turning on the switching transistor 17.

Therefore, the potential of the collector of the switching transistor 17, that is, the voltage at point B is the voltage of the frequency-voltage conversion circuit 1.
This is a sawtooth wave voltage having the same repetition period as the repetition period of 1 s of the synchronizing signal Ps inputted to the synchronous signal Ps.

The sawtooth wave voltage shown in FIG. 6(a) generated at the collector of the switching transistor 17 as described above is caused by the synchronization signal Ps input to the frequency-voltage conversion circuit 13 as described above. Since the voltage is a sawtooth wave voltage with the same repetition period as the repetition period Ts, the synchronization signal Ps with the repetition period Ts shown in FIG. 6(b) is input to the frequency-voltage conversion circuit 13. In this case, the sawtooth wave voltage generated at the collector of the switching transistor 17 becomes as shown by the solid line in FIG. The synchronization signal P with the repetition period Ts' shown in (C) of
When g' is input, the sawtooth wave voltage generated at the collector of the switching transistor 17 is as shown in FIG.
a) It will look like the dotted line diagram in the middle.

The sawtooth wave voltage generated at the collector of the switching transistor 17 as described above is smoothed by a smoothing circuit constituted by a smoothing resistor 20 and a smoothing capacitor 21, and is thereby applied to a point C on the output side of the smoothing circuit. A DC voltage Vf corresponding to the average value of the sawtooth wave voltage generated at the collector of the switching transistor 17 is generated.

The DC voltage Vf generated at the six points described above has a voltage value that is inversely proportional to the repetition period of the synchronization signal Ps supplied to the frequency-voltage conversion circuit 13. Therefore, the buffer amplifier 14 in FIG. 5 is configured to invert the polarity of the voltage Vf appearing at the six points mentioned above and output it.

That is, the buffer amplifier 14 in FIG.
The voltage at the six points mentioned above is applied to the transistor 22 of the emitter follower stage.
A voltage of the same polarity as [II is generated at the emitter of
A voltage whose polarity is inverted from the voltage at point D appears on the collector side of No. 5, and is supplied to point A.

In this way, the voltage generated by the circuit arrangement shown in FIG. 5 has a pressure value proportional to the repetition period of the synchronization signal Ps supplied to the frequency-voltage conversion circuit 13.

Next, in the frequency-voltage conversion circuit 13 and buffer amplifier 14 shown in FIG. 7, 26 is a monostable multivibrator, 27 is a smoothing resistor, 28 is a smoothing capacitor, 29 is an emitter follower stage transistor, and 3o is an emitter resistor. In the frequency-voltage conversion circuit 13 shown in FIG. 7, the monostable multipipe brake converter 26 generates an output pulse among predetermined pulses every time the synchronizing signal Ps is supplied thereto.

The time in the monostable multivibrator 26 is adjusted so that the output pulse from the monostable multivibrator 26 described above is shorter than the shortest cycle of the synchronization signal input to the vertical deflection circuit. A constant is set.

When the frequency-voltage conversion circuit 13 shown in FIG. 7 is supplied with a synchronization signal Ps having a repetition period of the synchronization signal P8 as shown in (,) of FIG. 8, the monostable multivibrator 26 is triggered every synchronization signal Pg, and the one-frequency voltage conversion circuit 13 is connected to the point E on the output side of the monostable multivibrator 26 as shown in FIG. 8(b).
A pulse Pd having a repetition period Ts which is the same as the repetition period Ts of the synchronization signal Ps supplied to the synchronous signal Ps and which always has a constant Td in the pulse is outputted.

The pulse Pd of Td among the pulses generated at the point E on the output side of the monostable multivibrator 26 as described above is smoothed by a smoothing circuit constituted by a smoothing resistor 27 and a smoothing capacitor 28. At point F on the output side of the smoothing circuit, the average value of the voltage of the pulse Pd having the same repetition period Ts as the repetition period Ts of the synchronizing signal Ps supplied to the frequency-voltage conversion circuit 13 and always having a constant pulse riTd is applied. A corresponding DC voltage Vf is generated.

The DC voltage Vf generated at the point F has a voltage value proportional to the repetition period Ts of the synchronization signal Ps supplied to the frequency-voltage conversion circuit 13. The buffer amplifier 14 in FIG. 7 amplifies the voltage Vf appearing at the point F using the transistor 29 in the emitter follower stage and supplies the amplified voltage to the point A.

In this way, the voltage generated by the circuit arrangement shown in FIG. 7 has a positive value proportional to the repetition period of the synchronization signal Ps supplied to the frequency-voltage conversion circuit 13.

(Effects) As is clear from the above detailed explanation, the vertical deflection circuit of the present invention generates a sawtooth wave voltage between the terminals by charging and discharging when the first reference potential is reached. a charging circuit that rapidly charges the capacitor; and a charging circuit that discharges the capacitor at a constant rate when the terminal voltage of the capacitor reaches a second reference potential that is higher than the first reference potential. with a discharge circuit.

A reference potential generation circuit that generates the first reference potential and the second reference potential described above, and the first reference described above in order to match the phase of the sawtooth wave voltage generated in the capacitor with the synchronization signal. Synchronization is achieved in a vertical deflection circuit which includes a means for superimposing a synchronization signal on the potential and a sawtooth wave voltage generated in a capacitor and causes a sawtooth wave current to flow through the deflection coil in addition to the deflection coil of the picture tube. A voltage proportional to the period of the signal is generated to change the average value of the first reference potential, and the phase of the r-wave voltage generated in the capacitor is always made to match the phase of the synchronizing signal. Since the vertical deflection circuit of the present invention is a circuit, it is possible to automatically synchronize without adjustment even to a synchronization signal whose period changes over a wide range, and according to the present invention, the above-mentioned conventional problems can be solved. points can be resolved well.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of an embodiment of the vertical deflection circuit of the present invention, FIGS. 2 to 4, FIGS. 6 and 8, and FIGS. 10 to 13 are waveform diagrams for explaining operation. 5 and 7 are block diagrams of a frequency-voltage conversion circuit, and FIG. 9 is a block diagram of a conventional vertical deflection circuit.

Claims (1)

[Claims] A capacitor that generates a sawtooth voltage between terminals when charging and discharging is performed, and a charging circuit that rapidly charges the capacitor when the voltage between the terminals of the capacitor reaches a first reference potential. , a discharge circuit that discharges the capacitor at a constant rate when the terminal voltage of the capacitor reaches a second reference potential higher than the first reference potential; and the first reference potential. a reference potential generation circuit that generates and a second reference potential;
In order to match the phase of the sawtooth wave voltage generated in the capacitor with the synchronization signal, there is provided means for superimposing the synchronization signal on the first reference potential, and a means for amplifying the sawtooth wave voltage generated in the capacitor to generate a picture tube. In a vertical deflection circuit that causes a sawtooth wave current to flow through the deflection coil in addition to the deflection coil, a voltage proportional to the period of the synchronizing signal is generated to change the average value of the first reference potential. , a vertical deflection circuit that always matches the phase of the sawtooth wave voltage generated on the capacitor with the synchronization signal.