JPS6264963A - Control circuit of shortcircuit detection/display apparatus - Google Patents

Abstract

PURPOSE:To remove the adverse effect of a wrong detection/display apparatus and to enhance reliability for discovering a trouble point at an early stage, by self-diagnosing a shortcircuit detection circuit and displaying the abnormality of a check display device when the circuit is out of order. CONSTITUTION:The control circuit of a display apparatus allows the shortcircuit detection part 68 consituting a shortcircuit detection control circuit to perform shortcircuit display on the basis of the detection signal outputted from a current detector when a shortcircuit current flowed to a distribution line. The first-third check signal generating circuits 78-80 of a self-diagnosis circuit 77 inject check signals in the first-third shortcircuit detection circuits Xa-Xc of the detection part 68 and a check signal comparing circuit 81 compares the signals applied from the circuits Xa-Xc with the check signals on the basis of the check signals through a shortcircuit discriminating circuit 70. When both of them coincide, a check display device Hc performs normal display and, when both signals do not coincide, the display device Hc displays abnormality.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a control circuit for a short circuit detection and display device attached to a power distribution line. .

(Prior Art) Conventionally, short circuit detection and display devices have been used for the purpose of early IQ detection of short circuit failures in power distribution lines. However, it has not been possible to determine whether or not the display device is operating normally, that is, whether or not the display device's circuitry is malfunctioning through regular periodic inspections. Therefore, the discovery of a malfunction detection display device had to be determined based on the actual fault condition of the power distribution line and the operating status of the display device. For this reason, there was some uncertainty in finding fault points in power distribution lines.

(Problems to be Solved by the Invention) The present invention makes it possible to discover a defective detection display device through periodic inspection, and detects the uncertain factors that conventional display devices have, that is, the defect detection that affects the detection of fault points in power distribution lines. This eliminates the negative effects of display devices. Furthermore, even if a distribution line failure occurs without periodic inspection, it is easy to determine whether the detection display device is operating normally or abnormally by checking the detection operation status and the fault diagnosis display. Reliability for early detection of failure points is improved.

Structure of the Invention (Means for Solving the Problems) This invention has been made to solve the above problems, and the i and ++ control circuits of the short circuit detection display device of the present invention detect short circuit current in the distribution line. A short circuit detection display device that displays a short circuit using a short circuit detection control circuit based on a detection signal output by a current detector when a current detector flows, a check signal generation circuit that generates a check signal and injects it into the 11111 circuit; The check signal injected from the signal generation circuit is compared with the signal output from the control circuit based on the check signal injected into the control circuit, and when the two match, a check indicator is displayed. Its essential feature is that it is equipped with a self-diagnosis circuit consisting of a check chair number comparison circuit that displays a normal display and also displays an abnormal check display on a check display when the two signals do not match.

(Function) With the above configuration, the check signal generation circuit of the self-diagnosis circuit injects a check (no. The check signal injected from the check signal generation circuit is compared and determined.

As a result of the comparison, the check signal comparison circuit causes the check indicator to display a normal display when the two signals match, and causes the check indicator to display an abnormal display when the two signals do not match.

(Embodiments) First Embodiment Hereinafter, an embodiment in which the present invention is embodied in a short circuit/ground fault direction detection/display device will be described with reference to FIGS. 1 to 5.

(Detector) In Fig. 1, the detector of the short-circuit/ground fault direction detection and display device will be explained first. Second and third current transformers CT1. Cr2. C70, a zero-sequence current transformer 85 for detecting zero-sequence current flowing through the distribution line, and a zero-sequence voltage detector 86.

Kanji No. 1 - 2nd and 3rd current transformers CTI, CT2. C
T3 is designed to output a metamorphic ignition from its secondary side when a short-circuit current flows through the distribution line.

(υ Control Circuit) The control circuit is roughly divided into a short circuit detection section 68 that constitutes a short circuit detection control circuit. A no-voltage detection section 69 and a short circuit determination circuit 70,
A self-diagnosis circuit 7 that diagnoses a short-circuit indicator Ha drive circuit that drives the short-circuit indicator Ha and the short-circuit detection control circuit.
7, a check indicator 1-1c that displays the comparison and discrimination results of the self-diagnosis circuit 77, a display lock circuit 76 that does not display the short circuit indicator Hc in the case of a check signal, and a zero-phase voltage and a phase comparison/discrimination circuit 84 that compares the phases of zero-sequence currents, a drive circuit for a ground fault direction indicator that drives a ground fault direction indicator based on the discrimination result of the phase comparison/discrimination circuit 84, a short circuit indicator Ha, and a ground fault. It is comprised of a timer circuit 93 for restoring the display of the direction indicator, a timer control circuit 104 for controlling the simultaneous timer circuit, and a power supply circuit 97.

Hereinafter, each part will be explained in detail according to the drawings.

(2) Short circuit detection section The short circuit detection section 68 includes the first, second and third short circuit detection circuits X.
It is composed of a, xb, and XC.

First, the first short circuit detection circuit Xa will be explained.

a full-wave rectifier 3 connected to the first current transformer CT1;
A parallel circuit of a smoothing capacitor C1 and a resistor R1 is connected between the positive and negative terminals of the circuit. Similarly, a diode D1 is connected between the positive and negative terminals of the full-wave rectifier 3.
．． Parallel circuit of variable resistor R2 and resistor R3, selector switch S
1. Resistor R4 and photocoupler PC light emitting diode L
A series circuit consisting of ED and ED are connected. By selectively connecting the changeover switch S1 to the variable resistor R2 or variable resistor R3 side, this short circuit ground fault direction detection display device can be attached to distribution lines through which different steady load currents flow. ing.

Also, the negative terminal of the diode D1 and the gold wave rectifier '? A capacitor C2 is connected between the negative terminal of the device 3.

A series circuit consisting of the emitter/collector of a switching transistor Tr1 and a resistor R5 connected via the collector is connected between an output terminal Pi (plus terminal) of a power supply circuit Z (described later) and a ground line E1. The collector-emitter of the phototransistor PTr in the photocoupler PC is connected between the ground &E1 and the base terminal of the switching transistor Tri.

The collector-emitter of a switching transistor Tr2 is connected between an output terminal P1 (plus terminal) of a power supply circuit Z (described later) and a ground line E1. A series circuit of resistors R9 and RlO is connected between both terminals of the resistor R5, and the positive terminal of the resistor R10 is connected to the base terminal of the switching transistor Tr2. Further, a capacitor C3 is connected between both terminals of the resistor R10.

Therefore, when a short-circuit current flows through the distribution line, the first current transformer CT1 outputs a transformed current based on the short-circuit current, and the full-wave rectifier 3 performs full-wave rectification of the transformed current. The photocoupler PC receives the full-wave rectified analog signal and outputs it as a digital signal using a light emitting diode LED and a phototransistor PTr.

Furthermore, when the level of the digital signal applied to the base terminal is a predetermined value, the switching transistor Tr1
turns on and outputs a short-circuit current detection signal. And the switching transistor Tr1
When the switching transistor Tr2 is turned on, the voltage of the resistor RIO is applied to the base terminal of the switching transistor Tr2, so that the switching transistor Tr2 is turned on.

The resistors R1 to R5, R9, R10, photocoupler PC
, switching transistor TrlTr2, capacitors C2 and C3, etc. constitute a current discrimination switching circuit 71 in FIG.

The rectifier circuit 3 and the current discrimination switching circuit 71 constitute a first short circuit detection circuit Xa.

Since the second short-circuit detection circuit xb and the third short-circuit detection circuit Xc are configured in the same manner as the first short-circuit detection section, the same configurations are denoted by the same reference numerals and the explanation thereof will be omitted. Note that in the third short circuit detection circuit XC, a resistor R11 is connected between the resistor R1 and the negative terminal of the full-wave rectifier 3.

■, No-voltage detection section Next, the no-voltage detection section will be explained.

In the third short circuit detection circuit XC, a diode array [)a is connected between the negative terminal of the resistor R1 and the negative terminal of the gold wave rectifier 3, and a diode array [)a is connected between the positive terminal side of the diode array Da and the negative terminal of the full wave rectifier 3. A series circuit of resistors R12 and R13 is connected to. Further, the collector-emitter of a transistor Tr3 is connected between the output terminal P1 of a power supply circuit to be described later and the negative terminal of the full-wave rectifier 3, and the positive terminal of the resistor R13 is connected to the base terminal of the transistor Tr3. Furthermore, the resistance R
Capacitors C4 and C5 are connected between both terminals of 13.

A series circuit of a NOT circuit 5 and an inverter 6 is connected to the collector of the transistor Tr3.

When the power distribution line is in a steady state, the voltage between the diode array D8 is divided by the resistors R12 and R13, and the transistor Tr3 becomes conductive by applying the voltage of the resistor R13 to the base terminal, and the diode array [ )
The signal between 8 and 8 is voltage amplified and applied to the input terminal of the knot circuit 5.

When the M-disconnector of the substation trips due to a short-circuit failure or the like in the distribution line, the voltage across the diode array [ ) 8 becomes no voltage, so the base terminal of the transistor Tr3 receives the voltage of the resistor R13 (i.e. no voltage). ) is applied,
The transistor Tr3 is turned off. Then, the transistor Tr3 is turned off and the potential between the collector and emitter of the transistor Tr3 increases, so that a signal corresponding to the logic value 1 is applied to the NOT circuit 5.

Therefore, a signal corresponding to the logic value 0 is output from the output terminal of the NOT circuit 5, and the inverter 6 rectangulates the waveform based on the signal corresponding to the logic value 0, and the logic flill
A signal corresponding to 1 (no-voltage detection signal) is output.

The die A-door array Da, resistors R11 to R14, capacitors C4 and C5, and transistor Tr3 constitute a no-voltage detection circuit 72, and the knot circuit 5 and inverter 6 constitute a second waveform manipulation circuit. .

■、Short circuit detection circuit Next, the first to third short circuit detection circuits Xa and Xb.

The short-circuit current detection signal, which is a digital signal output from the XC, and the short-circuit determination circuit 70, which receives the no-voltage detection signal from the no-voltage detection circuit 72 via the second waveform manipulation circuit 73, will be described.

The collector terminals of the switching transistors Tr2 in each of the short circuit detection circuits Xa, Xb, and XC are connected to an OR circuit 8 via a NOT circuit 7, respectively. and,
A NOT circuit 9 is connected to the output terminal of the OR circuit 8, and the output terminal of the NOT circuit 9 is connected to one input terminal of a NAND circuit 10.

Further, the output terminal of the NOT circuit 9 and the NAND circuit 10
A series circuit of resistors R15, R16 and a NOT circuit 11 is connected between the other input terminals of the resistor R16, and a capacitor C6 is connected between the positive terminal of the resistor R16 and the ground wire E2.

Between the output terminal of the NAND circuit 10 and one input terminal of the AND circuit 13 as a short-circuit detection gate circuit, there is a series circuit including a NOT circuit 12 as a first waveform manipulation circuit 74, a diode D2, a resistor R17, and a resistor R18. is connected. Note that the output terminal P1 of the power supply circuit 97 is connected to the positive terminal of the diode D2 via a resistor R19. A parallel circuit consisting of a resistor 1 (20) and a capacitor C7 is connected between the positive terminal of the resistor R18 and the ground wire E2, and a resistor corresponding to a logic value 1 is connected to the input terminal of the AND circuit 13 for a predetermined time depending on the time constant of the CR circuit. R20
It is designed to apply a voltage of .

1) A signal memory circuit 75 is constituted by the resistor R20 of I3 and the capacitor C7.

The above-mentioned NOT circuit 12 (first waveform manipulation circuit), signal memory circuit 75, AND circuit 13 (short circuit detection gate circuit)
A short-circuit determination circuit 70 is configured by the above.

IV. Drive circuit for short-circuit indicator Next, the drive circuit for short-circuit indicator Ha will be explained. The output terminal of the AND circuit 13 is connected to one input terminal of the NAND circuit 15.

Further, the output terminal of the AND circuit 13 and the NAND circuit 1
A series circuit of a resistor R21°R22 and a NOT circuit 16 is connected between the other input terminals of the resistor R22, and a capacitor C8 is connected between the positive terminal of the resistor R22 and the ground wire E2.

A NOT circuit 18 is connected to the output terminal of the NAND circuit 15, and an output terminal of the NOT circuit 18 is connected to the AND circuit 1.
It is connected to one input terminal of 7. Same AND circuit 1
The output terminal of 7 is connected to the input terminal of an OR circuit 55, which will be described later. Further, a switching transistor Tr is connected between the output terminal P1 of the power supply circuit 97 and the negative terminal of the full-wave rectifier 3.
A series circuit of a set terminal 19 and a common terminal 20 of the short-circuit indicator 1-1a is connected to the collector/emitter of the short-circuit indicator 1-1a.

The output terminal of the AND circuit 17 is connected to the base terminal of the switching transistor Tr4 via a resistor R23, and a resistor R24 is connected between the negative terminal of the resistor R23 and the ground wire E2.
24 voltage is applied to the base terminal of the switching transistor Tr4.

Therefore, the AND circuit 13 outputs the logic 1iff1 from the second waveform manipulation circuit 73 of the no-voltage detection section while the signal corresponding to the logic value 1 from the signal memory circuit 75 is applied.
When a signal @ (non-voltage detection signal) corresponding to is applied, a signal corresponding to the logical value 1 is applied to the short-circuit display switching circuit 98 based on both signals.

A switching circuit 98 for short circuit indication is constituted by the NOT circuits 16 and 18, the NAND circuit 15, the AND circuit 17, the resistors R21 to R24, and the capacitor C8.

In addition, the output terminal P1 of the power supply circuit 97 described later and the short circuit indicator Ha
A switching transistor T is connected between the reset terminal 21 of
The collector and emitter of r11 are connected. The output terminal of the OR circuit 60 is connected to the base terminal of the switching transistor Tr11, and a resistor R is connected between the base terminal and the negative terminal of the gold wave rectifier 3.
65 is connected, and the voltage of the resistor R65 is applied to the base terminal of the switching transistor Tr11.

Then, the OR circuit 60 outputs a signal 5 corresponding to the logical value 1.
When iq6 (display return signal) is applied, a signal corresponding to the logical value 1 is applied to the next stage, thereby applying the voltage of the resistor R65 to the base terminal and turning on the switching transistor Tr11. As a result, a display return drive current is supplied from the switching transistor l''rll to the reset terminal 21 of the short circuit indicator 1a.

The OR circuit 60. Switching circuit 9 for display recovery using resistor R63, switching transistor Tr11, etc.
9 constitutes a driving section of the short circuit indicator Ha together with the short circuit indicating switching circuit 98.

■、Short circuit indicator The short circuit indicator Ha will now be explained with reference to FIG.

The short circuit indicator)-1a is composed of a plurality of magnetic reversal indicators. When a short-circuit display drive current flows through the set terminal 19 in each magnetic reversal display, each drive coil 25 is energized and has a polarity opposite to that shown in FIG.
4a is magnetized as an S pole, and the magnetic pole part 24b is magnetized as an N pole.
The poles are reversely rotated so as to face the magnetic pole part 24b (N pole), and the marks attached to the surface 22b of each disk 22 are displayed simultaneously to the outside (short circuit display).

In addition, on the contrary, the short circuit indicator Ha is reset via the reset terminal 21! When the PIJ current flows, each return drive coil 21
is excited, and the magnetic pole portion 24a becomes N 1 as shown in FIG.
4, the magnetic pole part 24b is magnetized to S#ji, and each disk 22 is reversely rotated so that its N pole faces the magnetic pole part 24a (N pole) and its S pole faces the magnetic pole part 24b (S pole). is,
The marks attached to the surface 21a of each disk 22 are constantly displayed externally all at once.

Vl, self-diagnosis circuit Next, the self-diagnosis circuit 77 will be explained.

This self-diagnosis circuit 77 includes each short circuit detection circuit Xa.

Xb, Xck: Chixtuku signal j3sig1.51g2゜3
1g3 (check current), and short circuit detection circuits Xa, Xb, Xc via a short circuit determination circuit based on the check signal.
It is comprised of a check signal comparison circuit 81 that compares a signal applied from the above with the check signal, and a check indicator switching circuit 82.

Note that since the check signal generation circuits 78 to 80 connected to each short circuit detection circuit Xa, Xb, and Xc have the same configuration, the first check signal generation circuit 78 connected to the first short circuit detection circuit Xa will be explained. In the second and third check signal generating circuits 79 and 80, the same components are given the same reference numerals and the explanation thereof will be omitted.

The IC27 constituting the first check signal generation circuit 78 is connected to the output terminal P1 of the power supply circuit 97, and the oscillation circuit 2 includes a resistor R25, a capacitor C9, and a resistor 26.
8 are connected, and the IC 27 divides the number of excavations of the oscillation circuit 28. Furthermore, the clear terminal 31 of this IC27 is connected to the negative terminal of the full-wave rectifier via a resistor R29. Therefore, this IC 27 divides the number of excavations of the constant oscillation circuit 28.

Further, one input terminal of a NAND circuit 29 is connected to the output terminal of the IC 27, and resistors R27 and R2 are connected between the other terminal of the NAND circuit 29 and the output terminal of the IC 27.
A series circuit of 8 and a knot circuit 30 is connected, and a resistor R2
A capacitor C10 is connected between the positive terminal of 8 and the negative terminal of the gold wave rectifier 3.

The collector and emitter of a switching transistor Tr5 are connected to an output terminal P1 of a power supply circuit 97, which will be described later, and a positive terminal of a light emitting diode LED in the photocoupler PC of the first short circuit detection circuit Xa. A NOT circuit 32 is connected between the base terminal of the switching transistor rr5 and the output terminal of the NAND circuit 29. Further, a resistor R32 is connected between the base terminal of the switching transistor Tr5 and the negative terminal of the gold wave rectifier 3.

Therefore, the IC 27 divides the number of shots of the constant oscillation circuit 28 and applies a signal corresponding to the logical value 1 from its output terminal to one terminal of the NAND circuit 29 at predetermined intervals. Further, No. 13 corresponding to the logic WA1 is applied to the NOT circuit 30 by the time constant of the resistor R27 and the capacitor C10, and the NOT circuit 30 operates two NAND circuits based on the signal corresponding to the logic Mi1. A signal corresponding to the logical value O is applied to the other terminal. Then, the NAND circuit 29 applies one pulse signal corresponding to the logic 1flIO to the NOT circuit 32 based on the signals applied to both terminals.

Then, the NOT circuit 32 applies a signal corresponding to the logic value 1 to the next stage based on the pulse signal corresponding to the logic 1fJO. Then, the switching transistor T
r5 is a resistor R3 based on the signal corresponding to the logic value 1.
When the voltage No. 2 is applied, it turns on (conducts). As a result, a check signal 5iq is sent to the first short circuit detection circuit Xa via this switching transistor Tr5.
1 (check current) is injected.

In addition, the second and third check signal comparison circuits 79.80
Similarly to the first check signal generation circuit 78, 51g2 and 5iQ3 are respectively connected to the second and third short circuit detection circuits X.
b, Inject into Xc.

Next, the check signal comparison circuit 81 will be explained.

The output terminal of each NOT circuit 32 in the first to third check signal generation circuits 79 to 80 is connected to the input terminal of an OR circuit 33. In addition, the 1f#IA circuit 9 described later
A series circuit of resistors R33 to R35 and a series circuit of a resistor R36 and the collector-emitter of a switching transistor Tr6 are connected in parallel between the output terminal P1 of No. 7 and the negative terminal of the full-wave rectifier 3.

The positive terminal of the resistor R34 is connected to the output terminal of the OR circuit 33, and the positive terminal of the resistor R35 is connected to the base terminal of the switching transistor Tr6. Further, a capacitor C11 is connected between both terminals of the resistor R35.

This capacitor C11 is the short circuit detection circuit Xa.

Check Xb, Xc and short circuit detection circuit QSi91~
5i (by J3 flowing, the short circuit detection circuit Xa,
The capacity G is set so that the time delay determined based on the photocoupler PC of Xb and Xc, the capacitor C3, etc., and the time delay of the check signal flowing to the check signal comparison circuit 81 match each other.

A series circuit of NOT circuits 34 and 35 is connected to the collector terminal of the switching transistor Tr6, and an output terminal of the NOT circuit 35 is connected to one input terminal of a NAND circuit 36.

Further, the output terminal of the NOT circuit 35 and the NAND circuit 3
A series circuit of a resistor R37°R38 and a knot circuit 37 is connected between the other input terminal of the 6, and a capacitor C is connected between the positive terminal of the resistor R38 and the negative terminal of the gold wave rectifier 3.
12 are connected.

A NOT circuit 39 is connected between the output terminal of the NAND circuit 36 and one input terminal of the AND circuit 38.

Further, an AND circuit 40 is connected to the output terminal of the NOT circuit 39.
One input terminal of the AND circuit 38 is connected to the other input terminal of the AND circuit 38, and the NOT circuit 1 in the short circuit discriminating circuit is connected to the other input terminal of the AND circuit 38.
2 output terminals are connected. Furthermore, a NOT circuit 41 is connected between the output terminal of the AND circuit 38 and the other input terminal of the AND circuit 40.

One input terminal of an AND circuit 43 is connected to the output terminal of the NOT circuit 39 via a NOT circuit 42, and the other input terminal of the AND circuit 43 is connected to the output terminal of the AND circuit 40. There is. Further, both output terminals of the AND circuit 40 and the AND circuit 43 are connected to an input terminal of an OR circuit 44.

Said NOT circuit 41.42, AND circuit 38°40.4
3 and the OR circuit 44 constitute a mismatch circuit 83.

Therefore, the check signal comparison circuit 81 is connected to the OR circuit 33.
A check signal corresponding to the logical value 1 is applied to the circuit, and a signal corresponding to the logical value 1 is output. Due to this output, the switching transistor Tr6 is turned on because the voltage of the resistor R35 is applied to its base terminal. Then, a signal corresponding to the logical value O is applied to the next stage NOT circuit 34, and the same NOT circuit 34 applies a signal corresponding to the logical value 1 to the NOT circuit 35 based on the signal corresponding to the logical value O. .

The NOT circuit 35 applies a signal corresponding to the logical value O to one terminal of the NAND circuit 36 based on the signal corresponding to the logical value 1. Further, the logic 1g corresponding to the logic (60) is applied to the NOT circuit 37 with a delay due to the time constant of the resistor R37 and the capacitor C12, and the NOT circuit 37 applies the other signal of the NAND circuit 36 based on the signal corresponding to the logic 11aO. A signal corresponding to a logical value of 1 is applied to the terminal of .

Then, the NAND circuit 36 applies one pulse signal corresponding to the logical value O to the NOT circuit 39 based on the signals applied to both terminals. Then, the knock circuit 39 applies a signal corresponding to the logic value 1 to one terminal of the AND circuit 38 and the AND circuit 40 based on the pulse signal corresponding to the logic 1+FIO.

When a signal corresponding to the logical value 1 is applied to the OR circuit 33 in this manner, the NOT circuit 39 applies a signal corresponding to the logical value 1 to the next stage.

Furthermore, at this point, if the short circuit detection circuits Xa, Xb, XC and the short circuit discrimination circuit are normal, the AND circuit 38 outputs the short circuit detection circuits Xa, Xb to the other input terminal.

Xc, and check signal 5i injected into the short circuit determination circuit
By inputting a signal corresponding to a logical value 1 based on ll to 51g3, a signal corresponding to a logical value 1 is applied to one input terminal of the next stage NOT circuit 41 and AND circuit 43.

The NOT circuit 41 transmits the signal corresponding to the logical value O based on the signal corresponding to the logical value 1 to the AND circuit 40 at the next stage.
The AND circuit 40 applies a signal corresponding to the logic 1lIIO to one input terminal of the OR circuit 44.

On the other hand, when a signal corresponding to the logical value 1 is applied to the NOT circuit 42 from the NOT circuit 39, the NOT circuit 42 applies a signal corresponding to the logical value O to one input terminal of the AND circuit 43; As a result, the AND circuit 43 applies a signal corresponding to the logical value O to the other input terminal of the OR circuit 44 based on the signal corresponding to the logical value 1 from the AND circuit 38 and the signal corresponding to the logical value O. .

In this way, the OR circuit 44 has a signal corresponding to the logic value 0 applied to its inner input terminal, and therefore applies a signal corresponding to the logic value 0 to the AND circuit 45 at the next stage, which will be described later.

Therefore, in this mismatch circuit 83, the AND circuit 38
When one input terminal of the AND circuit 38 is applied with a signal corresponding to the logic value 1, and the other input terminal of the AND circuit 38 is applied with a signal corresponding to the logic value 1h1, that is, the inner input Both wheels immediate value 1 applied to the terminal
When the signals corresponding to the logic value O have the same pulse width, the OR circuit 44 applies the signal corresponding to the logical value O to the next stage and outputs 1.
The memory check indicator 1-1c is set not to operate.

On the other hand, when the short circuit detection circuits Xa, Xb, Xc and the short circuit discrimination circuit are in an abnormal state, that is, in the case of a disconnection, the AND circuit 38 is injected into the short circuit detection circuit and the short circuit discrimination circuit at the other input terminal. By inputting a signal corresponding to the logical value 0 based on the switch signal, a signal corresponding to the logical value O is applied to one input terminal of the next stage NOT circuit 41 and AND circuit 43.

Then, the NOT circuit 41 applies a signal corresponding to the logical value 1 to the AND circuit 40, so that the AND circuit 40 applies a signal corresponding to the logical value 1 to one terminal of the OR circuit 44. Also, at this time, the AND circuit 43 applies a signal corresponding to the logical value O to the other input terminal of the OR circuit 44 by applying a signal corresponding to the logical value O to both input terminals.

As a result, the OR circuit 44 applies a signal corresponding to the logical value 1 to an AND circuit 45, which will be described later.

That is, in this mismatch circuit 83, the AND circuit 3
When one input terminal of the AND circuit 38 is applied with a signal corresponding to the logic value 1 from the NOT circuit 39 and the other input terminal of the AND circuit 38 is applied with a signal corresponding to the logic value O, the OR circuit 44 A signal corresponding to a logical value of 1 is applied to the next stage to cause a check indicator HC (to be described later) to perform a display operation.

Furthermore, the pulse width of the signal corresponding to the logical value 1 applied from the NOT circuit 12 to one input terminal of the AND circuit 38 of the mismatch circuit 83 and the signal corresponding to the logical value 1 applied from the NOT circuit 39 If the pulse widths are different from each other, the mismatch circuit 83 applies a signal corresponding to the logical value 1 from the OR circuit 44 to the next stage in the same manner as described above.

Further, when the check signal (check current) is not applied to the check signal comparison circuit 81 from the check signal generation circuits 78 to 80, the logic circuits 33 to 37 inject the check signal N current into the check signal comparison circuit 81. In order to apply a signal corresponding to the logical value opposite to that at the time, the NOT circuit 39 applies a signal corresponding to the logical value O to one input terminal of the AND circuit 38.

Therefore, in this state, even if either a signal corresponding to a logic value 1 or a signal corresponding to a logic value O is applied to the other input terminal of the AND circuit 38, the AND circuit 38 will be set to a logic value 0 at the next stage. Apply the corresponding signal. As a result, the logic (
A signal corresponding to igO is applied, and a signal corresponding to the logical value 1 is applied to one input terminal of both AND circuits 40 and 43 at the next stage.

At this time, a signal corresponding to the logic value O is applied from the NOT circuit 39 to the other input terminal of the AND circuit 40, and a signal corresponding to the logic 1 or O is applied to the other input terminal of the AND circuit 43 from the AND circuit 38. is applied, both AND circuits 40 and 43 apply No. 13 corresponding to the logical value 0 to the off circuit 44. As a result, the OR circuit 44 has logic 1II.
A signal corresponding to jO is applied to the next stage.

Next, the check indicator switching circuit 82 will be explained.

A series circuit of the collector/emitter of the switching transistor Tr7 and the set terminal 19/common terminal 20 of the short circuit control circuit check indicator HC is connected between the output terminal P1 of the distribution power supply circuit 97 and the negative terminal of the full-wave rectifier 3. .

A resistor R39 is connected between the base terminal of the switching transistor Tr7 and the output terminal of the OR circuit 44.
A series circuit of R40, an AND circuit 45, and a resistor R41 is connected, and a series circuit of a reverse diode D6 and a resistor R42 is connected between both terminals of the resistor R39.

Further, a capacitor C13 is connected between the negative terminal of the resistor R39 and the negative terminal of the gold wave rectifier 3, a resistor R43 is connected between the negative terminal of the resistor R41 and the negative terminal of the gold wave rectifier 3, and the voltage across the resistor R43 is is applied to the base terminal of the switching transistor Tr7.

The AND circuit 45, resistors R39 to R43, diode D6, capacitor C13, and switching transistor T
r7 constitutes a check indicator switching circuit 82.

Further, a drive flywheel diode D7 is connected between the set terminal 19 and the common terminal 20 of the check display 1-1c.
is connected, and the reset terminal 21. A return driving flywheel diode D8 is connected between the common terminals 20. Furthermore, a resistor R45 and a switch $ are connected between the P1 terminal of the power supply circuit 97 and the reset terminal of the check indicator I'C.
Two series circuits are connected, and a capacitor C14 is connected between both terminals of the return driving flywheel diode D8.

By turning on this switch S2, the check indicator Hc in the abnormal display state can be reset and returned to the normal display state.

Therefore, when the AND circuit 45 receives a signal corresponding to the logical value O from the OR circuit 44, it applies a signal corresponding to the logical value wAO to the resistor R43, so that the switching transistor Tr7 is turned off.

Conversely, when the AND circuit 45 receives a signal corresponding to the logical value 1 from the OR circuit 44, the AND circuit 45 receives the logical value 1.
A signal corresponding to T is applied to the next stage, and since the voltage of resistor R43 is applied to the base terminal, switching transistor T
r7 is turned on, and a display drive current is supplied to the check display Hc via the set terminal 19.

(2) Check indicator The check indicator HC has almost the same configuration as the short circuit indicator Ha, and when the display drive current flows through the set terminal 19 and the common terminal 20, the drive coil (not shown)
By being excited, a mark attached to the back surface of the disk is displayed to the outside to indicate that the short circuit detection circuit or short circuit discrimination circuit is abnormal.

On the other hand, when the display return drive current flows through the common terminal 20 and the reset terminal 21, the check display HC excites the return drive coil (not shown), causing the mark attached to the surface of the disk to go outside. displayed to indicate normal status.

■1 display lock circuit Next, the display lock circuit 76 will be explained.

An OR circuit 46. Resistors R46, R47, AND circuit 47
series circuit is connected.

Further, a series circuit of a reverse diode D9 and a resistor R48 is connected in parallel between both terminals of the resistor R46, and a capacitor C15 is connected between the positive terminal of the resistor R47 and the ground FILE2. A CR integration circuit is constituted by the resistor R46 and the capacitor C15.

Therefore, when the check signal (check current) is not flowing to the check signal comparison circuit 81, the above-mentioned NOT circuit 3
5, a signal corresponding to the logical value 1 is applied to the OR circuit 46, so the OR circuit 46 outputs a signal corresponding to the logical value 1, and the time constant J5 is output from the CR integration circuit of the resistor R46 and the capacitor C15. Next, let's discuss AND circuit 47!
A signal corresponding to Ij value 1 is applied. As a result, the AND circuit 47 applies a signal corresponding to the logical value 1 to the other input terminal of the AND circuit 17.

On the other hand, when the check signal (check current) is flowing to the check signal comparison circuit 81, a signal corresponding to the logical value 0 is applied from the NOT circuit 35 to the OR circuit 46, so that the OR circuit 46 is connected to the logical value 0. A signal corresponding to the logic value O is output, and a signal corresponding to the logical value O is applied from the CR integration circuit including the resistor R46 and the capacitor C15 to the AND circuit 47 based on its time constant. As a result, the AND circuit 47 applies a signal corresponding to the logic 1mO to the other input terminal of the AND circuit 17.

■0 phase comparison and discrimination circuit Next, the phase comparison and discrimination circuit 84 will be explained.

The phase comparison/discrimination circuit 84 outputs the output terminal P2. of the zero-phase current transformer 85. P3, and the output terminal P4. of the zero-phase voltage detector 86. Connected to P5.

In FIG. 2, the in-phase comparison and discrimination circuit 84 receives the zero-sequence current detection signal outputted via the surge absorption circuit 87 when the zero-sequence current transformer 85 detects the zero-sequence current, and the zero-sequence current detection signal output from the zero-sequence voltage detector 8.
6 detects a zero-sequence voltage, the phase comparison circuit 89 compares the phases of the zero-sequence current and the zero-sequence voltage based on both signals. It is supposed to be done.

Then, the phase discrimination circuit 90 determines that the ground fault fault point is on the right side of the display if it is on the right side, or on the left side, depending on the direction of the phase comparison of the eight phase comparison circuits. Assuming that the fault point is on the left side of the display,
It is designed to output a signal.

Further, the switching circuit 91 is turned on based on the control signal of the phase discrimination circuit 90. Further, the signal memory circuit 92 responds to the ON operation of the switching circuit 91, and outputs a judgment signal corresponding to a logic value of 1 from the right display output terminal P6 for a certain period of time depending on the direction. It has become. Further, the signal memory circuit 92 responds to the ON operation of the switching circuit 91, and in the case of the left side display, assumes that the ground fault fault point is on the left side of the display, and outputs a judgment signal corresponding to the logical value 1 from the left side display output terminal P7. is output at a certain period of time.

The surge absorption circuits 87 and 88, eight phase comparison circuits, and phase discrimination circuit 90. The switching circuit 91 and the signal memory circuit 92 constitute a phase comparison and discrimination circuit 84.

X. Ground Fault Direction Indicator Drive Circuit The ground fault direction indicator drive circuit is composed of a drive circuit that drives the right direction indicator ('bl) and a drive circuit that drives the left direction indicator Hb2.

In addition, each direction indicator Hb1. Since the drive circuits for driving and displaying Hb2 have the same configuration, for convenience of explanation, the drive circuit for the right direction indicator Hbl will be explained, and the drive circuit for the left direction indicator Hb will be explained.
Regarding the circuit elements and logic circuits constituting the drive circuit of No. 2, 100 is added to the codes given to the circuit elements and logic circuits constituting the drive circuit of the right direction indicator 1-1b1,
The explanation will be omitted.

The input terminal of an AND circuit 48 as a gate circuit for ground fault detection is connected to the right display output terminal P6, and when a judgment signal corresponding to a logic value 1 is input from the right display output terminal P6, a logic value is output from the output terminal. A switch signal corresponding to 1 is applied.

The output terminal of the AND circuit 48 is connected to one input terminal of a NAND circuit 50. Moreover, the AND circuit 4
A series circuit of resistors R49, R50 and a circuit 51 is connected between the output terminal of resistor 8 and the first input terminal of the NAND circuit 50, and a series circuit of resistors R49 and R50 is connected between the positive terminal of resistor 1AR50 and the negative terminal of the gold wave rectifier 3. is connected to capacitor C16. A NOT circuit 52 is connected to the output terminal of the NAND circuit 50.

Further, a series circuit of the collector/emitter of a switching transistor rr8 and the set terminal 19/common terminal 20 of the right direction indicator Hb 1 is connected between the output terminal P1 of the power supply circuit 97 and the negative terminal of the full-wave rectifier 3. . Further, a drive flywheel diode 1) 10 is connected between the set terminal 19 and the common terminal 20 of the right direction indicator 1"bl, and a return drive flywheel diode D11 is connected between the reset terminal 21 and the common terminal 20. It is connected.

The output terminal of the NOT circuit 52 is connected to the base terminal of the switching transistor Tr8 via a resistor R51, and a resistor R52 is connected between the negative terminal of the resistor R51 and the negative terminal of the gold wave rectifier 3. The voltage of the resistor R52 is applied to the base terminal of the switching transistor Tr8.

Said knot circuit 50, 52, NAND circuit 50, resistor R4
9 to R52 and the switching transistor Tr8 constitute a switching circuit 100 for right direction display.

To explain the voltage amplification circuit 101, the output terminal Pi (positive terminal) of the power supply circuit 97 (described later) and the gold wave rectifier 3
A resistor R53° and a transistor Tr9 are connected between the negative terminals of
A collector-emitter series circuit is connected. A resistor R54 is connected between the base terminal of the transistor Tr9 and the collector terminal of the switching transistor Tr8.

Furthermore, the negative terminal of the resistor R54 and the gold wave rectifier 3
A resistor R55 is connected between the negative terminals of the transistor Tr9, and the voltage of the resistor R55 is applied to the base terminal of the transistor Tr9.

A voltage amplification circuit 101 is constituted by the resistors R53 to R55, the NOT circuit 53, and the transistor Tr9.

Next, the display return switching circuit 102 that drives the direction indicator Hb1 to display a return display will be explained.

The collector-emitter of a switching transistor Tr10 is connected between the output terminal P1 of the power supply circuit 97 described later and the negative terminal of the full-wave rectifier 3, and the reset terminal 2 of the right-hand display Hb1.
Connected to 1. Same switching transistor Tr
One input terminal of the OR circuit 54 and a resistor R56 are connected between the base terminal of IO and the NOT circuit 56 of the time limit circuit 93, which will be described later.
A series circuit of is connected.

A resistor R57 is connected between the negative terminal of the resistor R56 and the negative terminal of the gold wave rectifier 3, and the voltage of the resistor R57 is applied to the base terminal of the switching transistor Tr10.

The other terminal of the OR circuit 54 is connected to the left direction indicator 1.
-1 b It is connected to the output terminal of the knot circuit 153 for 2.

Further, a NOT circuit 53 is connected to the collector terminal of the transistor Tr9, and the NOT circuit 53 is connected to one input terminal of an OR circuit 154 for the left direction indicator Hb2, and an OR circuit in a timer circuit 93 to be described later. It is connected to one input terminal of 55.

The output terminal of the NOT circuit 153 for the left direction indicator Hb2 is connected to the other input terminal of the OR circuit 55 in the timer circuit 93.

The OR circuit 54, resistors R56, R57, and switching transistor Tr10 constitute a display recovery switching circuit 102.

Therefore, when the signal 3iq6 corresponding to the logic value 1 as the display return signal is applied from the NOT circuit 56 of the timer circuit 93 to the OR circuit 54, the OR circuit 54 outputs the logic 1l to the next stage.
A signal corresponding to a1 is applied.

Then, the voltage of the resistor R57 is applied to the base terminal of the switching transistor Tr10, so that the switching transistor TrlO is turned on, and a display restoration drive current is supplied from the switching transistor Tr10.
be done.

In addition, in the drive circuit for the left direction indicator Ht)2, when the switching transistor Tr108 is turned on, the voltage of the resistor R155 in the voltage amplifying circuit 201 is applied to the base terminal of the transistor Tr109, so that the switching transistor Tr108 is turned on. r109 turns on. Next, since the signal corresponding to the logical value O is applied to the NOT circuit 153, the NOT circuit 153 applies a signal corresponding to the logical value 1 to the other input terminal of the OR circuit 54, and the same as above is performed. The OR circuit 54 applies a signal corresponding to the logical value 1 to the next stage.

Hereinafter, the switching transistor Trl operates in the same manner as the switching transistor Trl.
A display return drive current is supplied from O.

Xl, ground fault direction indicator A pair of right direction indicators Hbl constituting the ground fault direction indicator
, left direction indicator 1''b2 has the same configuration as the short circuit indicator Ha, and when a ground fault display drive current flows through one set terminal to both indicators Hb1 and Hb2, each drive coil ( (not shown) is excited, so that the marks attached to the side faces of each disk are simultaneously displayed to the outside (earth fault direction display).

Moreover, on the contrary, both indicators Hb1. Reset terminal 21 to Hb2
When a display return drive current flows through the display return drive coils, each return drive coil (not shown) is excited, so that the marks attached to the surface of each disk are constantly displayed to the outside all at once.

The X■9 time limit part control circuit i11 and time limit circuit time limit part control circuit 104 will be explained.

The oscillation holding circuit 105 shown in FIG. 1(b) is an OR circuit 55.
When a signal corresponding to a logical value O is inputted via the logic value 0, a signal corresponding to a logical value 1 is output to the next stage based on No. 13 corresponding to the logical value 0, and,
Logic value O → 1 (SiQC5iQ
When a signal corresponding to 5.5iQ7) is inputted, a signal corresponding to the logic 11ff 1→0 is outputted to the clear terminal 96 of the IC 57 based on that signal, causing the IC 57 to start oscillation.

Moreover, this oscillation holding circuit 105 has the logic 1if as described above.
If a signal corresponding to a logical value 1 is inputted from the hold release circuit 106 (described later) while outputting a signal corresponding to tO, a signal corresponding to a logical value 1 is output from the output side. There is.

Furthermore, while the oscillation holding circuit 105 is outputting a signal corresponding to the logical value O as described above, when a signal corresponding to the logical field 1 is inputted from the holding release circuit 106 (to be described later), the oscillation holding circuit 105 outputs the logical value from the output side. It is designed to output a signal corresponding to 1.

Specifically, the oscillation holding circuit 105 is constructed as shown in FIG. 2(C).

That is, one input terminal of the OR circuit 107 is connected to the output terminal of the OR circuit 55, and the output terminal of the OR circuit 107 is connected to one input terminal of the AND circuit 108. The other input terminal of the AND circuit 108 is connected via an inverter 109 to an output terminal of an AND circuit 112 of a holding release circuit 106, which will be described later. Further, the output terminal of the AND circuit 108 is connected to the clear terminal 96 of the IC 57 via a NOT circuit 110.

The OR circuit 107, the AND circuit 108. Inverter 1
09. and the knot circuit 110, the oscillation holding circuit 10
5 are configured.

Next, the holding release circuit 106 shown in FIG.
7 continues in the oscillation stopped state, a signal corresponding to the logical value O is output from its output side to the oscillation holding circuit 105.

Roughly speaking, when a signal 5iQ6 (display return signal) corresponding to a logical value 1 is inputted from the NOT circuit 56, a signal corresponding to a logical value 1 is outputted from its output side.

Specifically, this holding release circuit 106 is as shown in FIG. 2(C). That is, the output terminal of the NOT circuit 56 is connected to the input terminal of the AND circuit 111, and the output terminal of the AND circuit 111 is connected to the output terminal of the AND circuit 112 via a series circuit of resistors R105 and R106. Further, a series circuit consisting of a reverse diode D100 and a resistor R107 is connected between both terminals of the resistor R105, and the negative terminal of the resistor R105 is connected to a capacitor C.
It is connected to the ground wire E3 via 100.

The AND circuits 111, 112, resistance R105°R10
6, R107, diode D100 and capacitor C1
00 constitutes a hold release circuit 106.

Next, the time limit circuit 93 will be explained.

IC57 has resistor R58, capacitor C17゜resistor 59
An oscillation circuit 95 consisting of the following is connected, and the IC 57 divides the number of oscillations of the oscillation circuit 95. IC
One input terminal of a NAND circuit 58 is connected to the output terminal of C57 and the NAND circuit 58 is connected to the output terminal of C57.
A series circuit of resistors R62, R63 and a NOT circuit 62 is connected between the other input terminals of the , and a capacitor 01 is connected between the positive terminal of the resistor R62 and the negative terminal of the gold wave rectifier 3.
8 are connected. A NOT circuit 56 is connected to the output terminal of the NAND circuit 58, and an output terminal of the NOT circuit 56 is connected to an OR circuit 60.

A display recovery signal generation circuit 103 is constituted by the resistors R62 and R63, the capacitor C18, the NOT circuits 56 and 62, and the NAND circuit 58.

When the IC 57 receives a signal corresponding to the logical value O from the oscillation holding circuit 105, the oscillation circuit 95 starts oscillating. Also, when IC57 is divided into a predetermined number of parts,
A signal corresponding to the logical value 1 is applied from the output terminal to one terminal of the NAND circuit 58.

Further, a signal corresponding to the logic value 1 is applied to the NOT circuit 62 with a delay due to the time constant of the resistor R62 and the capacitor 018, and the NOT circuit 62 applies the other signal to the NAND circuit 58 based on the signal corresponding to the logic value 1. A signal corresponding to logic IIO is applied to the terminal of . Then, the NAND circuit 58 applies one pulse signal corresponding to the logical value 1 to the NOT circuit 56 based on the rising signals applied to both terminals.

Then, the NOT circuit 56 outputs the signal 5IQ6 corresponding to the logic value 1 based on the signal corresponding to the logic (IllO).
(display return signal) is applied to the OR circuit 54, 154°60.

Therefore, this time limit circuit T retransmits i! in the event of a failure in the distribution line that involves tripping of the substation disconnector. On the other hand, in the case of a ground fault that does not involve a trip, an output signal is output through the output terminal of the IC 57 after a certain period of time after the ground fault is indicated.

X■, power supply circuit Next, the core source circuit 97 will be explained.

A full-wave rectifier 63 is connected to the secondary side of the current transformer 62 whose primary side is connected to a separate power source. A smoothing capacitor C19 is connected between the positive and negative terminals of the full-wave rectifier 63.
and a capacitor C20 are connected. Further, a three-terminal regulator 64 is connected between the positive terminal and the negative terminal of the full-wave rectifier 63, and a capacitor C21 and a diode D101. Capacitor C10
1 series circuit and a parallel circuit are connected. and,
The positive terminal of the capacitor C101 is connected to the timer control circuit 104, thereby making the capacitor C101 a power source for the timer control circuit 104. This capacitor C101 allows voltage to be applied to the simultaneous eye control circuit 104 even when the power distribution It- is in a no-voltage state. Further, the output terminal of the three-terminal regulator 64 outputs a driving current to each of the circuits via the output terminal P1.

Note that a surge absorber 65 is connected between the primary sides of the current transformer 62.

Function of the Embodiment The function of the control circuit of the horizontal short-circuit/ground fault direction display device configured as described above will be described.

Now, when a steady load current is flowing through the distribution line, the first to second short circuit detection circuits Xa and Xb are activated.

At Xc, the first to second 'R flow transformers CTI.

A small amount of transformed current is output from C70, C70, and after being full-wave rectified by the full-wave rectifier 3, most of it is consumed by the resistor R1, while the third short-circuit detection circuit
At C, it is consumed by resistor R1, resistor R11, and diode array [)a.

If the check signal (check current) is not flowing from the check signal comparison circuit 81 at this time, in the display lock circuit 76, the signal corresponding to the logical value 1 is output from the NOT circuit 35 of the check signal comparison circuit 81 to the OR circuit 46.
, the OR circuit 46 outputs a signal corresponding to the logical value 1, and the AND circuit 4 outputs a signal corresponding to the logical value 1 from the CR integration circuit of the resistor R46 and the capacitor C15 based on its time constant.
7 is applied with a signal corresponding to logical 1. As a result, the AND circuit 47 is in a state where a signal corresponding to the logical value 1 is applied to the other input terminal of the AND circuit 17.

In this state, for example, if a short-circuit current that can trip a substation circuit breaker flows through the distribution line to which the first current transformer CT1 is attached, a first short-circuit detection signal is generated from the first current transformer CT1. A transformed current is output to circuit Xa. Then, this transformed current is full-wave rectified by the full-wave rectifier 3, and the photocoupler PC inputs the full-wave rectified analog signal.
Digital output is performed by a light emitting diode LED and a phototransistor PTr.

Furthermore, when the level of the digital signal applied to the base terminal is a predetermined value, the switching transistor Tr1
turns on and outputs a short-circuit current detection signal. and,
When the switching transistor Tr1 turns on, the voltage of the resistor R10 changes to the switching transistor Tr2.
When the voltage is applied to the base terminal of the switching transistor Tr2, the switching transistor Tr2 is turned on.

Then, the collector of the switching transistor Tr2
Since the potential between the emitters decreases, logic mo is applied to the NOT circuit 7.
A signal corresponding to is applied, and the NOT circuit 7 has a logic value of 1.
A signal corresponding to is applied to the OR circuit 8.

Further, the OR circuit 8 applies a signal corresponding to the logical value 1 to the next stage NOT circuit 9, and the NOT circuit 9 applies a signal corresponding to the logical value O based on the signal corresponding to the logical value 1 to the NAND circuit 10. is applied to one terminal of Also, the knot circuit 1 is extended by the time constant of the resistor R15 and the capacitor C6.
A signal corresponding to a logical value 0 is applied to FIJ.
711. Then, the NAND circuit 10 sets t; for the logic laO based on the falling signal applied to both terminals.
One pulse signal is applied to the knot circuit 12.

Then, the NOT circuit 12 applies a signal corresponding to the logic 1a1 to the signal memory circuit 75 based on the pulse signal corresponding to the logic value O, and the signal memory circuit 75 applies the signal corresponding to the logic 1a1 to the signal memory circuit 75 based on the time constant of the resistor R20 and the capacitor C7. A signal corresponding to the logical value 1 is applied to the AND circuit 13 for a certain period of time.

On the other hand, when the circuit breaker of the substation is tripped by the short circuit current, and as a result, the distribution line becomes voltageless, there is no voltage between the diode array □a in the third short circuit detection circuit XC, so that the transistor Tr3 The voltage of the resistor R13 (ie, no voltage) is applied to the base terminal, and the transistor Tr3 is turned off. Next, the transistor Tr3
Since the transistor Tr is in the off state, the NOT circuit 5 includes a transistor Tr.
Since the potential between the collector and emitter of No. 3 increases, a signal corresponding to a logical value of 1 is applied.

Therefore, a signal corresponding to the logic value 0 is output from the output terminal of the NOT circuit 5, and the inverter 6 rectangles the waveform based on the signal corresponding to the logic value O, and a signal corresponding to the logic value 1 (no voltage detection signal).

Therefore, while the signal corresponding to the logical value 1 from the signal memory circuit 75 is applied to the AND circuit 13, the signal corresponding to the logical value 1 from the no-voltage detection section (no-voltage detection signal) is applied. Based on both signals, a signal corresponding to the logical value 1 is applied to one terminal of the NAND circuit 15.

Further, a signal corresponding to the logic 1a1 is applied to the NOT circuit 16 with a delay due to the time constant of the resistor R21 and the capacitor C8, and the NOT circuit 16 applies the other signal of the NAND circuit 15 based on the signal corresponding to the logic 1+fi1. A signal corresponding to the logic fiio is applied to the terminal of.

Then, the NAND circuit 15 applies one pulse signal corresponding to the logical value 1 to the NOT circuit 18 based on the rising signals applied to both terminals. Then, the same knot circuit 18
applies a signal corresponding to the logical value 1 to the AND circuit 17 based on the signal corresponding to the logical value 0.

Also, at this time, the AND circuit 17 outputs a switch signal corresponding to the logical value 1 since a signal corresponding to the logical value 1 is applied from the display lock circuit 76 described later to the other input terminal. Then, the voltage of the resistor R24 is applied to the base terminal of the switching transistor Tr4 based on the switch signal, so that the switching transistor Trj operates as A (conducting) and transfers the short circuit display drive current to the short circuit display Ha. supply

As a result, this short circuit display drive current causes the short circuit display Ha
indicates a short circuit.

On the other hand, the circuit breaker at the substation on the distribution line becomes tripped and becomes a no-voltage state, and the AND circuit 17 outputs the signal 5iq7 corresponding to the logic 1iiO→1, and the OR circuit 55 outputs the same 5iO.
Based on io7, a signal corresponding to the logical value 0→1 is output to the oscillation holding circuit 105.

Then, the oscillation holding circuit 105 outputs a signal corresponding to the logical value 1→0 based on the signal to the clear terminal 96 of the 1c57, and the IC 57 starts the oscillation of the oscillation circuit 95 and re-divides the number of shots. Let it start.

When the IC 57 divides into a predetermined number, a signal corresponding to the logical value 1 is applied from its output terminal to one terminal of the NAND circuit 58. Further, a signal corresponding to the logic value 1 is applied to the NOT circuit 62 after being delayed by the time constant of the resistor R62 and the capacitor 018, and the NOT circuit 62 receives the logic value 1.
A signal corresponding to the logic value O is applied to the other terminal of the NAND circuit 58 based on the signal corresponding to the logic value O. Then, the NAND circuit 58 sends one pulse signal corresponding to the logical value 1 to the NAND circuit 56 based on the rising signal applied to both terminals.
to be applied.

Then, the NOT circuit 56 applies a signal 51g6 (display return signal) corresponding to the logical value 1 to the OR circuit 60 based on the signal corresponding to the logical value O. Then OR circuit 6
By applying a signal corresponding to logic 11 to the next stage based on a signal 51g6 (display return signal) corresponding to logic lllll11, the voltage of resistor R65 is applied to the base terminal of switching transistor Tr11, and the switching transistor Tr11 is turned on. As a result,
A display return drive current is supplied from the switching transistor Trl 1 to the reset terminal of the short circuit indicator Trl a.

This display return drive current resets the short circuit indicator Ha and returns to the steady display state.

On the other hand, when the hold release circuit 106 receives a signal corresponding to the logic lif[1 from the NOT circuit 56, the hold release circuit 106 oscillates and holds the signal corresponding to the logic la1 from its output side based on this signal. Output to circuit 105. Then, the oscillation holding circuit 105 outputs a signal corresponding to the logical value 1 based on the signal. As a result, IC5
7 stops the oscillation of the oscillation circuit 95. That is,
The oscillation holding circuit 105 and the IC 57 return to their original states.

Note that when this trippable short-circuit current flows through the distribution line and a signal corresponding to a logical value of 1 is applied from the NOT circuit 12 to the AND circuit 38, the OR circuit 44 of the mismatch circuit 83
Since a signal corresponding to the logical value O is applied to the AND circuit 45, a signal corresponding to the logical value ViO is applied to the AND circuit 45. Therefore, since the AND circuit 45 applies a signal (low potential) corresponding to the logical value O to the next stage, the switching transistor Tr7 remains in the off state, and the check indicator HC does not perform the display operation.

Further, second and third current transformers CT2. Even if a short circuit current that can trip the substation circuit breaker flows in the distribution line to which the CT3 is installed, the short circuit indicator Ha will indicate a short circuit in the same way as above, and the time limit circuit 93 will indicate a short circuit after a predetermined time. Returns to steady display state.

Next, the operation of the self-diagnosis circuit 83 will be explained.

When a signal corresponding to the logic value 1 is applied to the next stage at predetermined time intervals from the NOT circuit 32 of the check signal generation circuit connected to the first short circuit detection circuit Xa, the switching transistor Tr5 receives the signal corresponding to the logic value 1. Turns on (conductivity) by applying voltage to resistor R32 based on
do. As a result, this switching transistor Tr5
A check signal 51g1 (check current) is injected into the positive terminal of the light emitting diode LED of the photocoupler PC in the first short circuit detection circuit Xa.

Now, if the first short circuit detection circuit Xa is normal, each circuit element and logic circuit operate in the same way as when the short circuit current is detected. A signal corresponding to a logical value of 1 is applied to one terminal.

Also, the NOT circuit 32 of the first check signal generation circuit 78
Since the signal corresponding to the logical value 1 is applied to the OR circuit 33 of the check signal comparison circuit 81, the OR circuit 33 applies the signal corresponding to the logical value 1 to the next stage. Then, the NOT circuit 39 applies a signal corresponding to the logical value 1 to one terminal of the AND circuit 38 and the AND circuit 40 based on the operation of each circuit element and logic circuit.

As described above, the AND circuit 38 has the short circuit detection circuit Xa at the other input terminal, and the NOT circuit 12 receives the signal corresponding to the logic value 1 (i.e., the signal corresponding to the logic value 1) based on the check signal 51g1 injected into the short circuit determination circuit. (signal with the same pulse width as the signal corresponding to the logical value 1 applied to the terminal)
is applied.

Then, the OR circuit 44 of the mismatch circuit 83 applies a signal corresponding to the logical value O to the next stage.

As a result, the AND circuit 45 receives the logical value O from the OR circuit 44.
By applying the signal corresponding to the logic value 0, the switching transistor Tr7 is in an off state because a signal corresponding to the logical value 0 is applied to the resistor R43, and the check indicator H
c does not display.

Note that when this check signal 5ia1 is injected into the first short circuit detection circuit Xa, the AND circuit 47 of the display lock circuit 76 outputs a logic value of 0 to the other input terminal of the AND circuit 17 in the drive circuit of the short circuit indicator Ha. Apply the corresponding signal. Therefore, regardless of whether a signal corresponding to a logic value 1 (No. 8 or a signal corresponding to a logic value O) is applied to the other input terminal of the AND circuit 17, the AND circuit 17 outputs a signal corresponding to a logic value 0. Since the voltage is applied to the next stage, the switching transistor Tr4 remains in the off state.

Therefore, the check signal 5iq1 injected into the first short circuit detection circuit Xa will not cause the short circuit indicator 1-18 to perform the display operation.

On the other hand, if the circuit element in the first short circuit detection circuit Xa is disconnected from the light emitting diode L[ED to the NOT circuit 12J of the short circuit determination circuit, and the logic circuit is disconnected, the NOT circuit 1
Since the signal corresponding to the logical value 2 to O is applied to one input terminal of the non-coincidence circuit 83, the OR circuit 44 of the same-year coincidence circuit 83 applies a signal corresponding to the logical value 1a1 to the next stage.

Moreover, the light emitting diode L in the first short circuit detection circuit Xa
Due to a malfunction in the circuit elements and logic circuits from the ED to the NOT circuit 12 of the short-circuit determination circuit, the pulse width of the signal corresponding to the logic 1lf11 applied from the NOT circuit 12 and the check signal injected to the check signal comparison circuit 81 may change. If the pulse width of the signal corresponding to logic 11 applied from the NOT circuit 39 to the other input terminal of the AND circuit 38 does not match based on the pulse width of the signal corresponding to the logic 11, the mismatch circuit 83 outputs the OR circuit 44 as described above. A signal corresponding to the logical value 1 is applied to the next stage.

As described above, by applying the signal corresponding to the logic mi from the OR circuit 44 to the AND circuit 45, the switching transistor Tr7 is turned on to apply a signal corresponding to the logic value 1 to the resistor R43, and the display is Drive current is supplied to the check indicator Hc via the set D; child 19.

As a result, the drive coil (not shown) of the check indicator Hc is energized, and the mark attached to the back of the disk is displayed to the outside to indicate that the short circuit detection circuit Xa or the short circuit discrimination circuit 70 is abnormal. show.

In order to return the check indicator Hc which has displayed an abnormality as described above to a normal display, it is sufficient to turn on the switch S2. Then, when the display return drive current is supplied from the power supply circuit 97 via the reset terminal 21, the check display 1-1
At c, a return drive coil (not shown) is energized, and a one-inch mark is displayed externally on the surface of the disk, indicating that it is in a normal state.

J3, the case where the check signal 5iQ1 is injected into the first short-circuit detection circuit Xa and the short-circuit discrimination circuit 70 has been described above, but when the check signal 5iQ1 is injected from the second check signal generation circuit 79 or the third check signal generation circuit 80, respectively The same applies when the check signal 51g2.5iQ3 is injected into the second short circuit detection circuit xb or the third short circuit detection circuit XC.

Next, the action at the time of a ground fault will be explained.

If a ground fault occurs in the distribution line, the phase comparison discrimination circuit 8
4 detects the zero-sequence current and zero-sequence voltage flowing through the IL through a zero-sequence current transformer 85 and a zero-sequence voltage detector 86, and compares the phases of the zero-sequence current and zero-sequence voltage.

Then, when the phase of the zero-sequence current is close to leading by 0 to 110 degrees with respect to the phase of the zero-sequence voltage as a reference, the phase comparison and discrimination circuit 84 determines that the ground fault point is on the right side, and outputs a logic signal from the right side display output terminal P6. A determination signal corresponding to the value 1 is applied to the AND circuit 48 for a certain period of time.

Subsequently, the AND circuit 48 applies a signal corresponding to the logical value 1 to one terminal of the NAND circuit 50. Further, a signal corresponding to the logic value 1 is applied to the NOT circuit 51 with a delay due to the time constant of the resistor R49 and the capacitor C16, and the NOT circuit 51 applies the other signal to the NAND circuit 50 based on the signal corresponding to the logic value 1. A signal corresponding to the logical value O is applied to the terminal of . Then, the NAND circuit 50 applies one pulse signal corresponding to the logical value 1 to the NOT circuit 52 based on the rising signals applied to both terminals.

Then, the same NOT circuit 52 applies a signal corresponding to the logical value 1 to the next stage based on the signal corresponding to the logical value O,
The switching transistor Tr8 has a resistor R at its base terminal.
It is turned on by applying a voltage of 52. As a result, the switching transistor Tr8 outputs a right direction display drive current as a ground fault direction display signal to the right direction indicator 1-1b1.

As a result, the right direction indicator 1-1 b i displays a ground fault due to this right direction display drive current.

Further, when the switching transistor Tr8 is turned on, the voltage of the resistor R55 is applied to the base terminal of the transistor Tr9, so that the transistor Tr9 is turned on, and the signal applied to the base is amplified and applied to the next stage. do. Then, a signal corresponding to the logical value O is applied to the NOT circuit 53, and the NOT circuit 53 transfers the logical value 1 to the next stage.
A signal 5iq4 corresponding to is applied.

As a result, the logic 1a is applied to the other input terminal of the OR circuit 154.
By applying the signal corresponding to the logical value 1, the OR circuit 154 applies the signal corresponding to the logical value 1 to the next stage. Further, the OR circuit 154 applies a signal corresponding to the logical value 1 to the next stage. Then, the voltage of the resistor R157 is applied to the base terminal of the switching transistor Tr110, thereby turning on the switching transistor Tr110. As a result, the switching transistor Tr
110 to the left direction indicator H via the reset terminal 21.
A display return drive current is supplied to b2.

At this time, if the left direction indicator Hb2 is displaying normally, even if the return drive coil is excited by the display return drive current, the magnetic pole part of the stator does not change its magnetic pole, so the disk maintains the normal display state. continue.

On the other hand, when the left direction display fiHb2 is in the ground fault direction display state, the magnetic pole part of the stator is the opposite magnetic pole to that in the normal display state, so when the return drive coil is excited by the return drive current, Then, the magnetic poles of the stator change to the opposite magnetic poles, so that the disk rotates back to normal display.

Furthermore, when the NOT circuit 53 applies the signal 5iQ4 corresponding to the logical value 1 to the next stage, the signal corresponding to the logical value 1 is applied to the input terminal of the OR circuit 55, so that the OR circuit 55 maintains oscillation. A signal corresponding to a logical value of 1 is applied to the circuit 105. As a result, I
C57 clears the division of the number of oscillations of the oscillation circuit and starts re-division v1 of the number of oscillations.

When 1057 is divided into a predetermined number, that is, after a predetermined period of time has elapsed, a signal corresponding to a logical value of 0 is applied from its output terminal to one terminal of the NAND circuit 58.

Thereafter, the display return signal generation circuit 103 operates in the same manner as when returning the short circuit indicator 1-1a, and the NOT circuit 56 applies the signal 5iq6 (display return signal) corresponding to the logic value 1 to the OR circuit 54. do.

Then, the OR circuit 54 applies a signal corresponding to the logical value 1 to the next stage, and the voltage of the resistor R57 is applied to the base terminal of the switching transistor TrlO, thereby turning on the switching transistor TrlO.

As a result, from the transistor Tr10 to the reset terminal 21
A display return drive current is output to the right direction indicator 1-1 b 1 through the right direction indicator Hbl, and the right direction indicator Hbl returns to display.

On the other hand, the phase comparison and discrimination circuit 84 detects that the phase of the zero-sequence current is, for example, 1.
When the deviation is 80 to 290 degrees, it is assumed that the ground fault point is on the left side, and a determination signal corresponding to the logical value 1 is applied from the left display output terminal P106 to the AND circuit 148 for a certain period of time.

Thereafter, in the same way as the drive circuit of the right direction indicator 1-1b1, each circuit element and logic element of the left direction indicator Hb2 operates and the switching 1 transistor Tr108 turns on, so that the left direction indicator Hb2 Outputs the left direction display drive current.

As a result, the left direction indicator Hb2 displays the left direction.

On the other hand, when the switching transistor Tr108 turns on, the transistor Tri09 turns on similarly to the drive circuit for restoring the right direction indicator Hb1, and amplifies the signal applied to the base and applies it to the next stage. As a result, the NOT circuit 153 applies a signal corresponding to the logical value 1 to the next stage.

As a result, the OR circuit 54 constituting the return drive circuit of the right direction indicator 1''bl applies a signal corresponding to the logic value 1 to the next stage to turn on the switching transistor Tr10. Then, a display return drive current is supplied from the switching transistor Tr10 to the left direction indicator Hb2 via the reset terminal 21.

At this time, if the right side direction indicator 1" bl is in a normal display state, even if the return drive coil is excited by the display return drive current, the magnetic pole part of the stator does not change its magnetic pole, so the disk remains in a normal display state. continue to hold.

On the other hand, when the right side direction indicator Hb1 is in the ground fault direction display state, the magnetic pole part of the stator is the opposite magnetic pole to that in the normal display state, so the return drive coil is excited by the return drive current. At this time, the magnetic poles of the stator are replaced by the opposite magnetic poles, so that the disk rotates back to normal display.

Further, when the NOT circuit 153 applies the signal 5ia5 corresponding to the logical value 1 to the next stage, the OR circuit 5 of the timer circuit 93
5 applies a signal corresponding to the logical value 1 to the clear terminal 96 of the IC 57. As a result, after a predetermined time, the time gate path 93 outputs the signal 5iG6 (
A display return signal) is applied to the OR circuit 154.

Then, the OR circuit 154 applies a signal corresponding to the logical value 1 to the next stage, and the voltage of the resistor R157 is applied to the base terminal of the switching transistor T110, thereby turning on the switching transistor Tr110.

As a result, a display return drive current is output from the switching transistor Tr110 to the left direction indicator Hb2 via the reset terminal 21, and the left direction indicator Hb2 returns to display.

In this embodiment, in the short circuit detection circuits Xa, Xb, and Xc, a photocoupler PC is used to input an analog signal based on the short circuit current, and the photocoupler PC is used for digital output, so the phototransistor PTr of the photocoupler PC Due to the high sensitivity and high speed performance of the resistor R1, the resistance value of the resistor R1 can be reduced.
1 heat generation can be reduced.

Second example Next, a second embodiment will be explained with reference to FIG.

In addition, the same reference numerals are attached to the same or corresponding configurations as those of the first embodiment, and the explanation thereof will be omitted.

In this embodiment, in the first embodiment, the right direction indicator H
In the configuration of the drive circuit for driving the return display of b1 and left direction indicator Hb2, resistors R53, R54, R55, transistor Tr9 and NOT circuit 53, and resistor R153,
R154, R155° switching transistor Tr1
09 and circuits 1 to 153 are omitted. Instead, the output terminal of the NOT circuit 52 in the drive circuit that drives the display is connected to one input terminal of the OR circuit 154, and the output terminal of the NOT circuit 152 is connected to one input terminal of the OR circuit 54. has been done.

Therefore, in this embodiment, in the drive circuit for the right direction indicator) bl, when the NOT circuit 52 applies the signal 5ia4 corresponding to the logic value 1 to the next stage, the IC5 of the timer circuit 93
7 starts re-dividing the excavation number of the oscillation circuit 95. Furthermore, in the drive circuit of the left direction indicator 1-1 b2, when the NOT circuit 152 applies the signal 51g5 corresponding to the logic 111 to the next stage, the IC 57 of the timer circuit 93 re-divides the number of oscillations of the oscillation circuit 95. Start.

Further, in this embodiment, the power supply circuit 9 in the configuration of the first embodiment is
The difference is that 7 is provided not in a separate power supply but in the third short circuit detection circuit Xa.

That is, the collector and emitter of the transistor Tr20 are connected between both terminals of the diode array Da.

A series circuit of a diode D20 and a rechargeable battery 65 is connected. Further, a resistor R65 is connected between the collector and base of the transistor Tr20, and a Zener diode ZD is connected between the pace terminal of the transistor Tr20 and the negative terminal of the gold wave rectifier 3.

This power supply circuit 97 further stabilizes the forward voltage across the diode array Da using the transistor Tr20, the Zener diode 7D, etc., and charges the battery 65.

When a steady load current is flowing through the distribution line, the backup battery 65 is not consumed, and the drive current is supplied to each circuit using the load current. When the substation circuit breaker trips and load current no longer flows through the distribution line, the backup battery 65 supplies the necessary drive current to each circuit from the output terminal P1.

Furthermore, in the check signal generation circuits 78 to 80, a plurality of ICs 57 were used for each phase in the above embodiment, but
In this embodiment, a common IC57 is used, and one input terminal of the AND circuit 29 for the second and third short circuit detection circuits Xb and Xc and a pair of output terminals of the IC57 are connected to resistors R66 and R67, respectively, and the AND circuit. 66 series circuits are connected.

A capacitor C22 is connected between the positive terminal of the resistor R67 and the negative terminal of the gold wave rectifier 3, and the resistor R66
A reverse diode D21 and a resistor R68 are connected between both terminals of the
series circuit is connected.

Further, this embodiment differs from the first embodiment in that the output terminal of the AND circuit 66 is connected to the positive terminal of a resistor R27.

Therefore, in this embodiment, the number of ICs 57 used can be reduced.

In this embodiment, in the third short circuit detection circuit Xc, the photocoupler PC isolates the digital output and the diode array Da connected in series to the short circuit detection circuit. A configuration is possible in which the short circuit detection circuit Xc, the power supply circuit 97, and the no-voltage detection circuit 72 are connected to the device CT.

Third embodiment Next, a third embodiment will be described with reference to FIGS. 5 and 6.

In this embodiment, the same or equivalent structures as those in the first and second embodiments will be denoted by the same reference numerals, and the explanation thereof will be omitted, and only the major differences will be explained.

The detectors are the first, second and third current transformers CT1°C70, CH2 as current detectors for each phase distribution line.
and a power supply current transformer CT are respectively attached, and the secondary side terminals of the first to third current transformers CT1, C70, CH2 are connected to each other to form a star circuit.

Further, a resistor R for detecting the zero-phase current synthesized from the three phases is connected within the star circuit, and the first to third current detectors CTI, CT2 . Zero phase detector 85 along with CT3
In addition, a zero-phase voltage detector 86 for detecting zero-phase voltage is provided.

Further, in the short circuit detection section, the primary side of the auxiliary current transformer CTa1 is connected between one secondary side terminal of the first current transformer CT1 and the terminal of the resistor R, and the primary side of the auxiliary current transformer CTa1 is connected between the secondary sides. Zener diode ZD.

A parallel circuit of a resistor R1, a smoothing capacitor C1, and a diode D is connected, and a series circuit of a diode D1 and a capacitor C2 is connected. A rectifier circuit 3 is constituted by the Zener diode 7D, resistor R1, smoothing capacitor C1, diode D, diode D1, and capacitor C2.

Therefore, when a short circuit current flows through the distribution line, the first current transformer CT1 supplements the transform current W based on the short circuit current.
The i-current is outputted via the current transformer Ta1, and the rectifier circuit 3 rectifies the transformed current. The photocoupler PC receives the rectified analog signal and outputs it as a digital signal using a light emitting diode LED and a phototransistor PTr.

The second short circuit detection circuit xb and the third short circuit detection circuit XC are connected to the second auxiliary current transformer CTa similarly to the first short circuit detection section.
2. and a third auxiliary current transformer CTa3. Note that in the third short circuit detection circuit XC, the phototransistor PTr.

Resistors R5, R10, capacitor C3, and switching transistor Tri are connected to the negative terminal of a full-wave rectifier 2, which will be described later, instead of being connected to the rectifier circuit 3.

Next, the no-voltage detection section will be explained.

Secondary side terminal P20 of detector CT for power supply. A full-wave rectifier 2 is connected to P21, and a smoothing capacitor C30 and a capacitor C31 are connected between the plus and minus terminals of the full-wave rectifier 2°.

Further, the structure of the no-voltage detection section differs from that of the first embodiment in that a series circuit of resistors R12 and R13 is connected between the positive terminal and the negative terminal of the full-wave rectifier 2.

Therefore, in this embodiment, the short circuit detection circuits Xa, Xb, Xc
In this system, a photocoupler PC is used to input analog signals based on the short-circuit current, and the same photocoupler PC is used for digital output. ．． The metamorphic current output from CTa3 can be reliably detected.

The control circuit of the short circuit detection and display device connects the first current transformer CT1 to the third current transformer i! to the distribution line 1-. 1 IcT
3 and a current transformer CT for power supply for primary insulation.
Secondary insulation is provided by the auxiliary current transformers CTa1 to CTa3, and tertiary insulation is provided by the photocoupler PC. Therefore, reliability of insulation of the control circuit can be improved.

In this way, in this embodiment, by inserting an auxiliary current transformer (CTa) in each star circuit, by inserting an auxiliary current transformer (CTa) in each star circuit, as is clear from the following equation, Primary side converted impedance Z-Z'/n2n; CT
Since the impedance on the secondary side of the secondary side impedance CTa can be increased and the star circuit can be insulated, the influence of wraparound current can be eliminated. Therefore, the circuit configuration is simplified and the insulation reliability of the control circuit is improved.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and may be modified as desired without departing from the spirit of the present invention.

Effects of the Invention As detailed above, this invention self-diagnoses the short-circuit detection control circuit using a self-diagnosis circuit, and if there is a malfunction in the short-circuit detection control circuit, the check detector displays an abnormality. This can be detected during periodic inspection of the equipment. Therefore, it is possible to eliminate the uncertain factors that conventional display devices had, that is, the negative influence of the fault detection display device on finding fault points in power distribution lines. In addition, even if a distribution line failure occurs without periodic inspection, whether the detection display device is operating normally or abnormally depends on the detection operation status.
This can be easily confirmed by checking the failure diagnosis display, which has an excellent effect of improving reliability for early detection of failure points.

[Brief explanation of drawings]

FIG. 1 shows an electric block circuit diagram of a short-circuit/ground fault direction detection and display device embodying the present invention, (a) is an electric block circuit diagram of the main part of the present invention, and (b) is an electric block circuit diagram of a timed circuit. Figure 2(a). (b) and (c) also show electric circuit diagrams of the short circuit/ground fault direction detection display device, (a) is an electric circuit diagram of the main part of this invention, (b) is a power supply circuit diagram, and (C) is a time limit circuit diagram. Fig. 3 is a schematic diagram of a short circuit indicator, Fig. 4 is an electric circuit diagram of the second embodiment, Fig. 5 is a block circuit diagram of the third embodiment, Fig. 6(a), (b) also shows a main part electric circuit diagram and a power supply circuit diagram, respectively. 68... Short circuit detection section, 69... No voltage detection section, 70
...Short circuit discrimination circuit, 71...Current discrimination switching circuit, 72...No voltage detection circuit, 73...Second waveform operation circuit, 74...First waveform operation circuit, 76...
・Display lock circuit, 77... Self-diagnosis circuit, 78...
・First check signal generation circuit, 79...Second check signal generation circuit, 80...Third check signal generation circuit, 81...Check signal comparison circuit, 82...Check indicator Drive circuit, 83... Mismatch circuit, 93
...Time limit circuit, 95...Oscillation circuit, 97...Power supply circuit, 98...Short display switching circuit, 99...
・Switching circuit for display recovery, Xa...first short circuit detection circuit, Xb...second short circuit detection circuit, Xc...
Third short circuit detection circuit, Ha... Short circuit indicator, Hbl.
・Right direction indicator, Hb2...Left direction indicator, H
C... Check indicator, CT1... First current transformer, CT2... Second current transformer, CT3... Third current transformer, L... Distribution line.

Claims (1)

[Claims] 1. In a short circuit detection and display device that displays a short circuit using a short circuit detection control circuit based on a detection signal output by a current detector when a short circuit current flows through a distribution line, A check signal generation circuit injected into a control circuit, and a comparison determination between the check signal injected from the check signal generation circuit and a signal output from the control circuit based on the check signal injected into the short circuit detection control circuit. The self-diagnosis circuit includes a check signal comparison circuit that displays a normal check display when the two signals match, and displays an abnormality display when the two signals do not match. A control circuit for a short circuit detection display device, characterized in that: