JPS6262640A - Reception timing signal generating circuit - Google Patents

Abstract

PURPOSE:To prevent the meaning of a timing slot from being slightly different by keeping a correction value corrected just before at a normal timing signal as the frequency and phase of an internal timing signal when a signal informing whether the input timing signal is normals or not is 'not'. CONSTITUTION:A control signal generator 100 is a circuit outputted a signal 105 controlling a voltage control circuit and revises an output signal 105 of a control signal holding circuit only when a CD signal 160 exists and fixes the signal 105 to a value just before the CD signal 160 is lost when the CD signal 160 does not exist. The meaning of the timing slot is not made slightly different after the recovery of an error even at a line fault longer than that in a conventional system by fixing the phase and frequency of the timing clock to the input timing signal sent from a transmitter just before the line fault takes place in such a way and the timing clock generated internally is pulled into the phase of a reception timing clock.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a reception timing signal generation circuit for a reception device used in a synchronous digital transmission line.

BACKGROUND OF THE INVENTION Recently, digital data transmission using a synchronous method has been widely used in various data communication fields such as computer-to-computer communication and facsimile communication. In synchronous data communication, the time slots on the time axis are clearly defined by the timing clock, and the meaning of each time slot, for example, ``The meaning of this time slot is the least significant bit of an 8-digit binary number.'' When the meaning is clear, such as, by knowing the value of the signal on the data line at this timing slot, digital communication can be performed.

In digital data transmission using the synchronous method, if a line failure occurs and input data and timing clocks do not reach the receiving device, the receiving station will not be able to operate correctly. For this reason, the receiving station uses an oscillation circuit to generate a timing clock, and matches the frequency and phase of this signal with the input timing clock. The configuration of the PLL circuit shown in FIG. 4 is known. (Technical Magazine 1 Transistor Technology, March 1983 issue, P. 270-278
However, with the above configuration, if the input timing signal is lost due to a line failure such as a momentary interruption, the oscillation frequency of the oscillation circuit of the receiving station will change. However, when the line failure is recovered, there will be a relatively large discrepancy between the timing slots of the transmitting station and the timing slots of the receiving station.Once this discrepancy occurs, the transmission The station and the receiving station use transmission frames such as HDLC to resynchronize the frames and synchronize the timing clock.

The meaning of 1. must be re-clarified.

The object of the present invention is to increase the line failure time T' without changing the meaning of one timing slot mentioned above. As an example of the conventional technology for the value of T, if a commercially available modem is used for digital transmission using a 144 kbps high-speed digital modem on a standard analog transmission line of 5QkHz to 108kHz, T = approx. The time is 100 milliseconds, and the number of codes during this time is approximately 14,400 bits.

Means for Solving the Problems The present invention provides internal timing signal generating means for generating an internal timing signal whose frequency is controlled by a control signal that generates a frequency close to the frequency of an input timing signal, and a method for generating an internal timing signal and an input timing signal. The above object is achieved by providing a phase comparison means for generating a signal according to the phase difference of the signals, and a control signal generation means for generating a signal for controlling the internal timing frequency from the signal according to the phase difference. It is something.

According to the above configuration, when the signal notifying whether the input timing signal is normal or not, the present invention compares the phases of the internal timing signal and the input timing signal at regular intervals, and obtains the signal from the phase of the internal timing signal and the input timing signal. A signal corresponding to the phase difference is used to bring the frequency and phase of the internal timing signal closer to the input timing signal, and when the signal notifying whether the input timing signal is normal or not is negative, this signal is The correction values made during normal operation immediately before failure are held as the frequency and phase of the internal timing signal.

Embodiment FIG. 1 is a schematic diagram of elements of a reception timing signal generation circuit of a digital signal receiving apparatus in an embodiment of the present invention.

In FIG. 1, 100 is a control signal generation circuit which is the key to the present invention, and 105 is a signal for controlling a voltage controlled oscillation circuit 110, which is an analog or digital signal. 110
is a voltage controlled oscillator (VCO). This may be a current control type, and is used in the sense of an oscillation circuit whose oscillation frequency changes depending on an external signal. 115 is the output signal of this circuit 100, which is usually the input timing signal 14.
It is a frequency that is an integer multiple of 0. 120 is a frequency divider which divides the output 115 of the voltage controlled oscillation circuit 110 into an integer 0/1 and outputs the frequency. 125 is the output from the frequency divider 120, and its frequency is close to the frequency of the input timing signal 140. 130 is a phase comparator circuit that receives the input timing signal 140 and the output signal 12 from the frequency divider 120.
5 and outputs a phase difference signal 135. 1
35 is an output signal from the phase comparison circuit 130, which is a function of the phase difference within the comparison time. 137 is a pulse signal for causing the control signal generator 100 to update the signal 105. 140 is an input timing signal, in this embodiment,
Even if this signal is lost, when this signal is recovered after a certain period of time T, the phase of this signal is recovered and the meaning of the timing slot is kept consistent. Reference numeral 150 denotes an input data signal input in synchronization with the input timing signal 140, which forms a frame such as HDLC, and is used to clarify the meaning of a timing slot by decoding this. A CD signal 160 indicates that the input timing signal 140 is valid (ON when valid, OFF when invalid).

This CD signal 160 is obtained as a carrier detection signal when a modem is used in the terminal device. When the CD signal 160 cannot be obtained, input data,
It is created from the properties of the input timing signal, transmission carrier, etc.

The operation of the above configuration will be explained below.

The timing signal oscillated by the voltage control circuit 110 is frequency-divided by an integer n/n by the frequency divider 120 and becomes an input to the phase comparison circuit 130. The phase comparison circuit 130 receives an input timing signal 140 to be compared, compares the phases thereof, and outputs the resulting phase difference signal as a signal 135. The signal 135 can be an analog or digital signal, which can be used depending on the purpose, but in this embodiment, the case of a digital signal will be described in detail later with reference to FIG.

The control signal generator 100 is a circuit for outputting a signal 105 to control the voltage control circuit. If there is a phase difference in the signal 35, the control signal generator 100 outputs the signal 105 in a direction to eliminate the phase difference, and when the CD signal 160 is ON, it outputs the signal 105. The new value is obtained by changing only the
When the CD signal 160 turns OFF, the value of the last correction result (although not necessarily the last one) carried out when the CD signal 160 was turned ON immediately before turning OFF is held;
This is the output signal 105. The output signal 105 is
Although either analog or digital signals may be used depending on the purpose, in the embodiment, the case of digital signals will be described in detail below using FIG. 2.

In FIG. 2, a portion 100 surrounded by a broken line is the control signal generator 100 shown in FIG.
Signal 160 and signal 105 correspond to those in FIG. Although the signal 135 and the signal 105 are each 8-bit digital signals, the present invention is not limited to this example in terms of the number of bits, the meaning of the code, etc.

Signal] 35 is when there is no phase difference (00000000)
It is. When the phase of the signal 125 is delayed compared to the phase of the input timing signal 140, assuming that the value of the signal 135 is positive, and the degree of delay is 7, the signal 135 becomes (0
0000111).

On the other hand, when the signal 125 is ahead of the phase of the input timing signal 140, the value of the signal 135 is negative, but this is expressed as a two's complement number, and if the degree of advance is 7, the signal 135 is (11111001,).

The adder circuit 200 adds the output signal of the control signal holding circuit 210 and the phase difference signal 135 to obtain a signal 205. This value is generated using the signal 137 and the signal 160 and is latched by the latch pulse 225 which is the output of the pulse generating circuit 220 and becomes the new output value 105 of the control signal holding circuit 210.

The time at which the latch pulse 225 is generated is a stable time at which the signal 205 does not change. The launch pulse 225 is generated by the latch pulse generation circuit 220 at regular intervals while the CD signal 160 is ON. While the CD signal 160 is OFF, the latch pulse 225 is not generated. Furthermore, the CD
The operation of the present invention can be further stabilized by giving the signal 160 a property of turning OFF immediately when the timing input becomes incorrect, and turning ON after a short delay when the timing input is correctly restored.

FIG. 3 shows a concrete circuit of the control signal generator 100 shown in FIG. 1, and the area inside the broken line 100 is an example of the control signal generator. In FIG. 3, 300 is an addition IC circuit, which corresponds to the addition circuit 200 in FIG.
0 is a launch circuit IC, which corresponds to the control signal holding circuit ζ in FIG. A circuit surrounded by a broken line 330 is a waveform shaping circuit for the signal 137, which shapes the input pulse into a thin pulse with a constant pulse width. The circuit surrounded by a broken line 340 is a CD signal generation circuit, and when the signal 160 changes from ON to OFF, the output signal 345 immediately turns OFF, but when the signal 160 turns OFF.
When turning on from F, the circuit turns on after a delay.

The latch pulse 325, which corresponds to the signal 225 in FIG.
Occurs only when signal 345 is ON.

As described above, according to this embodiment, the output signal 1 of the control signal holding circuit
05 is updated only when the CD signal 160 is ON, and when the CD signal 160 is OFF, by fixing it to the value immediately before it turned OFF, the phase and frequency of the timing clock of the receiving device can be updated to prevent line failures. By fixing the input timing signal to the input timing signal sent from the transmitting device immediately before the occurrence, even in the longest line failure ever, the meaning of the timing slot will not shift after the failure is recovered, and the phase of the reception timing clock will be maintained. In addition, it is possible to draw in an internally generated timing clock. Each circuit within the receiver can continue to operate during a line failure due to the internally generated timing clock according to the present invention.

Note that the accuracy of the timing clock of the transmitter is CCI
Taking TT convention v, 37 as an example, 1 = t: sopp
An accuracy of m is required. To achieve this goal, a crystal oscillator is often used in transmitting devices. The frequency of a crystal oscillator is affected by temperature and voltage, but during stable use, for example, for one minute, the frequency is 1×
A stability of 10 is easily reached.

Therefore, the time required for a 144 kbps pulse to generate a 05 pulse and a phase difference when the line is disconnected is:
If the receiver uses a voltage-controlled crystal oscillator and has the same accuracy as the transmitter, the time will be about 17 seconds. This is a 170 times improvement compared to 0.1 seconds for modems using current technology.

Effects of the Invention As described above, when the signal notifying whether the input timing signal is normal or not is normal, the phase of the internal timing signal and the input timing signal are compared at regular intervals, and the phase of the input timing signal is obtained from the comparison. A signal according to the phase difference is used to bring the frequency and phase of the internal timing signal closer to the input timing signal, and when the signal notifying whether the input timing signal is normal or not is negative, this signal is determined to be negative. By configuring the structure so that the corrected values that were made at the time of normal operation immediately before the change are held as the frequency and phase of the internal timing signal, the meaning of the timing slot is not deviated, and the failure time T of the line where the timing signal cannot be received correctly can be maintained. The effect can be increased by dogs.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of elements of a reception timing signal generation circuit in an embodiment of the present invention, FIG. 2 is a block configuration diagram of a control signal generation section in the same circuit, and FIG. 3 is a block configuration diagram of the control signal generation section in the same circuit. FIG. 100... Control signal generator, 110... Voltage controlled oscillation circuit, 120... Frequency divider, 130... Phase comparison circuit. Name of agent: Patent attorney Toshio Nakao (1st person)
Figure 2 Figure 3r171

Claims (1)

[Claims] internal timing signal generating means for generating an internal timing signal whose frequency is controlled by a control signal that generates a frequency close to the frequency of the input timing signal; and a phase signal generating means for generating a signal corresponding to a phase difference between the internal timing signal and the input timing signal. comprising a comparison means and a control signal generation means for generating a signal for controlling the internal timing frequency from a signal corresponding to the phase difference, and when the signal notifying whether the input timing signal is normal or not is normal; Compare the phases of the internal timing signal and the input timing signal at regular intervals, and use a signal corresponding to the phase difference obtained therefrom to bring the frequency and phase of the internal timing signal closer to the input timing signal, and When the signal that notifies whether the input timing signal is normal or not is negative, a reception timing signal generator that maintains the correction values that were performed when the signal was normal immediately before the signal became negative as the frequency and phase of the internal timing signal. circuit.