JPS6261978B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention generally relates to a digital data processing apparatus;
In particular, formed on a single semiconductor chip
This invention relates to a count pulse generator included in a MOS/LSI microprogram computer.

Significant improvements in computer control are achieved by using memory logic stored in high speed non-destructive permanent memory (ROM) or microprogrammed control instead of conventional transistor logic devices. Microprogramming makes it possible to incorporate the same comprehensive industry standard instruction set (operating code) into new computer lines that are architecturally compatible but may have different internal hardware, organization, and structure. Ta.
Yet another advantage provided by the microprogramming approach is that it minimizes the geometry of circuit logic functions that can be implemented with MOS/LSI circuit technology.

A general understanding of digital computers is necessary to understand the purpose of the present invention.
Any data processing device, including a digital computer, has five separate functional sections: input, storage, arithmetic logic unit (ALU),
Can be organized from output and control. These functional sections are interconnected by electronic signals representing data, commands and control signals. The order, timing and direction of information flow within and between these functional sections is determined by the control section. The control section directs the operation of the entire computer. This control section receives information units from the storage section that indicate which operation is to be performed and where in the storage section the data to be operated on is located. After the control section has determined the exact structure to be performed, this control section issues control signals to open or close certain gates in the system, and the necessary data in the form of electrical signals are used to carry out that operation. flow from one functional unit to another. When the arithmetic and logic section performs its function, the control section issues the necessary control instructions and causes the results to be transmitted to the storage section or channeled to some output device and stored on another storage medium. At the end of execution of an instruction, the control section advances the computer to fetch and decode the next instruction. Microprogram control to a digital computer allows control of microspect functions (adders, shifters, and other hardware) using minimal form factor and very low load MOS/LSI logic functional elements. It became possible. A general object of the present invention is to provide a microprogram computer system with improved performance and high packaging density. In particular, it is an object of the invention to provide such a microprogram computer system that can be implemented on a single semiconductor chip using MOS/LSI technology.

The microprogram computer of the present invention includes:
Implemented on a single semiconductor chip using MOS/LSI technology. The computer includes a data processing unit having a control logic unit, a unit for exchanging data with peripheral devices via at least one data transfer port, and a set of microprograms storing instructions issued by the control logic unit. and an arithmetic logic unit that performs operations on data words under program control. A binary timer is provided to enable the system to operate in interval timer mode, pulse width measurement mode and event counter mode. The binary timer cooperates with the interrupt logic to process interrupt requests in response to timeout signals from the binary timer and in response to external interrupt requests. In the preferred embodiment, the derivative of an external interrupt request is synchronized with the system clock cycle such that the interrupt request decode operation is performed by the main control logic during the same clock cycle in which the interrupt request occurs. The maximum bit rate at which sequential information is sampled through the external interrupt request input is thereby increased.

The novel features and other features and advantages which characterize the invention, both in terms of its mechanism and method of operation, will be better understood from the following description of a preferred embodiment, taken in conjunction with the accompanying drawings, in which: FIG.

FIG. 1 shows a microprogram computer 10 that is implemented using MOS/LSI technology and can be formed on a single semiconductor chip. The main functional sections of this microcomputer 10 are input-output ports 12, 14, 16 and 1.
8. port selection logic 20; program and data storage fixed memory (ROM) 22;
an arithmetic and logic unit (ALU) 24 and a main control logic unit 26. These main functional sections communicate with each other via signals representing data, commands and control signals during execution of the data processing program. The order, timing and direction in which this information flows through computer 10 is determined by main control logic 2.
6. This main control logic unit 26
is instructed by a sequence of machine language instructions or program instructions stored in ROM 22. Next, the main and auxiliary components of this microcomputer 10 will be explained in detail.

Input/output ports Input/output (I/O) ports 12, 14, 16
and 18 are identical except that an address is assigned to each port by master control logic 26. These ports will be referred to below as ports 0, 1, and 1, respectively, following normal instruction set nomenclature.
4 and 5. I/O on behalf of each port
Port 4 will be explained next.

I/O port 4 is an 8-bit latch containing logic circuitry that commands this I/O port 4 to load incoming information onto main data bus 28 upon command from load signal LD in combination with signal ENA4. . This loading is synchronized with clock signal ΦC so that the data on data bus 28 is stabilized. Data from the data bus is 8 bits 2
It is given to I/O port 4 in the form of a forward word. This word can be a binary coded decimal word, or a binary coded decimal word that represents a character to a peripheral device (PE) such as a printer.
It can be a hex code. Data from the data bus originates from an accumulator 30, which is part of the computer's data processing subsystem. For any data output to I/O port 4, main control logic 26
controls various gates such that information stored in the I/O port 4 is routed through the data bus to the I/O port 4. Port 4 then retrieves the information from the data bus and latches it in synchronization with the ΦC clock.

Another task performed by logic block I/O port 4 is to read the voltage level at its input pins. This is the enabling signal
This is done when PORT4ENA becomes active and load signal LD remains inactive. Information on input pins from peripheral devices is driven onto the main data bus 28 and routed through various gates to the final destination, an accumulator 30.

I/O port 4 has yet another function that it performs in test mode. When an input signal is activated, that is, when the voltage level corresponding to this signal drops to a low level corresponding to a logic "1", instead of selectively retrieving information from the data bus 28, the I/O port The 4 logic block always takes data from its data bus and supplies it directly to its input pins. This operation is not synchronized with the ΦC clock. It provides a direct path around the internal latch circuit. It disables the internal latch circuits so that they do not drive the port pins and instead logically connects the port pins directly to the internal data bus 28.

Port 5 has the additional feature that when the signal input to port 5 drops to a low voltage corresponding to a logic "1", port 5 takes the information present on that pin and drives it onto the internal data bus 28. functions in test mode.
This causes port 5 to be the assigned input to the internal data bus during test mode and port 4 to be the assigned output from the internal data bus, thus providing a test signal to the internal data bus through port 5. An external tester can be used to input and monitor the internal data bus to verify this test through port 4.

Input/output ports 0, 1, 4 and 5 are fully bidirectional input/output ports. Further, an interrupt control port 32, which will be described later, is addressed as port 6. Further, a binary timer 34, which will be described later, is addressed as port 7. Output command (OUT
or OUTS) causes the contents of accumulator 30 to be latched to the addressed port.
An input command (IN or INS) causes the contents of that port to be transferred to the accumulator 30.

Strobe Logic Strobe logic 34 is associated with I/O port 4 operation. The strobe logic 34 provides a single pulse output signal after the I/O port 4 is loaded with new data. In its basic mode, strobe logic 34 is responsive to the combination of an active signal PORT4ENA and an inactive load signal LD indicating that new data is being loaded from data bus 28 into the latch circuit of I/O port 4. do. At this time, the strobe logic delays its information for one cycle of ΦC, thus generating a single negative going pulse that remains low for two cycles of ΦC and then rises. This flag can be used to signal a peripheral device (PE) that computer 10 is finished outputting new data to port 4. This delay ensures that the new data is latched into the port 4 latch and stabilized before the strobe signal is routed to the peripheral.

The second function of strobe logic 34 is to provide a synchronization clock to the external tester during test mode to indicate what machine cycle the computer is in. This information is given as the inverse of the clock cycle ΦC. When the signal to the strobe logic is active, the strobe output is simply the inverse of ΦC. Its output determines when machine cycles begin and end within computer 10 to coordinate the driving of information onto data bus 28 and the strobing of information from the data bus via ports 5 and 4. ΦC is inverted so that the tester is informed.

Another input to strobe logic 34 is signal R from main control logic 26, which is used to inhibit the strobe output. Signal R is active during the reset state of the machine which causes the execution of the test routine to be synchronized with the ΦC clock. For example, in test mode, the strobe output may be active and an external tester may drive data to port 5 and read data from port 4. However, the computer 10 is still in reset, and even if there is sufficient voltage to operate the clock generator, there is no guarantee that there will be sufficient voltage to operate the rest of the circuit, so Computer 10 may be held in reset by internal power-on clear logic located in main control logic 26. Therefore, while computer 10 is in the reset state, the main control logic inhibits the strobe output from becoming active. As soon as the computer 10 starts executing its first instruction, i.e. as soon as the computer is reset, the strobe output indicates that the tester is synchronously driving the instruction to port 5 and valid data from port 4. Start generating a ΦC inversion pulse that makes it acceptable.

Clock Generator The timing signals required to establish the proper operating cycle are provided by clock generator 2.
8. For purposes of the present invention, the clock circuit may be of conventional construction and may consist of a crystal controlled oscillator and a counter circuit. In the preferred embodiment, there are four external modes and one internal mode. In external mode, clock generator 38 takes an external timing reference and generates three system clocks: ΦF (fast clock), Φ
A logic device that generates C (main cycle clock) and ΦE (early cycle clock). If an external crystal is connected to XTL1 to the clock generator
If connected between the input and the XTL2 input, the clock generator generates a ΦF high speed clock that is one-half the oscillation frequency of the crystal. The timing reference may be applied by an external solder capacitor network or an external resistive capacitor network. In another operation mode,
The timing reference may be provided by an external timing source in the form of a square wave or sine wave or other pulsating signal. The clock generator 38 has XTL1 and
Contains an internal oscillator that is activated when both XTL2 pins are grounded.

The ΦC signal is the cycle clock for computer system 10. This ΦC signal defines a complete machine cycle. All gating of information onto the bus and all acceptance of information from the bus occurs during a single ΦC cycle.
The length of the ΦC cycle can be 4 or 6 ΦF clock cycles. The reason for having short cycle and long cycle ΦC clock signals is that
This is because certain complex data transmissions require longer times, such as data traveling over several internal buses from an original point to a destination point with inherent propagation delays. For these operations, main control logic 26 instructs the clock generator that the clock cycle is to be extended from four ΦF periods to six ΦF periods. This is accomplished by the signal LONG from main control logic 26 to the clock generator.

The ΦE clock signal is an auxiliary clock having the same period as the ΦC clock. The difference between these two is that the ΦC clock generates a single positive going pulse during the last ΦF period of the machine cycle. That is, for short cycles, Φ
The C clock goes to a logic "0" level at the beginning of the cycle and remains at that level for three ΦF cycles, then goes to a logic "1" level for one ΦF cycle, and then returns to a logic "0" level. For long cycles, the ΦC clock is
It remains at a level corresponding to a logic "0" for five ΦF periods, then goes to a voltage level corresponding to a logic "1" for a single ΦF period, and then returns to "0". The fall of the ΦC clock from a logic "1" level to a logic "0" level is defined as the end of the cycle and the beginning of the next cycle. The ΦE clock therefore goes from a low level to a high level at the beginning of a machine cycle. The ΦE clock remains high for the first two ΦF periods of the machine cycle and then goes low for the remainder of the machine cycle.

One example of the use of the ΦF clock is to transfer information to and from scratchpad register 40, as described below. Information is transferred from scratch pad register 40 during the early part of the machine cycle when the ΦE clock is at a positive level. When the ΦE clock goes low, the information from the scratchpad is latched and cannot change, so during that same cycle new information enters the scratchpad and changes the actual register without changing the output of the scratchpad 40. can do. The use of the ΦE clock is for auxiliary purposes and essentially provides a single pulse in the early part of the machine cycle, while the ΦC clock provides a single pulse at the end of the cycle without overlapping. give.

Port Selection Logic The basic function of port selection logic 20 is to select the logical port element to be read or written. Main control logic 26 directs which particular ports are addressed according to the currently executed instruction. During the operation of the output instruction, the port number is placed on the internal data bus 28, i.e. the contents of the internal data bus are placed on the internal data bus 28.
is driven to number 04 indicating that it is being addressed. Port selection logic 20 scans internal data bus 28 and holds the information for one cycle. If the read high (RD HI) or load high (LD HI) signal is active, and if the port address was on the data bus during the previous cycle, then the address of the number that was on the data bus during the previous cycle is port is addressed. When that particular port is accessed, if the port is to read data, the main control logic 26
activates the read high signal RDHI. The presence of an active load high (LD HI) signal during the cycle following the cycle in which the port address was on the data bus indicates that the port addressed during the previous cycle has information currently present on the internal data bus 28. This indicates that the received information is latched into the latch circuit.

Regarding port 7, binary timer 36, if a read operation is to be performed, the signal is activated, and if a load operation is to be performed, the signal LT is activated. Also, the load ICP and read ICP signals of the interrupt control port 32 are activated.

The way ports 0 or 1 are addressed is somewhat different from the way ports 4 and 5 are addressed. When port 0 or 1 is addressed, that address was not driven onto the data bus in the previous cycle. Alternatively, if port 0 or port 1 is activated, the read low signal
RD LO or load low signal LD LO becomes active during that cycle. At this time, the port selection logic corresponds to the least significant bit of instruction register 42.
Determine the state of the IRO signal. If the signal is in a logic "0" state, it indicates that port 0 is to be accessed. If that signal is in a logic "1" state, it indicates that port 1 is to be accessed. Therefore, it connects signal port 1 in the same way as ports 4 and 5.
ENA and load signal LD are used to access port 1, but unlike ports 4 and 5, selection of port 0 or 1 is via signal RD LO or LD LO
and the specific state of the IRO signal.

The signal R input to port selection logic 20 is an inhibit signal from main control logic 26 indicating that computer 10 is in a reset state.
When in the reset state, computer 10 loads while the inhibit signal is present. However, since there are no driving elements on the internal data bus 28, the contents of the internal data bus 28 are 00, and thus the input/output ports are initialized to the known 00 state. One exception to this embodiment is that ports 0 and 1 are not initialized during reset, maintaining their previous contents.

Interrupt Control Port Interrupt control port device 32 is referred to as port 6 within the computer system. The ICP or interrupt control port 32 is an 8-bit write only latch. When the signal LOAD ICP is active,
Data present on the main data bus 28 to the interrupt control port 32 is latched into the interrupt control port latch circuit, synchronized with the ΦC clock signal, and thus sent to all of the latch outputs during the first clock cycle following the LOAD ICP signal. Given. Instead of enabling the information stored in the interrupt control port's latch circuit to the main data bus at the appropriate time, when an instruction is executed to read the interrupt control port 32, the voltage level on the external interrupt pin 46 Enabled to bus bit 7. Nothing is enabled on the other data bus pins, so they assume a logic "0" state. Therefore, instead of actually reading information at the interrupt control port latch, when an instruction input from port 6 is executed, the logic or voltage level of the external interrupt pin is transferred to data bus bit 7 (DB7).

Interrupt Logic In a microprogram computer system, an interrupt signal is a request or command to the main control logic to halt execution of a currently executing sequence of instructions and to execute another sequence of instructions in its place. Some are called unmasked interrupts, meaning they are instructions rather than requests that cannot be denied. An interrupt that can be masked is not an instruction, but a request for the main control logic to execute a different sequence of instructions than the one it is currently executing.

The function of interrupt logic 44 in computer system 10 is to provide requests to the main control logic in response to inputs from binary timer 36 or external interrupt pin 46. If the main control logic in response to the request wishes to execute the request, it sends three signals:
FREEZE signal, path interrupt vector low or IVL
Interrupt logic 44 is signaled by the signal and the path interrupt vector high or IVH signal. In response to the three signals, interrupt logic 44 passes the appropriate address onto data bus 28.

The active state of the external interrupt signal is determined by the EDGE input to interrupt logic 44. In order to generate an external interrupt signal during normal interrupt operation, the logic state of the signal on the EXT INT pin 46 requires an active transition from a logic 0 to a logic 1. This transition is gated by the external enable signal EXT ENA, which acts as a toleration function for external interrupt requests. To generate a normal external interrupt request for the main control logic,
The interrupt logic must first have the EDGE bit properly defined at a logic "0" or "1" and an external interrupt enable signal at a logic "1". If an inactive to active transition of a signal on the external interrupt pin occurs, it passes an interrupt request to the main control logic by pulling that signal to a low voltage or active state.

Interrupt logic 44 also provides a binary timer signal.
An interrupt request is passed to main control logic 26 in response to TIME OUT. When the TIME OUT signal is activated, interrupt logic 44. binary time 36
is notified that it is performing its proper functions and may conditionally pass the interrupt request to main control logic 26. Interrupt logic 44 passes interrupt requests to the main control logic when the timer enable bit is activated. If the timer enable input is inactive when the TIME OUT signal generates its pulse, the information that TIME OUT has occurred is retained until the timer enable input is activated.

However, when an appropriate transition occurs on the external interrupt input that would normally result in an interrupt request, the interrupt logic 4
If the external enable input to 4 is inactive, then the interrupt logic ignores external interrupt requests. When the timer generates a TIME OUT pulse, the external interrupt logic latches that pulse and if the timer enable input to the interrupt logic is active, it passes the interrupt request to the main control logic.

According to another condition, if the LT signal becomes active, it remains in the interrupt control logic 44.
Clears stored information related to TIME OUT pulses. For example, if a TIME OUT pulse occurs and the timer enable input to the interrupt logic is inactive, the information that a TIME OUT pulse has occurred is latched into the interrupt logic. However, if the LT signal goes active, the TIME OUT signal latch in interrupt logic 44 is cleared. If the timer enable signal TIMER ENA to the interrupt logic subsequently becomes active, no requests are passed to the main control logic. This is because the request is cleared by activating the LT signal.

Another output of the interrupt logic, other than the interrupt request output IRQ, is the differentiated version of the external interrupt signal, referred to as EXT INT'. Signal EXT INT' represents the logic state of external interrupt input 46. This signal is appropriately buffered and used so that an input or read ICP instruction from port 6 is executed to drive data bus 7 rather than having an external interrupt pin drive data bus 7 directly. It is used when

Interrupt requests are interrupts that can be masked, so
Main control logic 26 can choose to ignore or allow interrupts through separate enabling and disabling circuits. If the main control logic unit 26
If the interrupt is in the appropriate state to accept an interrupt request, it responds to the interrupt logic using three control signals. The first control signal is the FREEZE output which is activated for one cycle to prevent the interrupt logic from changing its current state. Following this freeze cycle, the main control logic performs a single ΦC cycle delay. During this delay cycle, virtually no computer operations occur. This delay allows the interrupt logic to fully stabilize. During the next two cycles, main control logic 26 requests that interrupt logic 44 load the address of the next program instruction onto data bus 28.
In response to an interrupt request, main control logic 26 interrogates the interrupt logic with an interrupt vector signal to determine the address of the next sequence of instructions. This is referred to as a vectored interrupt where the interrupt logic responds directly to the address of the next instruction sequence. For example, in response to an external interrupt request, interrupt logic 44 may provide location 00A0 for the beginning of a new instruction sequence. If it is responding to a TIME OUT signal from the interrupt logic, that interrupt logic will give address 0020, for example, to the main control logic, so the next instruction to be executed will come from that location. directs the information to its appropriate address register.

In this embodiment, fixed memory (ROM) 22
An 11-bit address is required to access all of the bytes in. However, data bus 28 only has a capacity of 8 bits. Information is passed to internal data bus 28 so that
It is first passed in groups of 8 bits, then
Three other bits are passed. Therefore, when the main control logic requests that the interrupt logic pass an interrupt vector, it must first request the low portion of the vector and then request the high portion of the vector. The decision to pass the high part of the vector following the low part of the vector is arbitrary in this example.

To illustrate an example, assume that external interrupt pin 46 is properly activated and a request is made by interrupt logic 44 to main control logic 26 for an interrupt. Assume that after this, but before main control logic 26 accepts the request, binary timer 36 generates a TIME OUT pulse. Interrupt logic 44 maintains its requests to main control logic 26, with two requests outstanding at this time. One request is made via external interrupt pin 46.
The other request is from binary timer 3.
It comes from 6. In this example, the binary timer 36 inputs are given priority over the external interrupt inputs. That is, if a timer interrupt request occurs, timer vector address 0020 is passed to data bus 28 and then to address register 0020 where the next instruction is stored in ROM 22.
It will be executed from Then, when main control logic 26 executes the instruction placed at location 0020,
It requests a vector of outstanding external interrupt requests, and interrupt logic 44 passes vector 00A0 onto data bus 28.

The purpose of the FREEZE signal is to ensure that main control logic 26 only accepts the interrupt with the highest priority present in the interrupt logic at that time. The FREEZE signal allows the vector to pass through completely even if a higher priority interrupt request occurs during the vector's transmission. That is, interrupt logic 44 is instructed to completely pass the vector while the vector is being passed, regardless of what subsequently happens to the external interrupt input or the timer TIME OUT input. After the FREEZE signal occurs in the next ΦC cycle, the interrupt logic is given time to decide which vector to pass. Then, the third Φ
In the C cycle, the main control logic activates the IVL input to the interrupt logic, so that the interrupt logic passes the lower eight bits of the interrupt vector onto the data bus 28. 4th ΦC
In the cycle, the main control logic 26
The IVH signal is activated, and in response to that signal, interrupt logic 44 passes the upper half of its interrupt vector onto the data bus.

A FETCH signal is generated from main control logic 26 in response to the new address passed by the vector. Two other outputs are interrupt logic 4
They are defined as START2 to binary timer 36 and auxiliary clock signal AUX CLOCK to timer 36. These signals are suitably buffered and run in a binary timer 36.
synchronized to enable and disable.

Arithmetic and Logic Unit (ALU) ALU 24 performs the arithmetic and logic operations required to process program instructions. ALU 24 is a component of a data processing device that includes shifter selector 50 and complement arithmetic unit 52. This device is capable of performing arithmetic, shifting, and logical operations on operands. ALU24 is basically 2
A set of logic elements having two main inputs, an A-bus and an S-bus. These buses are so named because accumulator 30 is the primary data source for the A-bus and scratchpad 40 is the primary data source for the S-bus. There is a main 8-bit data output designated by reference numeral 54. This is referred to as the result bus, which is basically the logical result of the operations performed on the A-Bus and S-Bus inputs.

Another set of outputs on bus 55 from ALU 24 represent the resulting state of the operation most recently performed in the ALU. Status registers 56 are used to store these status signals for use in later computer operations.
Status register 56 holds five status flags: sign, carry, zero, overflow, and interrupt control bits.

The carry signal CRY to ALU 24 represents the state of the carry flip-flop in status register 56. This information is represented in the form of a logic ``1'' or ``0'' indicating that a carry of the high order bit occurred as a result of an ALU operation, and the information is latched into status register 56 and later stored. It can be used for ALU during the operation cycle. Also, a complete set of status bits from status register 56 is available to the ALU via the A-bus. One of the status outputs from the ALU, in addition to providing input to the status register, goes directly to the control logic. This is a ZERO signal.

There are several control inputs from main control logic 26 that cause the ALU to perform specific operations on various data inputs. One of these control inputs is ADD, which commands the ALU to perform a binary addition of the A-Bus and S-Bus inputs. Another control input to ALU 24 is referred to as OR, which commands the ALU to perform a forward-OR function on the A-Bus and S-Bus inputs. There are exclusive or (XOR) and AND control lines for operating on two input data sets. Also, increment only the A-bus input.
There is an incremental line INC that commands the ALU. There is a decrement control line DEC that commands the ALU 24 to decrement the S-bus. Therefore, the decrement line DEC
When activated, the information on the S-bus has its value decremented by one bit and the result placed on the result bus. Add the data content of the A-bus to the data content of the S-bus and add it to the carry input.
There is an add carry line that commands the ALU.

Another control signal is the BCD adjustment signal (BCDADJ), which is used to perform binary coded decimal arithmetic operations. ALU24 is basically:
A binary addition is performed, and the result of the binary addition can be adjusted so that its contents represent two decimal digits. For example, if hex 99 were added to hex 22 and a normal binary addition was performed, the result would be BB, representing the particular code of the data bus. However, display B is not an acceptable data decimal digit. It is only an acceptable binary or hexadecimal representation for a binary stream. Therefore, the desired result would not be BB, but 21 with a high carry from the remainder. Therefore, ALU2
4 performs a binary addition, but the result is adjusted after the binary addition is complete so that the amount is transferred from binary format back to decimal digit format.

Complement Arithmetic Unit Associated with the A-bus input to ALU 24 is complement arithmetic unit 52 . The complement unit 52 inverts the bits on the A-bus before passing them to the ALU. This complement arithmetic unit 52 is activated by the COMP signal input. If the COMP signal is a logic "0", the data passes through complement unit 52 unchanged.

Selector/Shifter The A-bus input to ALU24 requires a selector/shifter.
A combination of shifters 50 is associated. Selector/shifter 50 can perform six different functions. One data input comes from accumulator 30 and a second data input comes from status register 56. Selector 50 may forward the contents from the accumulator to the ALU without modification. Similarly,
Sector 50 may transfer the contents of status register 56 unchanged to the ALU. This is each
This is done in response to the ACC-ALU and STAT-ALU signals. Sector 50 may also perform other functions on the accumulator input in response to the shift input. That is, selector 50 takes data present on the A-bus and shifts it one or more bits to the right or left in response to a shift right or shift left command from main control logic 26.

Accumulator Accumulator 30 is simply an 8-bit latch. The accumulator 30 is connected to the ALU result bus 5.
4 and an output coupled to selector shifter 50. Upon activation of the control signal LD_ACC, the information present on the result bus is latched into the accumulator and synchronized with the ΦC control clock.

Status Register Status register 56 has four inputs from ALU 24. These inputs represent the current state of the results of ALU operations. Upon command from the SET STATUS input signal, the status register receives information present on the new status bus 55 coupling the ALU to the status register 56 and latches that information into the status register bits.
The fifth status register bit represents an interrupt control bit for the main control logic. This prevents the main control logic 26 from allowing interrupt requests from the interrupt logic, even if the external enable or timer enable bits have enabled the interrupt logic bit 44 to pass the interrupt request to the main control logic. This bit is used to command the
If the interrupt control dot maintained in status register 56 is zero, main control logic 26
ignores the interrupt request and continues processing the instruction sequence it is currently processing. However, if the interrupt control bit in the status register is a logic ``1'', main control logic 26 will make the decision to grant or disallow the interrupt request as soon as it has finished executing the currently participating instruction. commanded to do.

Interrupt control bit ICB of status register 56 is
Controlled by main control logic 26 using the CLEAR ICB and SET ICB signals.
When the CLEAR ICB signal is activated and synchronized with the ΦC clock input, the interrupt control bit is driven to a logic ``0'' state. When the SET ICB signal is activated and synchronized with the ΦC clock, the ICB bit is set to a logic "1". status register 56
The ICB bits of can also be changed by the LOAD STAT signal which causes the contents of result bus 54 to load all five bits of status register 56.

Scratchpad Register The scratchpad register 40 is a general-purpose RAM.
A large number of 8-bit registers, for example 64, are provided to be used as memory. This set of registers is used to store variable data during program execution. Scratchpad register 40
may be loaded from the result bus 54, ie, the result of the ALU 24, when commanded by the RESULT-SPAD control input. When this signal is activated and synchronized with the ΦC clock, the data currently present on result bus 54 is loaded into the appropriately addressed register.

The scratchpad register array 40 is
Single 8 driving to S-Bus input to ALU24
Has bit output. Synchronized with ΦE clock
When commanded by the SPAD-S-Bus signal, the scratchpad 40 transfers data from the scratchpad address register to the S-Bus of the ALU 24. Thus, data is read from the scratchpad 40, which is synchronized with the ΦE clock, and written to the scratchpad, which is synchronized with the ΦC clock.

Another input to scratchpad 40 is a 6-bit register address. This is each register 0
-64 comes from the SPADR bus to be addressed.

The S-Bus is the second basic input to ALU 24. One information input is provided to the scratch pad 4 in response to a signal SPAD-S from the main control logic 26.
It comes from 0. The second source of information for the S-bus is
These are the lower 4 bits of the instruction register 42, and the signal
In response to IR-S, the four least significant bits of instruction register 42 are transferred to the four least significant bits of the S-bus, the upper four bits of the S-bus containing zeros.

Another possible input to the S-bus is the ISAR or indirect scratchpad address register 58.
It comes from Active ISAR-DATA BUS
In response to the signal, ISAR sets the 6 bits of ISAR to S-
It is transferred to the lower 6 bits of the bus, and the upper 2 bits are 0. ISAR can be displayed as holding two octal digits. This division of the ISAR is important because when using the ISAR to reference a scratchpad byte, many instructions increment or decrement only the three least significant bits of the ISAR. This makes it easy to refer to a buffer of consecutive scratchpad bytes.

Another source of information on the S-bus may come from main data bus 28. Control signal DATA
In response to BUS-S, the eight bits of data bus 28 are transferred to the eight-bit S-bus.

If none of the above possible elements is driven to the S-Bus, the contents of the S-Bus is zero. To understand the significance of this condition, consider the case where it is desired to transfer the contents of accumulator 30 to the main data bus without changing that information. to the shifter 50 to carry out this process.
ACC-ALU input is activated. This results in
Information from accumulator 30 is transferred through shifter 50 to complement arithmetic unit 52 without changing its output. Since the complement control to the complement unit 50 is inactive, the information passes directly through the complement unit unchanged and the contents of the A-bus are essentially the contents of the accumulator 30. This is because no shifting or complement operations are performed. The ADD signal to ALU 24 is active. This causes the result bus to contain the binary sum of the contents of the A-Bus input and the S-Bus input. However, if no driving element is selected to drive the S-Bus, the contents of the S-Bus are zero. Adding zero to the contents of the A-bus produces a result equal to the contents of the A-bus. Therefore, the information on the A-bus coming from the ACC passes through the ALU to the results bus 54 without actually being modified. From the result bus, the data is transferred to data bus 2
8.

Scratchpad Address Bus The source of addresses for the scratchpad register array 40 is the scratchpad address bus 6.
It is 0. Scratch pad address bus 60
is a 6-bit bus that allows all 64 scratch pad registers to be accessed.
The six bits of ISAR can be driven to the scratchpad address bus in response to control signal ISAR-SPADR. Another source of information for the scratchpad address bus 60 is the four least significant bits of the instruction register 42. In response to the signal IR−SPADR,
The lowest four bits of the instruction register are transferred to the lowest four bits of the SPADR bus, and the upper two bits of SPADR are zeros. A final possible source of information is the 4-bit register address bus 61 generated by the main control logic 26. A 4-bit register address is generated directly by main control logic 26 in response to control signal REG ADDR-SPADR, which corresponds to a register address to the scratchpad address bus. It is transferred to the address bus 60. This allows main control logic 60 to directly access the 16 lowest registers of the scratchpad register array in response to certain instructions.

ISAR Logic Unit ISAR logic unit 58 is an indirect scratchpad address register. In this embodiment, it is a 6-bit register that can be used to supply the address of a scratchpad register in scratchpad array 40. Input to ISAR comes from result bus 54, which is the result of ALU operations. and the main control logic unit 26
There are some control inputs from In response to the LOAD UPPER1 signal from the main control logic, the fourth, fifth and sixth most significant bits from result bus 54 are loaded into the upper three bits of ISAR 58. LOAD UPPER2 from main control logic
In response to the signal, the lower three bits of the result bus
Charged to the upper 3 bits of ISAR. In response to the LOAD LOWER3 signal from the main control logic, the lower three bits of the result bus are loaded into the lower three bits of ISAR.

Therefore, ISAR can be loaded in three different ways. All six bits of the ISAR transfer the lower three bits from the result bus 54 to the lower three bits of the ISAR and transfer the fourth, fifth, and sixth most significant bits of the result bus to the upper three bits of the ISAR. It can be loaded in one go by transferring it to the bit. To perform this operation,
Both the LOAD LOWER3 and LOAD UPPER1 signals are activated at the same time. Also, either half of the ISAR can be charged. The upper 3 bits of ISAR remain unchanged while the lower 3 bits
Bits can be loaded with new information. In this case, the information is passed to the results bus and LOAD
In response to the LOWER3 signal, only the lower three bits of ISAR are loaded from the lower three bits of result bus 54. If it is desired to change the upper 3 bits of the ISAR while leaving the lower 3 bits of the ISAR unchanged, this loads new information into the results bus 54 for the upper 3 bits of the ISAR.
This can be done by activating only the LOAD UPPER2 signal.

The transfer of information from results bus 54 to ISAR 58 is synchronized by the ΦC clock. Moreover, ISAR
The contents of the lower three bits of can be incremented, decremented, or left unchanged. Therefore, in response to the increment signal INC, the contents of the lower three bits of ISAR are provided to the ISAR output, when synchronized with the ΦC clock at the beginning of the next machine cycle.
The new contents of the lower 3 bits of ISAR are 1 greater than in the previous cycle. In response to the decrement signal DEC, the contents of the existing ISAR are driven onto its output bus at the end of the cycle, and the information loaded back to the ISAR is the same except that the lower three bits are decremented. This allows the 8-bit section of scratchpad 40 to be easily accessed without reloading the ISAR.

Instruction Register Instruction register 42 receives instructions to be executed from program ROM 22 via data bus 28. Eight bits are latched into instruction register 42 during all operation code fetches. Some instructions are completely specified by the upper four bits of the OP code. In these instructions, the lower four bits are an immediate register address or an immediate four-bit operand. When latched into instruction register 42, main control logic 2
6 decodes the instruction and provides necessary control gating signals to all circuit elements. Command register 42 removes information from main data bus 28, and in response to a control signal FETCH synchronized by the ΦC clock, command register 42 latches information from its inputs into its internal latches and provides the information to its outputs. . The output of the instruction register is 8 bits of a latch that is routed to main control logic 26. Additionally, the four least significant bits are also conveyed to the S-bus and the scratchpad address bus through appropriate gating circuits. The least significant bit, IRO, is one of the outputs provided by instruction register 42 for port selection logic 20 as described above.

ROM Address Registers Associated with ROM address register array 48 are four registers. There is a program counter (PC), a stack register (P), a data counter (DC) and an auxiliary data counter (DC1). The program counter is used to address instructions or immediate operands. The stack register is used to store the contents of the program counter during interrupt or subroutine calls. Data counters are used to address data tables. READ/
In addition to the WRITE input there is a control input from main control logic 26 for each of these registers. Register input is address register array 4
8, while the READ/WRITE input indicates whether that register is enabled to the address register output line or the information on the address register line is written to that register. used to. Lines from the address register array are therefore bidirectional and depending on the state of the READ/WRITE signal, information on those lines is either sourced from the address register or written to the appropriately addressed register. Determine.

In response to the appropriate register being addressed and the READ line being activated, register contents are driven onto the address register output bus 62. This is a bidirectional bus; if the READ/WRITE line is in the read state, the information is driven onto bus 62. At that point, it's lachi 64
and is transferred to adder/incrementer 66. While the ΦE clock is active, the information present on the input bits of address latch 64 is transferred through the latch to its output bits. When the ΦE clock is inactive, the information at the input to latch 64 may change, but the output of the latch remains the same. Therefore,
Early in the cycle when the appropriate register is being addressed, the READ line is placed in a read state and information is driven from register 48 to ROM address bus 68. When the ΦE clock is inactive, the information on the address register bus 62 may change, but the information on the ROM address bus does not. This is because address latch 64
This is because it is stably held by .

Adder/Incrementer Associated with ROM address register array 48 is adder/incrementer 66 . This logic element can be placed in register PO or register as required.
Increase DC and also register PO of related branch
It is also used to add a displacement to register DC, or in an add data counter (ADC) instruction.
It is also used to add data bus contents to the data bus.

Adder/incrementer logic block 66 performs the basic function of maintaining the proper addresses in address register 48 as controlled by main control logic 26. While executing a set of instructions, unless an instruction branch or jump is encountered, the program counter sequentially executes the particular set of instructions it is executing. In such a mode of operation, adder/incrementer 66 and address latch 64 receive an address from address register array 48 early in the cycle when the ΦE clock is active, and receive an increment from master control logic 26. Adds 1 to the address on address bus 68 in response to the command. When the ΦC clock goes active, it drives the incremented information back onto the ROM address bus and if the main control logic
READ/in ROM address register file
If the WRITE line has been switched from the READ state to the WRITE state, the incremented information is loaded back into the program counter of address register 48.

There are several instances in which it may be desirable to transfer information in ROM address register array 48 to a location on scratchpad 40. For example, when an interrupt is executed, the current contents of the program counter are stored or placed in stack register P, and the program counter is populated with the vector address provided by the interrupt logic. The next instruction to be executed begins at that vector address. 1st
If a second interrupt occurs while the second interrupt routine is being executed, the contents of the program counter are stored in stack register P and the new instruction sequence location is loaded into register PCO. However, the information previously in register P was the address to which execution should return when all interrupts are taken. In this case, if the second interrupt occurs, register P
information (original contents of the program counter) will be lost. Therefore, under certain conditions,
It is desirable to store the contents of register P in protected storage where certain program events cannot easily cause another number to be reloaded. Therefore, it is desirable to provide a data path for transferring the contents of the address registers to the scratchpad register array 40.

To transfer the contents of the address register to the scratchpad register 40, the main control logic 2
6 selects the appropriate register in the address register file and selects it to be read. Therefore, the contents of the selected register are driven on ROM address bus 68 to adder/amplifier 66. When the data capacity of the address register is larger than the data capacity of the internal data bus,
More than one machine cycle is required to transfer the contents of the address register. In this example, the address register has an 11-bit capacity and the data bus has an 8-bit capacity. Therefore, during one cycle, main control logic 26 stores stack register P.
may be enabled to drive the ROM address bus 68. Control signal when activated
The ADL-DATA BUS enables transfer to the 8-bit main data bus 28 below the adder/amplifier 66. The information is transmitted through the main data bus 28 and the main control logic 26 opens the appropriate gates to transfer the information from the main data bus through the ALU 24 to the S-bus and finally to the scratch pad register array 40. . Then, on the next machine cycle, the main control logic again addresses stack register P and asserts the READ line, causing register P to be driven to the ROM address bus 68 and the adder/incrementer. Adder/incrementer control line ADU-DB is activated, causing the adder/incrementer to transfer the upper three bits of the 11-bit address to the lower three bits of data bus 28. Other gating signals through this circuit are such that their information is on the data bus 28.
through and finally to the scratch pad 40.

In some cases, it may be desirable to populate the address registers from scratchpad register array 40 or from some other source, such as program ROM 22. To perform these operations, information is transmitted from the main data bus 28. To transfer information from the main data bus to ROM address register array 48, it must first pass through an adder/incrementer. If control signal
If XFR LOWER is activated, this causes 8 bits of the data bus to be routed to adder/incrementer 66.
is transferred to the lower 8 bits of the ROM address bus. After the appropriate register of address register 48 is addressed and the correct control line is activated, the information is written to the appropriate address register.

To transfer information from data bus 28 to the upper three bits of the address register, adder/incrementer control signal XFR UPPER is activated, which causes the lower three bits of the data bus to
It is transferred to the upper three bits of ROM address bus 68 so that it can be written to the appropriate address register.

Main control logic 26 determines whether to execute the next instruction in sequence or in a jump in the forward or reverse direction. In order to cause the program counter to skip forward or backward for a program branch, it is necessary to apply a positive or negative displacement to the program counter so that the new content is larger or smaller than it would otherwise be. The displacements to be applied to the program counter are contained on data bus 28. Main control logic 26 instructs adder/incrementer 66 to transfer the contents of data bus 28 to adder/incrementer 66 . The main control logic also
ADDRESS-ADDER is used to command adder/incrementer 66 to transfer the contents of ROM address bus 68 to the other input of the adder/incrementer. This time, it adds those two inputs,
When the ΦC clock is activated, the result of the addition is
drives to the ROM address bus, where the result is
The program counter of ROM address register array 48 may be written to.

Fixed Memory (ROM) ROM 22 is the primary location for program storage. The program storage may be read/write memory or some combination of read-only memory and read/write memory.
ROM by Horold W. Dozier September 1976
It is preferably formed by ion-implanted N-channel silicon gate technology in a serial read-only memory configuration such as that described in U.S. Pat.

Programs and data constants for the microcomputer are stored in program ROM 22. When a ROM access is required, the appropriate address register (PO or DC) is gated to the ROM address bus and the ROM output is gated to the main data bus 28. The first byte in ROM is location 0.

Upon activation of the RESET input signal or when power is first applied to computer 10, main control logic 26 gates information from data bus 28 to the appropriate address register of ROM address register array 48. At this point in the reset cycle, no drive element for the data bus is selected. Therefore, the information on the data bus is byte 0. That information is gated into the appropriate address register, specifically the program counter, so that when execution begins, the program counter contains location 00. From there, instruction execution continues unless a program branch or jump is encountered, or an interrupt occurs that causes the sequence of instructions located at the vector address to be executed and execution of that sequence of instructions to be suspended. , proceed sequentially. ROM 22 receives addresses from ROM address bus 68 through address latch 64 and provides data from the addressed ROM location to its data output bus 70.

Information is transferred from ROM 22 to main data bus 28 in response to the ROM-DATA BUS signal. If the information read from the ROM at this point is an instruction, that information is transmitted on the internal data bus, and the FETCH input to the instruction register 42 is
The information is transferred to the ROM2 via the internal data bus 28.
2 to the instruction register 42. Information other than instructions, such as data, is communicated to other parts of the machine by gating instructions issued by main control logic 26.

Main Control Logic Unit Main control logic unit 26 functions as a director of information within computer 10 . computer 1
Within any subsystem of 0, there are major logic elements and major buses that perform specific functions on data and that can communicate data from one point to another. Therefore, the specific functions performed by microcomputer system 10 are the functions of what data is transferred from one location to another and at what point a specific logical function is performed on that data. . Main control logic 26 provides control outputs for all other logic blocks and provides gating signals to all major buses within the machine.

Control input to main control logic 26 consists of instructions accepted from instruction register 42 for the microprocessing subsystem of computer 10. For example, if it is desired for the microprocessor to increment the contents of accumulator 30, the instruction INC-ACC is placed in the appropriate location in program ROM 22. When an instruction is retrieved from the program ROM, it is placed in an instruction register where it is transmitted to the main control logic and decoded. Main control logic 26 decodes that the instruction is an increment accumulator instruction and therefore issues appropriate control outputs to cause all logic blocks in the system to respond so that the contents of accumulator 30 are incremented. and activate and deactivate the gate.

The control output necessary to produce this result is the signal ACC which first gates the flow of data from the accumulator 30 through the selector shifter 50.
- Contains those that activate ALU. The shift signal of selector 50 is not activated so that the data passes through the shifter unchanged. The main control logic deactivates the complement signal COMP so that the information passes through the complement arithmetic unit unchanged. All of the gating signals that can gate the various logic elements onto the S-Bus are deactivated so that the contents of the S-Bus are zero. Also, the ALU's incremental signal is activated. Therefore, the contents of the A-bus transmitted to ALU 24 are incremented and the incremented result appears on result bus 54. The load accumulator signal LD ACC indicates that the information from the result bus is Φ
It is activated so that it is returned to the accumulator 30 in synchronization with the C clock. I/O port,
All of the signals controlling ISAR, scratchpad and strobe are deactivated. but,
Main control logic 26 is required to activate some of the signals in the addressing logic so that the next instruction can be fetched.

While main control logic 26 is activating a signal to ensure that accumulator 30 is incremented,
This main control logic must also fetch the next instruction. In this case, the program counter register is accessed, thereby
This program counter register is made driveable to the ROM address bus. By selecting the appropriate register address line of the address register, it is possible to read the READ to the address register.
Activate the line and the contents of the program counter will be
Appears on the ROM address bus. Main control logic 26 provides an increment signal INC to adder/incrementer 66 so that the ROM address bus is incremented. The READ-WRITE signal is switched to the write state so that the information is written back to the program counter. On the next cycle, the incremented value is accessed to the ROM address bus and
Therefore, the next instruction in the program ROM is retrieved. After the instruction is placed in the instruction register 42, the main control logic activates and deactivates the control signals so that the instruction is properly executed.

Main control logic 2 by means of interrupt logic 44
When an interrupt request is given to 6, the above-described retrieval procedure is different. If the appropriate conditions are met, a new instruction is retrieved from the ROM and placed in the instruction register 42 as described above.
Instead, the main control logic activates the appropriate control outputs to cause the interrupt vector location to be passed from the interrupt logic 44 to the program counter of the address register 48. next instruction
In FETCH, the vector address is the new address to be fetched.

A further difference in this procedure occurs when the RESET signal input to the computer is activated. When this occurs, main control logic 26 halts execution of the currently executing instruction, activates the appropriate control signals, and registers the program counter as previously described.
Make it load 00. When the reset input is deactivated, main control logic 26
Fetch the instruction starting at location 00 and start executing it.
A condition similar to RESET occurs when power is first applied to the system or when power is removed or reduced for a short period of time and then returned to normal operating levels. Internal to the main control logic 26 is a power-on-clear circuit that determines whether power was initially applied or is reduced to some non-functional voltage level and then to an acceptable voltage level. Senses that it has been returned to the level. If any of these conditions occur, the main control logic performs a RESET so that the program counter is returned to location 00 from the start of program execution.

The TEST input to the main control logic informs the main control logic that it is currently in test mode. Unlike other inputs, this TEST input is a 3-level input. If this input is in a low voltage state, it is deactivated in the main control logic, which interprets the instructions and activates or deactivates the appropriate control signals to allow the processor to function normally. . If the test input to the main control logic is taken to a very high voltage, it activates the TEST output going to the strobe logic and I/O ports 4 and 5 logic. It also deactivates the ROM-Data bus signal so that the normal mode of operation is suspended and no information from the program ROM is passed to the internal data bus. In this state, data supplied to the internal data bus will be accepted from port 5 and instructions will be fetched from the peripheral device through port 5 when in test mode instead of fetching instructions from the internal ROM.

Binary Timer Referring to FIGS. 3 and 4 in addition to FIG.
6 is a logic element that allows a binary timer to be instructed to generate a certain program delay or time delay and to perform a counting function without interfering with normal instruction execution or with minimal interference with instruction execution. It is. Binary timer 36 functions as a delay timer, which is a unit that generates a certain portion of the second delay under program control, and in another mode, binary timer 36 counts external events. Functions as a counter. In yet another mode, the pulse width measurement mode, this timer counts the number of ΦF clock cycles that occur between activation and deactivation of a particular control input and is applied to that particular control input. It can be used to be able to measure the width of a pulse.

In the timer delay mode, the main functional units are prescaler logic 72 and timing logic 74. Prescaler 72 is a programmable divider of the ΦF count clock. The function of prescaler 72 is to pre-decrease the frequency of input count clock ΦF so that longer time delays can be generated in the timer circuit using a minimum number of counts in main timer 36. The timing logic unit 74 includes a time register (FIG. 4) having modulo N data storage means that is activated when a reload signal is generated by the time register load control unit. and for storing a selected positive count number for transfer by the logic circuit to the time register.
A decrement is coupled to the count output of the time register to produce an output equal to the count minus one. A decoder is also coupled to the output of the time register and is adapted to generate a first voltage level indicating that the count output of the time register has reached one. The time register load control unit is connected to the decoder and
the output signal of the decoder is responsive to a primary count pulse and a load signal, the primary count pulse occurring, the output of the decoder not being at a first voltage level, and the load signal not occurring; When the count signal is generated. However, this control unit causes the reload signal to occur when the main count pulse occurs and the output of the decoder is at the first voltage level or when the load signal is being generated.
When a count signal is generated by the time register load control unit, the output of the decrementer is transferred to the time register by the logic circuit. The logic circuit determines the first voltage level of the decoder;
An interrupt control signal is output in response to the main count pulse and the absence of the load signal. The binary timer control input contains three signals to select the prescaler divide value, a start-stop signal, and a control signal to indicate that the timer operates in pulse-width mode.
PW, 3 clock inputs, read strobe,
Write strobe, count clock, START
It consists of an auxiliary start/stop input, designated 2, and an auxiliary count clock. There is a control output called the TIME-OUT signal that indicates that the timer has counted down to a preset value.
Output from the advance timer to interrupt logic 44. Further connected to the main data bus 28 are data in and data out channels.

The data input signal is connected to port selection logic 20.
Binary timer 36 by LT signal LOAD TIMER
Data output from binary timer 36 is enabled to main data bus 28 by the RT signal, READ TIMER.

When the timer is in MODULO-N timer mode, a prescaler divider applies the appropriate code to the three prescale selection inputs (divide by 20 input, divide by 5 input, or divide by 2 input).
The selection is made by driving the The timer is
In PULSE WIDTH mode it is not enabled and the main start-stop signal is enabled so that the timer runs. 2 when enabled to operate by the START-1 signal.
Advance timer 36 decrements each time prescaler 72 divides the count clock by the preset number.
For example, if the prescaler is enabled to divide by 20, then the ΦF count clock's 20
At the end of each cycle, timer logic 74 decrements by one count. When the main timer register decrements the specified number of counts, a TIME-OUT signal is generated, the timer continues to decrement its count by the specified number again, and the next TIME-OUT signal is generated in the same way. It becomes like this. The number of counts required to generate a TIME-OUT pulse is set by loading the count number into binary timer 36 by an output command to port 7, which is the input of binary timer 36 in this embodiment. . For example, if prescaler 72 is enabled to divide by 20 and a binary timer is loaded with a binary 00, a TIME-OUT pulse will be generated every 200 cycles of the ΦF count clock.

The operation of the timer 36 in the pulse width measurement mode is such that the timer receives the pulse width mode signal PW.
Similar to MODULO-N timer mode, except that when enabled by START2, the auxiliary start/stop signal START2 must be enabled to enable the timer in pulse width mode. The auxiliary start signal is activated by a suitably buffered and synchronized signal from an external interrupt input and, in pulse width mode, is activated by a binary timer 36.
is enabled to operate only when external interrupt pin 46 is in its proper state. Therefore, the width of the pulse on external interrupt pin 46 can be measured using binary timer 36.

In another basic mode of operation, timer 36 may be configured to calculate the auxiliary count clock directly without using a prescaler. In this mode, a non-prescale value is selected. That is, the divide control input is driven to a logic low level. This is accomplished by writing the appropriate data to interrupt control port 32, which has been assigned port number six. Similarly, pulse width mode is not selected, so the pulse width input is set to a logic "0". Timer 36 is enabled to be started by main start signal START1, and when so configured, timer logic 74 decrements the main timer on every cycle of the auxiliary clock input. Therefore, the time between timeout pulses can be defined to be equal to a certain number of auxiliary clock pulses. For example, if a binary timer is loaded with the number 10, a timeout pulse will be generated at the end of every 10 cycles of the auxiliary input clock.

In this configuration, TIME-
When an OUT pulse is generated, it goes to interrupt logic processor 44. If the interrupt logic is properly enabled, the interrupt request is transmitted to the main control logic 26. Therefore, a binary timer is used to generate a certain delay, ie, a certain number of counts of the ΦF count clock, and to generate an interrupt request to the main control logic at the end of that delay. Additionally, the timer may be enabled to count a specified number of auxiliary clock inputs and generate an interrupt request to main control logic 26 after completion of that specified number of auxiliary clock cycles.

Also, binary timer 36 may be enabled to operate only when the START2 signal is activated.
The START2 signal is the derivative of the external interrupt input, and is therefore active only when the external interrupt input is in the appropriate state. This is used to measure the width of the external interrupt input pulse. In this mode, information is computed by initially reading the contents of a binary timer at the beginning of the pulse and calculating the elapsed time difference rather than issuing an interrupt request to the main control logic at the end of the pulse. At this time, interrupt logic 46 is still enabled and an interrupt request will be generated if properly configured.

Interrupt Logic Referring to FIGS. 1, 3, and 5, according to a preferred embodiment, the derivative of the external interrupt request signal is synchronized with the ΦC clock so that an interrupt request occurs during the same ΦC cycle. An interrupt request decode operation is performed to allow increasing the maximum bit rate of serial information sampled through the external interrupt input. In conventional interrupt logic configurations, a minimum of three ΦC clock cycles are required for an interrupt request to be decoded, processed, and transmitted to the main control logic, which does not transmit serial information. This effectively limits the maximum speed that can be achieved.

According to the logic configuration of interrupt logic 44, an interrupt request is provided to main control logic 26 during the next ΦC cycle in response to an external interrupt input. In some cases, the length of time when an external interrupt request is made, that is, when some peripheral requests that the microprocessor system stop executing the current instruction sequence and instead execute a new instruction sequence. It is desirable that it be as short as possible. Therefore, as soon as an external request occurs, it is desirable that the request be transmitted to the master control logic as quickly as possible, and it is desirable that the master control logic respond to the request as quickly as possible. The response time of the main control logic is fixed due to constraints imposed by existing conventional instructions on the response of the main control logic to interrupt requests. However, there are no restrictions as to how the external interrupt signal is decoded and the amount of time required to acknowledge a legitimate external interrupt.

The amount of time required to decode and transmit an external interrupt request to the main control logic is reduced by the circuit of the present invention as illustrated in FIG. The decode operation is performed when the data on the internal data bus is guaranteed to be stable.
arranged to occur during a portion of a clock cycle. This is done by first deriving the signal F ₁ which is a function of the condition being in the logic "0" state and the .PHI.C clock cycle being in the logic "1" state. However, when ΦC goes to logic “1”, the signal is
It can be changed without changing F ₂ up to a cycle. Therefore, F ₁ is the synchronous logical inversion of the signal. The second signal F ₂ is the appropriate request state,
That is, the ΦC clock must be stabilized before falling so that a logic "1" to request an interrupt or a logic "0" if no request is made is transmitted to the control logic immediately after the fall of the ΦC clock. represents the result of the interrupt decision logic that must be used.

System Operation Referring to FIGS. 1 and 3, the operation of the binary timer within the present invention will now be described.
This operation sends TIME-OUT to interrupt logic 44 upon completion of the 200ΦF clock pulse.
A description will now be given of configuring binary timer 36 to function in MODULO-N delay mode to generate pulses.

Binary timer 36 is first set to a prescale value dividing by 20, and main timer 74 is set to count 10. External interrupt logic 44 is configured to be enabled to pass an interrupt request to main control logic 26 when a timeout pulse occurs. In order to configure the binary timer to operate in this mode, appropriate control information must be loaded into interrupt control port 32. Therefore, the divide by 20 input is set and the next two most significant bits are cleared.
Timer 36 is enabled to start immediately by setting the start bit. The external interrupt pin EDGE pin is set to logic "0". The TIME interrupt is enabled by setting the following bit so that the TIMERENA signal to the interrupt logic coming from the interrupt control port is enabled. External interrupts are disabled by setting their least significant bit to a logic "0". Therefore, its least significant bit is the external enable bit and is cleared so that external interrupts are not enabled.

The second bit, bit 1, is the timer enable bit. When this is set, the interrupt request is sent to the interrupt logic
- Enabled to be transmitted to main control logic 26 in response to an OUT pulse. Bit 3, the third valid bit, is the EDGE bit which selects the active edge of the external interrupt pin. That is, it selects whether low-high transitions or high-low transitions are to be detected. In this example, this bit is set to 0. The next bit is for the binary timer.
START bit, which is set to a logic ``1'' to enable the binary timer to start. The next bit is Pulse Width (PW), which is set to logic ``0'' so that Pulse Width mode is disabled. The next bit in this register is the divide-by-2 control for the prescaler which is set to 0, and the next two most significant bits are the divide-by-5 control which is set to 0 and the divide-by-2 control for the prescaler which is set to 0. This is the prescale input for division by 20. After loading the interrupt control port with the appropriate data, represented by 8A in hexadecimal notation, the main timer is loaded with a decimal value of 10, which is OA in hexadecimal notation. In summary, the main timer is loaded with a count of 10, the prescaler is loaded with a divide by 20 value, the timer is enabled to run, and the timer interrupt is enabled to occur.

When executing an instruction set in which the timer is configured in MODULO-N delay mode to generate an interrupt to the main control logic every 200ΦF clocks, the first thing that happens is that the first instruction in the sequence In this example, machine code 20 located at address 100 must be retrieved. The program counter in address register array 48 must be selected such that the contents of the program counter 100 are made available to ROM address 68. That information is then latched into address latch 64, and then
The data is transmitted to the program ROM 22. program
After ROM22 is addressed, machine code 20
appears in the output corresponding to that address.

To place that data into instruction register 42, the ROM-DATA BUS control line must be activated. With the FETCH signal activated, the information is transferred from the data bus to the instruction register 42 in synchronization with the ΦC clock. moreover,
During this fetch, an incremental signal to adder/amplifier 66
INC indicates that the information appearing on the ROM address bus is incremented to a new incremented value at the end of the cycle.
101 is activated so that it is driven back to ROM address bus 68. The program counter is further selected by the main control logic and READ/
The WRITE line is set so that the incremented information 101 is loaded back to the program counter.
Moved from READ state to WRITE state. At this time, the operation code has been taken out to the instruction register 42, and the contents of the program counter are
It has been incremented from 100 to 101.

At the beginning of the next machine cycle as determined by the ΦC clock, the machine code 20 present in the instruction register 42 is decoded in the main control logic 26. This instruction, in this example, LOAD
IMMEDIATE and so the program
The next bit of information or information word stored in the ROM is loaded into the accumulator 30. Therefore, the instruction operation code is located
Since it is in ROM at 100, the data word at location 101 is the one that is loaded into the accumulator. In this example, the content of that data word is hexadecimal 8A.
The main control logic must transfer this word in the program ROM to the accumulator 30.

To perform this operation, main control logic 26 again uses ROM address bus 68.
Address register file 4 that enables this
Select the PC register at 8. Therefore,
The contents of the ROM address bus are incremented data 101
It is. The information stored in location 101 is stored in ROM
The data is transferred through the data output bus 70 and applied to the main data bus 28 at the transfer gate. Additionally, the main control logic activates the DATA BUS-3 transfer signal so that information 8A is transferred from the data bus to the S-bus input of ALU 24.

Additionally, main control logic 26 deactivates all control inputs to the A-bus of ALU 24 so that neither accumulator 30 nor status register 56 is selected. The data is not shifted or complemented in any way so that the A-bus inputs of ALU 24 are all zeros. The ADD signal to the ALU means that the contents of the S-bus (8A) are added to the A-bus (0) and the S-bus contents (8A) are added to the A-bus (0).
The bus is activated so that its data can pass unchanged through the ALU.

Data is latched into the accumulator 30 with the load accumulator signal LD_ACC activated and synchronized with the ΦC clock. Hence, as mentioned above, the data is incrementally added to ROM location 101
The data is transferred from the storage unit 30 to the storage unit 30. Additionally, when program counter data is latched into address latch 64, adder/incrementer 66
drives its incremented value 102 back onto the ROM address bus. With the program counter selected, the address register array 48 is
The READ/WRITE line changes to the WRITE state at the end of the cycle so that the accumulator 30 has been loaded with the information corresponding to the incremented location 102 stored in the program counter of the ROM address register array 48. do.

The final cycle of the LOAD IMMEDIATE instruction is
This is a FETCH of the next instruction to occur. This is the FETCH from main control logic 26.
Activate the signal and address register file 4
This is accomplished by selecting the program counter from 8 to cause the ROM address bus to be loaded with an incremented address location 102.
This sets address latch 64 so that the information at ROM location 102 appears at the data output of ROM 22.
Being beaten. ROM-DATA BUS signal is
Since information is activated to pass from the output of the ROM to the main data bus 28 and the FETCH signal is activated, that information is latched into the instruction register 42 in synchronization with the ΦC clock. Furthermore, the adder/
Incrementer 66 is enabled to increment so that when the 102 address is latched into address latch 64, the increment value 103 is driven onto ROM address bus 68 and into address register array 48.
The READ/WRITE line is switched from READ mode to WRITE mode so that an increment value of 103 is written to the program counter of address register array 48.

The new instruction command B6, which was the data retrieved from address 102, is latched into instruction register 42. At the beginning of the next cycle, the main control logic decodes the B6 command, which is a command to output data to port 6 (interrupt control port). In order for port selection logic 22 to activate port 6, the address of that port must be driven onto data bus 28. The address of port 6 is OUTPUT SHORT command B6
It is included in the lower 4 bits. Therefore, in order to transfer port address 6 to data bus 28, the lower four bits of the instruction register must be driven to the main data bus. In order to do this,
The IR-S signal is activated. This allows the lower four bits of the instruction register to be transferred to the S-bus input of the ALU. A-bus
Since no signals controlling the ALU are activated, the contents of the A-bus are 00.
The ALU is enabled to add, so the 06 is added to 00, which means that the 06 passes through the ALU unchanged, and the value
06 appears on result bus 54. RESULT BUS−
The DATA BUS signal is activated so that the contents of result bus 54 are transferred to the main data bus. Therefore, the value placed on the lower bit of instruction register 42
06 has been driven to the main data bus 28.

During the next cycle, the main control logic 26 enables the contents of the accumulator 30 onto the main data bus 28, and the port selection logic causes the data to be loaded into the port at the address that was on that bus during the previous cycle. command the device 20; To do this, the ACC-ALU control signal from main control logic 26 is activated. Thereby, the contents of the accumulator 30 are transferred to the selector shifter 50. No shifts are performed on the data so that it passes through the shifter unchanged. This data also passes through complement arithmetic unit 52 unchanged. This is because the complement signal COMP is not activated. Since none of the drive elements are enabled for the S-bus, the ALU
The S-Bus inputs to are all zeros and the ALU is enabled to perform the addition. Therefore, the contents of the accumulator pass unchanged through the ALU to the results bus 54. The information in the accumulator was previously set by a previously executed LOAD IMMEDIATE instruction and is 8A. Therefore, the content loaded onto the main data bus 28 is
It is 8A.

Additionally, the main control logic unit 26 has a load high (LD
HI) input to port selection logic 20. This instructs the port selection logic to load information from the main data bus into the high numbered port at address 06 that was on the data bus during the previous cycle. As a result of the value 06 on the data bus in the previous cycle and as a result of the LD HI signal being activated during the current cycle, port selection logic 20 activates the LI CP signal so that the contents of the main data bus are It is synchronized with the ΦC clock and transferred to the interrupt control port 32.

Therefore, at the end of this cycle, the instruction register still contains instruction B6. The program counter in address register array 48 is 103
The accumulator 30 is still 8A
Contains. However, interrupt control port 32 also contains data 8A, which information is transferred to the output of the interrupt control port and goes to the control input of binary timer 36 and interrupt logic 44. This information would then allow the binary timer to function with a prescale by divide by 20 in MODULO-N delay mode. This information would also start a timer and enable timer interrupts.

The count of 10 remains loaded into the main timer such that when combined with the prescale value of divide by 20, the binary timer generates the TIME-OUT signal after the occurrence of the 200ΦF clock pulse. The following instructions are taken to do this. Program counter is ROM address register array 4
8 to the ROM address bus. The address of the contents of the bus is latched into address latch 64, which is the current contents of program counter 103. Therefore, 103 is the address to the program ROM and the information at location 103 appears on the ROM data output bus 70. In this example, that information is
It is 7A. Furthermore, the adder/incrementer is enabled to increment. When the ΦE clock pulse ends, indicating that information is latched in the address latch, the adder/amplifier drives back onto the ROM address bus 68. Its increment value is
It is 104.

At this point in program execution, the READ/WRITE line in address register file 48 is switched from READ mode to WRITE mode, allowing 104 information to be written back to the selected program counter. moreover,
The ROM-DATA BUS signal is activated so that the data appearing at the output of the ROM is transferred to the main data bus, and the GET signal is activated so that the information is loaded into the instruction register 42 in synchronization with the ΦC clock. be converted into Therefore, at the end of the cycle,
The program counter includes location 104. Instruction register 42 contains command 7A.

At the beginning of the next cycle, the main control logic
Decode 7A and this is LOAD IMMEDIATE
Recognize that it corresponds to the SHOPT command. this
In the LOAD IMMEDIATE SHORT instruction, the main control logic 26 is commanded by this instruction to
The lower 4 bits of that instruction are stored in the accumulator 30.
so that it is placed at To do this, the main control logic enables the IR-S line such that the lower four bits of the instruction register, which is a hexadecimal A, are transferred to the S-bus, making the contents of the S-bus OA. become No element is selected on the A-bus of the ALU so that the A-bus is 00. The ADD instruction is
provided to the ALU by the main control logic unit 26;
00 is therefore added to A and the resulting OA appears on the results bus 54. Load accumulator signal
LD_ACC is activated so that the content OA of the result bus is loaded into the accumulator 30 in synchronization with the ΦC clock. At the end of this cycle, instruction register 42 still contains data 7A, but accumulator 30 is loaded with OA
have.

The program counter remains loaded with code 104. During the next cycle, main control logic 26 retrieves the next instruction from ROM 22. To do this, the program counter is routed from the address register file 48 to the ROM address bus 6.
8, the READ/WRITE control is placed in READ mode, and the information is synchronized with the ΦE clock.
Latched into ROM address latch. Therefore, ROM 22 is addressed at location 104. place
The data appearing at 104 is driven to the ROM's data output bus 70. Additionally, adder/incrementer 66
is enabled to perform an increment, and at the appropriate time the incremented value 105 is placed on the ROM address bus 68.
Driven back to . to address register array
The READ/WRITE signal is set to WRITE so that the incremented value 105 is written to the program counter.
mode can be switched. Therefore, at the end of this cycle, the program counter contains information 105.

The data at ROM location 104 in this example is B7
It is. This is the command for OUT PUT SHORT-PORT7. The ROM-DATA BUS signal is
Activated so that data is transferred from the ROM output bus to the main data bus. The FETCH signal is activated so that information on the data bus is transferred to the instruction register 42. Therefore, at the end of the cycle, the program counter contains code 105 and the instruction register contains instruction B7. At the beginning of the next cycle, the main control logic decodes the new instruction B7 and recognizes that this is the instruction to output data from the accumulator to port 7.

To address port 7, main control logic 26 first transfers the port address to data bus 2.
Must be placed at 8. Signal IR-S is activated and the lower four bits of the instruction register are transferred to the S-bus. The ADD signal is enabled, so the result of the ALU is data 07 from the lower four bits of instruction register 42 on the S-bus unchanged. The result bus is RESULT−
Enabled to the data bus using the DATA BUS CONTROL signal. Therefore, the content of data bus 28 is 07.

During the next cycle, main control logic 26 enables the contents of accumulator 30 to be driven onto the main data bus. Port selection logic 20 is selected to place the data into the port at the address that was on the bus during the previous cycle. To do this, the ACC-ALU signal is activated, thereby allowing the data stored in the accumulator 30 to be transferred to the shifter 50. Shifter 50 and complement unit 52 are not enabled, so data passes unchanged from the accumulator to the ALU. Since no elements are enabled to drive the S-Bus, the S-Bus inputs to the ALU are all zeros. ADD instruction
ALU and the result appears on result bus 54. The RESULT-DATA BUS signal is enabled, allowing data on the result bus to be transferred to the data bus. In addition, main control logic 26 asserts a load high input to port selection logic 20, thereby causing the data bus to go to the high numbered port, timer port 7, that appeared on the data bus during the previous cycle. The port selection logic is commanded to load the contents.

After properly decoding the fact that the data bus contained number 07 in the previous cycle, port selection logic 20 is instructed to perform a load high instruction. In response to this command, port selection logic 20 activates the load timer signal so that the data on main data bus 28 is transferred to binary timer 36.
main timer register. At the end of this cycle, instruction register 42 still contains machine language instruction B7 and location 105 is stored in the program counter of address register 48. The content of the accumulator 30 is OA, and the information OA is transferred to the main data bus and loaded into the binary timer 36. Therefore, the binary timer contains the data hex OA, which is 10 of 10
Equivalent to hexadecimal value. Previously configured to divide the ΦF clock by 20 and previously enabled to start, timer 3
6 starts the operation.

The binary timer 36 is activated before loading the data OA. However, when a load timer instruction is applied to the binary timer, the binary timer clears the residual count in prescaler 72 so that it restarts its count at the end of the cycle. First, it divides the ΦF clock by 20. When this is done, it decrements the main timer register by one. Therefore, it decrements from OA to 99. This continues until 200 ΦF clocks have elapsed. When this happens, TIME−
The OUT pulse is communicated to interrupt logic 44;
The interrupt request is then forwarded to main control logic 26.

Output instruction B7 to port 7 is completed only after the next instruction fetch has been executed. Each instruction is responsible for fetching the next instruction so that the main control logic automatically advances through the instruction sequence. Therefore, the next instruction, whatever it is, is fetched as described above, and that instruction is placed in program location 105, which is the current contents of the program counter.

As will be apparent from the foregoing, the microprogram computer of the present invention is capable of highly efficient instruction processing, while substantially reducing storage requirements.

The examples described above are preferred embodiments of the invention, and certain changes may be made to the systems described above without departing from the spirit and scope of the invention as set forth in the claims. And in some cases,
It may be possible that some of the features of the invention may be useful when used separately from other features.

[Brief explanation of the drawing]

FIG. 1 of the accompanying drawings is a block diagram of a microprogrammed computer having functional elements interconnected according to the invention, and FIG. Figure 3 is a functional diagram of the binary timer and interrupt circuit of Figure 1; Figure 4 is a detailed block diagram of the timer shown in Figure 1; Figure 5 is a diagram illustrating the timing signals used; The figure is a timing diagram illustrating execution of decoding of an interrupt request. 10...Micro computer, 12, 14, 16,
18... Input/output port, 20... Port selection logic device, 22... Program data storage fixed storage device, 24... Arithmetic logic unit (ALU), 2
6...Main control logic unit, 28...Data bus, 3
0...Accumulator, 32...Interrupt control port, 34...Binary timer, 38...Clock generator, 40...Scratchpad register, 44...
...Interrupt logic unit, 46...External interrupt pin, 5
2...Incrementer, 54...Result bus, 55...Status bus, 56...Status register, 58...Indirect scratchpad address register, 60...Scratchpad address bus, 62...Address register Output bus, 64...Address latch, 66...
...adder/incrementer, 68...address bus.

Claims (1)

Claims: 1. (a) a master control logic device for controlling the order, timing and direction of information flow; a device for exchanging data with a peripheral device via a data transfer port; (b) a data processing system having a program storage device containing a microprogram that controls the execution of instructions issued by the device; and an arithmetic unit that performs operations on data words under program control; (b) from an external data source; It includes an interrupt pin 46 for receiving a pulse signal and means for generating an auxiliary clock signal synchronized with a predetermined amplitude transition of the external pulse signal, and also includes a timeout signal from a binary timer or an input from the interrupt pin 46. (c) interrupt logic for processing interrupt requests in cooperation with the interrupt logic and including prescaler logic 72 and timing logic 74; the binary timer; the timing logic is decremented on each division to the prescaler logic, and the prescaler logic and timing logic are configured to count from the program storage device to the binary timer; Generates signals to select signal and prescaler divider values, start/stop signals, clock inputs, read strobes, write strobes, and timeout signal to indicate when the binary timer has counted down to a preselected value. the prescaler preselects the count clock when enabled by the start signal. a microprogrammed computer system comprising: decrementing a count by one count each time the preset count is divided by a preset number and generating a timeout signal for the interrupt logic.