JPS6261279B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic musical instrument capable of producing multiple sounds simultaneously, which is capable of producing a new sound by detecting the most decayed sound among the maximum number of simultaneous sounds. If a new key is pressed while all the notes with the maximum number of simultaneous polyphony are being sounded, the sound that has decayed the most among the currently sounding notes will be stopped, and a new sound will be played. It is preferable to This invention has been made in view of the above points. According to the present invention, a key code identifying a pressed key is stored in one of a plurality of channels of a key code memory, and the key code stored in each channel is stored in a time slot corresponding to each channel in a continuous cycle period. An electronic musical instrument that is added to a time division tone generator in a time division manner, which operates when all channels are producing sound and a new key is pressed, and the key code corresponding to the newly pressed key is transmitted to the An electronic musical instrument comprising a truncation device for assigning to a channel corresponding to a time slot in which the most attenuated sound in the key code memory is generated, and said assignment is performed in two consecutive cycle periods, a first half period and a second half period. The degree of attenuation of each attenuated sound generated from the tone generator in each consecutive time slot of the first half period is compared in sequence, and the degree of attenuation is advanced compared to all the preceding time slots of the first half period. first means cooperating with said first means and generating a truncate signal for each time slot in which the last truncate signal is generated in the time slot containing the most attenuated sound; delay means for generating a single truncate signal in the second half period in a time slot containing the most attenuated sound; writing means for writing a key code corresponding to the newly pressed key into a channel of the key code memory corresponding to the single time slot in which a single truncate signal is included. Also, the first
The means compares the contents of the minimum value storage means and a signal indicating the degree of attenuation of each attenuated sound with the minimum value storage means, and truncates when the degree is ahead of the contents of the minimum value storage means. a comparator that generates a signal and rewrites the stored contents of the minimum value storage means to a signal indicating that the degree is advanced; and the delay means delays the last generated truncate signal by a time equal to one cycle period. Thus, the single truncated signal is formed. The invention will now be described in detail with reference to the embodiments of the accompanying drawings. FIG. 1 is a diagram schematically showing an electronic musical instrument according to the present invention. A keyboard 1 is equipped with a large number of key switches operated by each key. The operation of these key switches is detected by a key coder 2, and an operating key switch (on switch) is detected. ) is generated. Key code KC of detected operation key switch
are sequentially sent out from the key coder 2 one by one with a constant time width T _p established by a clock φ _B as shown in FIG. 2c, for example. The key code KC output from the key coder 2 is supplied to the channel processor 3. The channel processor 3 is a circuit for assigning the sound specified by the depression of the key on the keyboard 1 to any one of the channels whose number corresponds to the maximum number of simultaneous sounds. The basic conditions for assignment are: (A) It must be assigned to a channel that has not yet been assigned a pronunciation (blank channel); (B) The same note must not be assigned to multiple channels twice. , is. The channel processor 3 performs the allocation operation in accordance with the above basic conditions, but since it includes the truncation circuit of the present invention internally, even if the above condition (A) is not satisfied, if the truncation condition described later is satisfied, , is adapted to perform the allocation operation. In the channel processor 3, the key code storage circuit 11 includes a specific number of storage circuits (storage locations) corresponding to the total number of channels, and includes a gate on the input side. It is convenient to configure it as a circular shift register, and assuming that the number of channels is 12 and the number of bits of the key code KC is 9, one storage position is 9 bits and a shift register with 12 storage positions (12 words × 9 bit) is used.
The key code stored in each memory location is sequentially shifted in accordance with the main clock pulse φ ₁ (FIG. 2a), outputted from the final stage and fed back to the input side, so that the stored contents are circulated and held. The pulse interval of the main clock pulse _φ1 is, for example, 1 μs,
This pulse interval will be referred to as channel time. Assuming that the total number of channels is 12, time slots of 1 .mu.s width successively separated by the main clock pulse _.phi.1 correspond to the first channel to the twelfth channel in sequence. As shown in Figure 2b, each time slot is sequentially connected to the first channel to the first channel.
Let's call it 12 channel hours. Each channel time occurs cyclically. One allocated operation time T _p in the channel processor 3 corresponds to the pulse interval of the clock pulse φ _B (FIG. 2c), and this pulse φ _B is applied to the first channel time every two cycles of each channel time. Occurs when. One-time allocated operation time T
_p is divided into one circulation period T _p1 in the first half and one circulation period T _p2 in the latter half of each channel time. First half period T
_p1 is indicated by pulses Y _1-12 as in FIG. 2d, and the second half period T _p2 is indicated by pulses Y _13-24 in FIG. 2e.
Directed by. In the first half period T _p1 ,
Preparatory operations for assignment are performed, such as comparison in the key code comparison circuit 12 and detection of the lowest attenuation channel in the truncate control circuit 13. In the second half period T _p2 , a storage operation is performed according to the assignment, such as storing the key code KC in the key code storage circuit 11. In this embodiment, the first channel is assigned to the pedal keyboard, and the second to twelfth channels are assigned to the manual keyboard (upper keyboard, lower keyboard). Therefore, during the first channel time, assignment operations related to the pedal keyboard are executed, and during the second to twelfth channel times, assignment operations related to the manual keyboard are executed. Therefore, pulses Y 2 to 12 are generated corresponding to the first half period for manual keyboard assignment operation, and pulses Y _{2 to Y12} are generated corresponding to the second half period for manual keyboard assignment operation.
Y _14-24 are generated (Fig. 2 f, g). Also, the pulse for the second half period for pedal keyboard assignment operation.
Y ₁₃ is generated (Figure 2h). Pulse of Figure 2 i
_Y24 is generated at the end of the allocation processing operation time _Tp , that is, at the 12th channel time of the second half period _Tp2 . The key code comparison circuit 12 compares the key code KC sent from the key coder 2 with the key code storage circuit 1.
Compare the contents of the memory key code KC ^* output from 1 and display the comparison result depending on whether it matches or does not match.
Output COM. The key code KC is generated during one assigned operation time T _p (Fig. 2 c), and the stored key code KC ^* is the content assigned to the 1st to 12th channels during this time T _p , which is circulated twice. do. Therefore, one comparison is completed in one circulation period T _p1 in the first half. This comparison shows that the conditions of said allocation
It is checked whether (B) is satisfied. Comparison result
COM is a signal 1 when there is a match, and a signal 0 when there is a mismatch. The comparison result storage circuit 14 stores the comparison results.
COM and retains its memory during the second half period T _p2 until reset by pulse _Y24 . The stored comparison result REG is inverted by an inverter 15 and applied to AND circuits 16, 17, and 18. Therefore, if no match is detected in the first half period T _p1 , the memory comparison result will be stored during the second half period T _p2 .
REG is signal 0, and signal 1 is applied to AND circuits 16-18 via inverter 15. This means that the assignment condition (B) is satisfied. The code detection circuit 19 detects which keyboard the key code KC sent from the key coder 2 belongs to in order to assign the sounds of the pedal keyboard and the sound of the manual keyboard to predetermined channels respectively. This is a circuit that does this. For example key code
KC is, in order from the most significant digit, K ₂ (MSB), K ₁ , B ₃ ,
Assuming that it is composed of 9 bits of data: B ₂ , B ₁ , N ₄ , N ₃ , N ₂ , N ₁ (LSB), the upper 2
The bits K ₂ and K ₁ represent the keyboard type, and the 3 bits below them represent the keyboard type.
Bits B ₃ , B ₂ , B ₁ represent the octave range,
The lower four bits N ₄ , N ₃ , N ₂ , and N ₁ represent pitch names within one octave. Therefore, the upper 2 bits
The keyboard type is detected according to the contents of K ₂ and K ₁ . When the input key code KC is for a pedal keyboard, the pedal keyboard detection output PK becomes signal 1, and when it is for a manual keyboard, the manual keyboard detection output MK becomes signal 1. The assignment detection circuit 20 includes the key code storage circuit 1
The contents of the memory key code KC ^* output from 1 to each channel time are monitored to detect whether or not the key code is stored. memory key code
During the channel time when KC ^* exists, the detection output A becomes signal 1, indicating that the channel has been assigned sound generation. memory key code
During the channel time when KC ^* does not exist, the detection output A is a signal 0, indicating that the channel is a blank channel. Therefore, if the detection output A is a signal 0, the above-mentioned assignment condition (A) is satisfied. In addition, the detection output A is a key-on signal A that specifies the channel that should be generating sound.
used as. The assignment detection circuit 20 can be configured, for example, by an OR circuit that produces an output of 1 when at least one bit of the output of the key code storage circuit 11 is a signal 1. When the input key code KC is for a manual keyboard, the output MK of the code detection circuit 19 becomes signal 1. This manual keyboard detection output MK is applied to AND circuits 17 and 18. AND circuit 17
outputs signal 1 when both of the assignment conditions (A) and (B) are satisfied. When condition (B) is satisfied,
In the second half period T _p2 , the output of the inverter 15 is signal 1. Furthermore, if a blank channel exists, the output A of the assignment detection circuit 20 becomes a signal 0 during that channel time, and a signal 1 is applied to the AND circuit 17 via the inverter 21 during that channel time. Since the manual keyboard assignment is done in the second half of the manual period (Fig. 2g), the second half of the manual pulse
_Y14-24 are added to AND circuit 17. In this way, when a new key is pressed on the manual keyboard and it is confirmed that the key code KC does not match the stored key code KC ^* (REG = 0),
At the time of pulse Y _{14 to 24} in the second half period T _p2 ,
At the channel time of the earliest blank channel (A=0) (in the order of the 2nd to 12th channels), the condition of the AND circuit 17 is satisfied and signal 1 is output. This output signal 1 generates a set signal S (=1) and a reset signal C (=1) via OR circuits 22 and 23. The set signal S instructs that the input key code KC should be assigned to the channel corresponding to the channel time when the signal S is generated. When a new assignment is instructed by the generation of the set signal S, the stored contents of the channel in the key code storage circuit 11 are changed to the input key code KC.
be rewritten as . That is, at the input gate of the memory circuit 11, data (KC ^* ) fed back from the final stage output is suppressed by the reset signal C,
The input key code KC is read into the first storage position of the key code storage circuit (shift register) 11 by the set signal S. Note that when the set signal S is generated, the storage in the comparison result storage circuit 14 is set to "1", and the output of the inverter 15 becomes "0". As a result, the AND circuit 16~
18 is inhibited so that it generates the set signal S only during one channel time. If the input key code KC is from a pedal keyboard, the pedal keyboard detection output of the code detection circuit 19
PK becomes signal 1. This output PK is AND circuit 1
Added to 6. The AND circuit 16 receives a pulse _Y13 for specifying the pedal keyboard channel during the second half period _Tp.
The output of the AND circuit 16 becomes signal 1 during the first channel time _{of the second half period T p2 ,} and the set signal S and reset signal C are generated. The AND circuit 16 has a signal A
is not added, and the above-mentioned assignment condition (B) is only confirmed by the output of the inverter 15. This is because in this embodiment, only one tone is assigned to the pedal keyboard, and the first channel is assigned as a dedicated channel for the pedal keyboard. Therefore, the memory key code KC ^* of the pedal keyboard already assigned to the first channel and the new input key code of the pedal keyboard
If KC does not match (REG = 0), the assignment of memory key code KC ^* is forcibly canceled (signal C
) and enter a new key code.
KC is assigned to the first channel. This assignment operation for the pedal keyboard is executed regardless of whether the key associated with the stored key code KC ^* of the pedal keyboard is being pressed or is being released and being attenuated. Therefore, there is no need to consider "blank channels" as in condition (A). Furthermore, instead of the key code KC, the key coder 2 almost regularly supplies a start code that commands the key-off detection operation.
The code detection circuit 19 detects the addition of the start code and generates a key-off test signal x during the second half period T _p2 . During one assignment operation time T _p during which the start code is generated, the channel processor 3 does not make any new assignments, and only detects whether or not the key associated with the already assigned key code ^* has been released (keyed off). Ru. The key-on 1 time memory circuit 24 has a memory location corresponding to each channel, and preferably uses a 12-bit circular shift register 24a, for example. When the set signal S is generated to allocate the key code KC to a certain channel, the signal 1 is stored in the shift register 24a via the OR circuit 24b in synchronization with the channel time. This memory is stored in the inverter 24 by the key-off test signal x.
c. It is forcibly reset via the AND circuit 24d, but when the same key code KC is input again after that, the coincidence detection signal (COM=
1) causes the channel to store signal 1 again. Since the key-off test signal x is generated during the latter half period T _p2 (12 channel time) in which the memories of all channels in the key-on 1 memory circuit 24 go through one cycle, the contents of memories of all channels are reset. If the key continues to be pressed, key coder 2
detects this and generates the same key code KC again, so remember the key code of one of the channels.
KC ^* and input key code KC match, key on 1
Signal 1 is stored in the corresponding channel of the time storage circuit 24. On the other hand, if the key has been released, the key code KC of that key is not supplied, so the coincidence detection signal of the key code comparison circuit 12 is not generated (COM = 0), and the memory of the channel is an off check signal. It maintains the state "0" reset by x. Therefore, the next time the key-off test signal x is generated, the memory of the key-released channel is signal 0, so this is inverted by the inverter 25 and applied to the key-off detection storage circuit 26. The key-off detection storage circuit 26 includes a storage circuit such as an AND circuit 26a for key-off detection and a circular shift register 26b having a storage location corresponding to each channel. The key-off detection memory circuit 26 includes the output of the inverter 25, the key-off test signal x, and the key-on signal A.
When the AND condition is satisfied in the AND circuit 26a, it is determined that the key is off, and the signal 1 is stored in the shift register 26b. That is, when the key-off test signal x (start code) is generated, the key-on is not stored in the key-on 1 time memory circuit 24, and the key code KC ^* is not stored in the key-on 1 time memory circuit 24.
Detects that a new key has been released (key switch operation has ended) on the condition that the key has been assigned. The key-off detection memory circuit 26 outputs the stored contents of each channel in a time-division manner for each channel time in synchronization with the clock _φ1 , and when the signal is 1, this output is a key-off signal indicating key-off. It is used as D. Key off signal D
If this occurs, it means that the sound in the channel has entered a state of attenuation after the key is released. When the sound generation is completed, the decay end signal DF is applied from the envelope generating circuit 27 to the OR circuit 23, as will be described later, to generate the reset signal C, and reset the key-off memory of the channel in the memory circuit 26. As described above, the basic assignment operation is executed in the channel processor 3, and the key code KC ^* of the assigned key switch (key) and the key-on signal A indicating that it has been assigned or the assigned key is released. A key-off signal D indicating that the key-off signal has been input is time-division multiplexed in synchronization with the time of each channel, and is outputted, respectively, and supplied to the subsequent sound generation circuit 28, envelope generation circuit 27, and the like. Truncate Control Operation In addition to the above-mentioned basic allocation operation, the channel processor 3 also executes an allocation operation based on the truncate control operation according to the present invention. In this example, the truncate control operation is performed on a manual keyboard. When all 11 notes are being sounded on the 2nd to 12th channels assigned to the manual keyboard, when a new 12th key is pressed on the manual keyboard, the note with the most attenuation among the 11 notes currently being sounded will be played. The truncate control operation is a control operation that detects a sound, stops the sound, and assigns the 12th sound to that channel so that it can be played. In order for the above control operation to occur, (1) all 11 tones must be being sounded, (2) any of the tones must be attenuating, and (3) the 12th key must be pressed. Three conditions are required. FIG. 3 shows an example of the truncate control circuit 13, in which an amplitude comparison circuit 33 and a minimum amplitude storage circuit 34 detect the channel to which the sound whose attenuation is most advanced is assigned. The truncate channel designation circuit 81 confirms the above conditions (1) and (2), and generates the truncate channel designation signal MTCH at the time of the channel to be truncated.
The above condition (3) is confirmed by the AND circuit 18 (FIG. 1). In this embodiment, the sound whose attenuation is the most advanced is detected based on the amplitude value of the envelope waveform. That is, the digital processing type electronic musical instrument is equipped with an envelope generation circuit 27 as shown in FIG.
The envelope waveforms are sequentially read out from the envelope memory 31. A typical example of an envelope waveform stored in the envelope memory 31 is shown in FIG. The envelope waveform shown in FIG. 4 is divided into a plurality of sample points along the time axis, and the amplitude value of each sample point is sequentially stored in each address of the envelope memory 31. It is preferable to use a read-only memory or the like that stores the amplitude value of each sample point of the envelope waveform in a binary digital quantity as the memory 31 for the use of the envelope amplitude value in the truncate control circuit 13. If a memory storing the amplitude is used, an analog-to-digital converter 32 may be provided as shown by the imaginary line to convert the amplitude into a digital amplitude value and then supply it to the truncate control circuit 13. The read control circuit 30 operates according to the main clock _φ1 .
Twelve channels are time-divisionally shared, and when a key-on signal A is applied, the channel operates during the corresponding channel time and sequentially reads amplitude values from the memory 31 in accordance with the attack clock. By this reading, a partial envelope waveform as shown in the attack portion of FIG. 4 is obtained. When the envelope amplitude reaches the sustain level, the attack clock is stopped and the same amplitude value is continuously read from memory 31, resulting in a partial envelope waveform as shown in the sustain section of FIG. When the key-off signal D is applied, amplitude values are sequentially read out from the memory 31 in accordance with the decay clock to obtain a partial envelope waveform as shown in the decay portion of FIG. In this way, the generation of the envelope waveform is completed. In the decay portion, the amplitude value gradually attenuates as time passes. Such an envelope waveform is read out from the time-sharing memory 31 for each channel. Therefore, it can be said that in one circulation period (12 channel times) of each channel time, the sound of the channel whose envelope amplitude value read out from the memory 31 is the smallest is attenuated the most. As the read control circuit 30, a counter capable of time-division shared operation for 12 channels, a suitable shift register, or the like can be used. The envelope amplitude values read out in a time-division manner from the memory 31 at each channel time are supplied to the truncate control circuit 13 for use in the truncate control operation.
is added to control the amplitude envelope of the musical note. The key code KC ^* assigned by the channel processor 3 is applied to the sound generation circuit 28,
A musical tone signal having the pitch specified by the code and having any desired tone color is generated from the same circuit 28 in a time-division manner for each channel time. This musical tone signal is applied to a weighting circuit 29, and a musical tone signal whose amplitude envelope is controlled is obtained from the circuit 29. Now, the envelope amplitude value G generated by the envelope generation circuit 27 is transmitted to the truncate control circuit 1.
3 (FIG. 3).
The amplitude comparison circuit 33 compares the envelope amplitude values G of each channel and detects the channel with the smallest amplitude value. The envelope amplitude value G is a binary digital quantity, as described above. Although data for all bits of this amplitude value G may be input to the comparator circuit 33 for comparison, it is usually not necessary to compare so precisely, and multiple bits (for example, n bits) constituting the amplitude value data may be compared. It is sufficient to compare several bits of the upper digits. In the amplitude comparison circuit 33 shown in FIG.
Gn, G _o-1 , G _o-2 , (Gn is the most significant digit MSB, G _o-1 is
The one lower digit of Gn is input, and the one lower digit of G _o-1 for G _o-2 is input. Therefore, the envelope waveform amplitudes are compared in this case with respect to the three most significant bits. The minimum amplitude storage circuit 34 is a circuit that stores the detected minimum amplitude value, and the comparison circuit 33 compares the stored minimum amplitude value MG with the input amplitude value G.
This comparison is performed sequentially for each channel. If the input amplitude value G is smaller than the stored amplitude value MG during a certain channel time (G<MG), the storage circuit 34 is immediately rewritten and the input amplitude value G is newly stored. As the channel time elapses, the stored minimum amplitude value MG is rewritten as appropriate by sequentially performing comparisons for each channel.
Therefore, when the comparison of all channels is completed, that is, the amplitude value G of the 12th channel and the stored amplitude value
Only when the comparison with the MG is completed can the channel with the correct minimum amplitude value be known. Therefore, one circulation period in the first half of the 1st to 12th channel times is used only for the above-described sequential comparison of each channel. First, to explain the details of the comparison operation, the input amplitude value G and the stored amplitude value MG are compared for each bit. The memory circuit 34 has delay flip-flops 35, 36, and 37 corresponding to bits G _o-2 , G _o-1 , and Gn, respectively, and the stored contents are AND circuits 38, 39, and 40, and an OR circuit 4.
1, 42, and 43, respectively. The comparison circuit 33 compares the input amplitude value G and the stored amplitude value MG, and produces an output of CM=1 when G<MG,
When G≧MG, an output of CM=0 is produced. Three AND circuits 44-46, 47-4 for each bit
9, 50 to 52 and OR circuits 53, 54, and 55 are provided, and a logic is set up to detect G<MG. Logic (1)... Compare the magnitude of each bit of the amplitude values G and MG. That is, the logical formula is as follows.・MGn → AND circuit 51 _o-1・MG _o-1 →AND circuit 48 _o-2・MG _o-2 →AND circuit 45 Here, _Go ~ _o-2 connects Gn ~ Go _o-2 to inverter 5
These are signals inverted at 6, 57, and 58, respectively. Therefore, Gn, G _o-1 and G _o-2 are respectively 0, MGn, MG _o-1 ,
When MG _o-2 is 1, each AND circuit 51, 4
The outputs of 8 and 45 become signal 1. This represents Gn<MGn G _o-1 <MG _o-1 G _o-2 <MG _o-2 , respectively. Therefore, if the most significant digit is Gn (0) < MGn (1), then naturally G < MG, so the output signal 1 of the AND circuit 51 is compared via the OR circuit 55, the AND circuit 59, and the OR circuit 60. Output CM of circuit 33 (=1)
becomes. If the comparison result output CM is “1”, G<
It represents MG. When the most significant digit is Gn(1)>MGn(0), G>
However, when Gn (1 or 0) = MGn (1 or 0), it is necessary to check the comparison result of the lower digits. Logic (2)... When Gn=MGn, if the lower digit is G _o-1 < MG _o-1 , then G < MG, so the following logic is constructed. When Gn=MGn=1, CM ₂・MGn→AND circuit 50 When Gn=MGn=0, CM ₂・→AND circuit 52 Here, CM ₂ is the comparison result of the lower digits, and OR circuit 5
This is the output of 4. That is, when G _o-1 < MG _o-1, CM ₂ =1. However, the lower digit is G _o-1 =
For MG _o-1 , it is necessary to further check the lower digits. This is the same as above, when G _o-1 = MG _o-1 = 1, CM ₁・MG _o-1 → AND circuit 47 When G _o-1 = MG _o-1 = 0, CM ₁・_o-1 →AND circuit 49 Here, CM ₁ is the comparison result of the lower digits and is the output of the OR circuit 53. In other words, G _o-2 < MG _o-2
When CM ₁ =1. When G _o-2 = MG _o-2 , there are no more lower digits to be compared, so input the signal 0 to the AND circuits 44 and 46 at all times.
CM ₁ =0. When the conditions of the logics (1) and (2) set as described above are satisfied, a signal 1 is outputted from the OR circuit 55 (CM ₃ =1) and inputted to the AND circuits 59 and 61. The fact that this signal CM ₃ is "1" indicates that the input amplitude value G is smaller than the stored amplitude value MG. One comparison operation is performed every one operation time T _p . Therefore, the pulse _Y24 is applied to the delay flip-flop 63 via the OR circuit 62, and is delayed by one bit time, so that the signal 1 is transferred from the flip-flop 63 to the AND circuit 6 at the first channel time.
Added to 1,64. Since the signal 1 is always applied to the other input side of the AND circuit 64, the signal 1 is outputted from the AND circuit 64 and applied to the AND circuit 65 via the OR circuit 60. However, the same AND circuit 65 has a manual pulse Y _2-12 during the first half period.
is added, so the circuit 65 is inhibited during the first channel time. This is because the truncate operation is performed only on the manual keyboard. Since the output of the AND circuit 65 is a signal 0, the output of the inverter 66 becomes a signal 1, and the signal 1 of the flip-flop 63 is held via the AND circuit 67. Next, at the second channel time, the signal CM is still "1" and the pulses Y _{2 to 12} are also the signal 1, but depending on the content of the key-off signal D, which is another input of the AND circuit 65, the signal CM is still "1". An output is produced from circuit 65. That is, the key-off signal D is "1" if the sound of the channel is attenuating, and is "0" otherwise. Therefore, the AND circuit 65 confirms the truncate condition (2). If the sound assigned to the second channel is attenuating, the minimum value detection signal Z is output from the AND circuit 65.
(=1) is output. This signal Z is applied to the AND circuits 68, 69, 70 of the minimum amplitude storage circuit 34, and each bit signal G _o-2 , G _o-1 ,
Gn is selected and stored in flip-flops 35-37. AND circuits 38-40 are inhibited, the previous stored value MG is canceled, and at the same time the storage in flip-flop 63 becomes "0". In this way, in one cycle period of each channel time (except for the first channel), the key-off signal D
Regardless of the comparison result, the minimum value detection signal Z is forcibly generated at the channel time when this occurs, and the envelope waveform amplitude value of the channel is stored in the storage circuit 34 as the minimum amplitude value. Thereafter, since the AND circuits 61 and 64 are inhibited by the output signal 0 of the flip-flop 63, the signal CM ₃ which is the true comparison result is sent to the AND circuit 65 as the comparison result output CM via the AND circuit 59 and the OR circuit 60. can be added to. While pulses Y ₂ to _{Y 12} are being generated, all channels for the manual keyboard are sequentially compared, and each time an input amplitude value G smaller than the stored amplitude value MG is detected, the signal CM is set to “1”. and if this is attenuating, a detection signal Z is generated. Therefore, although signal Z may be generated many times, the envelope waveform amplitude value of the channel in which signal Z is generated most recently is the true minimum amplitude value. A 12-bit shift register 71 is provided to detect this true minimum amplitude value, that is, the channel where the attenuation is the most advanced. The detection signal Z is input to the shift register 71, sequentially shifted by the clock _φ1 , delayed by 12 bit times (12 channel times), and then sent to the shift register 71.
is output from the final stage. Last stage of register 71
The output of Z ₁₂ is applied to the AND circuit 72, and the outputs of the first stage Z ₁ to the 11th stage Z ₁₁ are all applied to the OR circuit 7.
3 and is input to the AND circuit 72 via an inverter 74. By delaying the signal by 12 bits in the register 71, the input channel of the register 71 and the channel of the final stage output match. Holding signal 1 in the register 71 means that the detection signal Z=1, and the signals of the first stage Z ₁ to the 11th stage Z ₁₁ are higher than the signal of the final stage Z ₁₂ . This is the later comparison result. Therefore, the final stage Z ₁₂
When the signal is “1”, the signal 1 is sent to the subsequent stage Z ₁ to Z ₁₁ .
If it holds, it means that the signal 1 of this stage _Z12 is not the last detection signal Z, and the next stage
If signal 1 is not held in Z ₁ to _{Z 11} , this stage
Signal 1 of Z ₁₂ means that it is the last detection signal Z. The output of inverter 74 is signal 1 only if signal 1 is not held in the subsequent stages _Z1 to _Z11 .
becomes. The contents of the latter stages Z ₁ to _{Z 11} correspond to the remaining 11 channels. Therefore, the detection result of the second channel first detected in the first half period T _p1 (Z=
(regardless of whether it is 1 or 0) is output from the final stage Z ₁₂ of the register 71 during the second channel time of the second half period T _p2 , the detection results of the remaining 3rd to 12th channels are output from stages Z ₁₁ to Z ₂ are remembered respectively. Therefore, the signal of the final stage _Z12 and the output of the inverter 74 become "1" at the same time only during a single channel time in the second half period (manual second half period).
This channel time corresponds to the channel of sound that is most attenuated. Now, an AND circuit 75 is provided to confirm the condition (1) for the truncate operation. One input of the AND circuit 75 receives the key-on signal A.
is inverted and added by an inverter 76,
The other input is the manual pulse for the first half period.
Y _{2 to 12} are added. When the key-on signal A is "1", it indicates that the channel has been allocated (currently sounding), and when it is "0", it indicates a blank channel. Therefore, when all 11 tones are being generated in the manual channel, the signal A is "1" while the pulses Y2 _{to Y12} are being generated, and the output of the AND circuit 75 is the signal 0. However, if there is a channel in which even one note is not being produced, the inverted key-on signal becomes "1", and the AND circuit 75 outputs a signal 1. When the signal 1 is output from the AND circuit 75, the signal 1 is stored in the delay flip-flop 77 and self-held via the AND circuit 78 and the OR circuit 79. This self-holding is maintained until AND circuit 78 is inhibited by pulse _Y24 .
Therefore, if the condition (1) is satisfied, the flip-flop 77 holds the signal 0 during the second half period T _p2 , and if it is not satisfied (if there is a blank channel), the flip-flop 77 holds the signal 1 during the second half period T _p2 . hold. The output of flip-flop 77 is connected to inverter 80.
is added to the AND circuit 72 via
If the condition (1) is satisfied, signal 1 is output from the AND circuit 72 at the single channel time when attenuation is most advanced (in the second half period T _p2 ).
This is the truncate channel designation signal MTCH
The signal is supplied to the AND circuit 18 (FIG. 1) as a signal.
However, if the condition (1) is not satisfied, the AND circuit 72 is inhibited, so even if the channel with the most advanced attenuation is detected, the truncate channel designation signal MTCH will not be generated. The truncate channel designation signal MTCH is
It is added to the AND circuit 18 in FIG. This AND circuit 18 receives a signal obtained by inverting the comparison result storage signal REG of the comparison result storage circuit 14 and a manual keyboard signal from the chord detection circuit 19.
MK and second half manual pulses Y _14-24 are added respectively. When a new 12th key is pressed on the manual keyboard while all 11 tones are being produced, a match detection signal is generated by inputting the key code KC for that key.
Since COM becomes “0”, the comparison result storage signal REG
The inverted signal of is "1". This satisfies the condition (3) for the truncate operation. When it is confirmed that both the truncate conditions (1) to (3) are satisfied, the AND circuit 18 is activated at the channel time when the truncate channel designation signal MTCH is generated in the second half manual use period (Fig. 2g). Outputs signal 1. In response, a set signal S and a reset signal C are generated, and the key code KC ^* stored in the corresponding channel is generated.
, and a new input key code KC is stored in the corresponding channel of the key code storage circuit 11.
Further, the signal 1 (key-on) is stored in the corresponding channel of the key-on 1 time storage circuit 24, and the storage of key-off in the corresponding channel of the key-off detection storage circuit 26 is canceled. In this way, the sound whose decay is the most progressed is stopped, and a new sound is assigned to the same channel in its place. Note that the pedal keyboard is designed to produce only one note, so when a new key is pressed on the pedal keyboard, the sound of the previously assigned pedal keyboard note is immediately canceled and a new key is assigned. No truncate control action is performed. However, if the assignment operation is to be performed without distinguishing between the pedal keyboard and the manual keyboard, it goes without saying that the above-mentioned truncate control operation will be executed for all 12 channels. Note that when the reading of the decay envelope from the envelope memory 31 of the envelope generation circuit 27 (FIG. 1) is completed, the decay end signal DF is output.
is generated from the read control circuit 30 and applied to the OR circuit 23 of the channel processor 3 to generate the reset signal C. At this time, the sound generation in the channel ends and the allocation is canceled. The envelope generating circuit 27 is disclosed in Japanese Patent Application No. 47-125516 (Japanese Unexamined Patent Publication No. 49-1989), which is already publicly known.
No. 84218)・A device such as that disclosed in the title of the invention “Envelope waveform generator” can be used. The electronic musical instrument of the present invention is constructed using the truncate control circuit 13 and related logic circuits, etc., and the channel processor 3 to which this truncate circuit is applied has the configuration shown schematically in FIG. However, it is also possible to use an assignment circuit of the type disclosed in the specification of Japanese Patent Application No. 47-125514 (Japanese Unexamined Patent Publication No. 49-84216) entitled "Key Assigner". Also, key coder 2
In addition to the methods described in the above embodiments, the method disclosed in the specification of Japanese Patent Application No. 47-125513 (Japanese Unexamined Patent Publication No. 49-84215) with the title of the invention "Key Data Signal Generator" may be used. equipment or patent application 1977-
It is also possible to use a device of the type disclosed in the specification of No. 92173 entitled "Key code generator". However, when the truncate control circuit 13 is configured as shown in FIG. 3, two circulation periods of the total channel time are required to generate the truncate channel designation signal. In this case, it is advisable to take this point into account and generate the key code KC with sufficient time. As described above, the present invention has the advantage that the truncate control operation in assigning sound tones for an electronic musical instrument can be performed reliably with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing an embodiment of the electronic musical instrument of the present invention, FIG. 2 is a timing chart showing various control clock pulses, and FIG. 3 is a detailed block diagram of the truncate control circuit in FIG. 1. FIG. 4 is a graph showing a typical envelope waveform. 3...Channel processor, 13...Truncate control circuit, 33...Amplitude comparison circuit, 34...
...Minimum amplitude memory circuit, 81...Truncate channel designation circuit, 24...Key-on 1 time memory circuit, 26...Key-off detection memory circuit.

Claims (1)

[Claims] 1. A key code for identifying a pressed key is stored in one of a plurality of channels of a key code memory, and the key code stored in each channel is stored at a time corresponding to each channel in a continuous cycle period. An electronic musical instrument that is added to a time-division tone generator in a time-division manner, which operates when all channels are generating sound and a new key is pressed, and the key code corresponding to the newly pressed key. a truncation device that assigns the key code memory to a channel corresponding to a time slot in which the most attenuated sound is generated, and the assignment is performed in two consecutive cycle periods, a first half period and a second half period. In the electronic musical instrument, the degree of attenuation of each attenuated tone generated from the tone generator in each successive time slot of the first half period is compared in sequence, and the degree of attenuation is greater than that of all preceding time slots of the first half period. first means cooperating with said first means and generating a truncate signal for each advancing time slot, the last truncate signal being generated in the time slot containing the most attenuated sound; delay means for receiving a signal and generating a single truncated signal in the second half period in a time slot containing the most attenuated sound; and a delay means cooperating with the delay means and receiving the single truncated signal. , writing means for writing a key code corresponding to the newly pressed key into a channel of the key code memory corresponding to the single time slot in which the single truncate signal is included. 2. The first means compares the contents of the minimum value storage means with a signal indicating the degree of attenuation of each attenuated sound, and determines whether the degree is more advanced than the contents of the minimum value storage means. a comparator that generates a truncate signal and rewrites the stored contents of the minimum value storage means to a signal indicating that the degree is advanced; 2. The electronic musical instrument of claim 1, wherein said single truncated signal is formed by delaying.