JPS6259936B2 - - Google Patents

Info

Publication number
JPS6259936B2
JPS6259936B2 JP56011885A JP1188581A JPS6259936B2 JP S6259936 B2 JPS6259936 B2 JP S6259936B2 JP 56011885 A JP56011885 A JP 56011885A JP 1188581 A JP1188581 A JP 1188581A JP S6259936 B2 JPS6259936 B2 JP S6259936B2
Authority
JP
Japan
Prior art keywords
circuit
transistor
amplifier circuit
collector
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56011885A
Other languages
Japanese (ja)
Other versions
JPS57125532A (en
Inventor
Akio Iwase
Akio Hashima
Hitoshi Sugano
Joji Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56011885A priority Critical patent/JPS57125532A/en
Publication of JPS57125532A publication Critical patent/JPS57125532A/en
Publication of JPS6259936B2 publication Critical patent/JPS6259936B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1408—Balanced arrangements with diodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1433—Balanced arrangements with transistors using bipolar transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0043—Bias and operating point
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/009—Reduction of local oscillator or RF leakage

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Superheterodyne Receivers (AREA)

Description

【発明の詳細な説明】 本発明はテレビジヨンチユーナ回路に関し、
UHF時に於ける入出力特性の大巾な改善を実現
し、Ｓ／Ｎ特性の改善、あるいは、強電界地域で
の、受像機の電源投入時に於けるAGC回路の誤
動作を防止できるテレビジヨンチユーナ回路を提
供するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a television tuner circuit;
A television tuner that can significantly improve input/output characteristics during UHF, improve S/N characteristics, and prevent AGC circuit malfunctions when turning on the receiver in areas with strong electric fields. It provides a circuit.

第１図を参照して、従来のチユーナ回路、およ
び本発明のチユーナ回路の基本的な動作について
説明する。Tr4，Tr5，Tr6，Tr7およびTr8，Tr9
は、交叉結合型のダブルバランスミキサーを構成
するトランジスタ、トランジスタTr10，Tr11から
構成される差動増幅回路は、局部発振周波数信号
の増幅作用を行うとともに、不平衡信号を入口端
子ロより入力し、平衡信号に変換するモード変換
の作用も行う。負荷抵抗Rc1，Rc2より取り出さ
れた信号は、抵抗ＲB7，ＲB8を介して、混合用ト
ランジスタ対のTr4，Tr7、およびTr5，Tr6のベ
ースに入力される。一方、高周波信号は、トラン
ジスタTr8，Tr9で構成される差動増幅回路の入
力端子イより入力され、それぞれのコレクタ端子
より、前記混合回路のエミツタ端子に入る。トラ
ンジスタTr4，Tr5，Tr6およびTr7で混合作用が
行なわれ、交叉型に接続した、コレクタより負荷
に、中間周波信号のみ、導かれる。平衡信号とし
て、IFトランスIF・TRの一次コイルに接続さ
れ、IFトランスIF・TRで平衡→不平衡の変換を
行ない、IF出力端子ニより、出力する。 The basic operations of the conventional tuner circuit and the tuner circuit of the present invention will be explained with reference to FIG. Tr 4 , Tr 5 , Tr 6 , Tr 7 and Tr 8 , Tr 9
The differential amplifier circuit consisting of the transistors Tr 10 and Tr 11 that constitute a cross-coupled double-balanced mixer amplifies the local oscillation frequency signal, and also inputs the unbalanced signal from the input terminal RO. However, it also performs mode conversion to convert into a balanced signal. The signals taken out from the load resistors Rc 1 and Rc 2 are input to the bases of the mixing transistor pairs Tr 4 and Tr 7 and Tr 5 and Tr 6 via the resistors R B7 and R B8 . On the other hand, the high frequency signal is inputted from the input terminal A of the differential amplifier circuit composed of transistors Tr 8 and Tr 9 , and enters the emitter terminal of the mixing circuit from the respective collector terminals. A mixing effect is performed by the transistors Tr 4 , Tr 5 , Tr 6 and Tr 7 and only the intermediate frequency signal is guided from the cross-connected collectors to the load. As a balanced signal, it is connected to the primary coil of the IF transformer IF/TR, converts from balanced to unbalanced in the IF transformer IF/TR, and outputs it from the IF output terminal.

次にUHF受信時について説明する。UHF受信
時には、電源回路ブロツクｃを動作させ、トラン
ジスタTr14，Tr15で構成される差動増幅回路、お
よびトランジスタTr12，Tr13で構成されるベース
接地型トランジスタ対で、UHFの中間周波信号
（UIF信号）の増幅回路として作用する。UIFの
入力端子ハより、入つた信号は、トランジスタ
Tr12，Tr13のコレクタより、平衡信号として、前
記IFトランスIF・TRの一次コイルに接続され、
VHF受信時と同様、ニより出力するものであ
る。 Next, UHF reception will be explained. During UHF reception, the power supply circuit block c is operated, and the UHF intermediate frequency signal is transmitted through the differential amplifier circuit consisting of transistors Tr 14 and Tr 15 and the common base type transistor pair consisting of transistors Tr 12 and Tr 13 . (UIF signal) amplification circuit. The signal input from the input terminal C of the UIF is transferred to the transistor
The collectors of Tr 12 and Tr 13 are connected as balanced signals to the primary coil of the IF transformer IF/TR,
Similar to when receiving VHF, it is output from D.

第１図に示す従来の回路に於いて、UHF受信
時には、混合回路のTr4，Tr5，Tr6，Tr7の各ト
ランジスタのベース端子には、抵抗、Rc1，ＲB
７、およびRc2，ＲB8を介して、BM電圧が印加さ
れた状態になつている。従つてUIFの大入力信号
が、平衡信号としてトランジスタTr12，Tr13のコ
レクタに出力される場合に、ミキサートランジス
タのTr4，Tr5，Tr6，Tr7のコレクタ・ベース間
のPN接合の順方向特性に従つて、コレクタより
ベースへ信号のリークが発生し、入出力特性が第
３図に示す様に入力電界が過大になれば、直線性
を示さなくなる。映像信号としては、同期信号の
飽和現象として現われ、AGC動作の誤動作の原
因にもなるものであつた。 In the conventional circuit shown in Fig . 1 , at the time of UHF reception, resistors , Rc 1 and R
7 , and the BM voltage is applied through Rc 2 and R B8 . Therefore, when a large input signal of the UIF is output as a balanced signal to the collectors of transistors Tr 12 and Tr 13 , the PN junction between the collectors and bases of mixer transistors Tr 4 , Tr 5 , Tr 6 , and Tr 7 is According to the forward characteristics, signal leakage occurs from the collector to the base, and the input/output characteristics no longer exhibit linearity if the input electric field becomes excessive, as shown in FIG. As a video signal, this appeared as a saturation phenomenon in the synchronization signal, and was a cause of malfunction in AGC operation.

本発明は、上記従来の欠点を除去するものであ
り、チユーナの入出力特性を大巾に改善し、従来
回路に於いて発生した問題を解決するものであ
る。 The present invention eliminates the above-mentioned drawbacks of the conventional circuit, greatly improves the input/output characteristics of the tuner, and solves the problems encountered in the conventional circuit.

第２図を参照して本発明の一実施例について詳
細に説明する。本実施例と従来例との相違点は、
局部発振周波数の差動増幅回路のコレクタ負荷抵
抗Rc1，Rc2の接続点と、BM電源の間に、電源切
換回路を設けたものである。 An embodiment of the present invention will be described in detail with reference to FIG. The differences between this embodiment and the conventional example are as follows:
A power supply switching circuit is provided between the connection point of the collector load resistors Rc 1 and Rc 2 of the local oscillation frequency differential amplifier circuit and the BM power supply.

第２図において、VHF受信時に於いては、Bv
より電源ブロツクＡを介して得られる電源をトラ
ンジスタTr1のベースに印加する。トランジスタ
Tr1は、動作し、抵抗R1による電圧降下のため
に、Tr1のコレクタ電圧は低下する。Tr1のコレ
クタは抵抗R3を介してトランジスタTr2のベース
に接続されている。従つてPNP型トランジスタ
Tr2のエミツタ―ベース間が導通し、トランジス
タTr2は動作し、次段のトランジスタTr3のベー
スにTr2のコレクタより電圧が印加される。Tr3
が動作し、Tr3のエミツタに電圧が発生し、
Tr10，Tr11で構成された局部発振周波数の増幅回
路は動作する。又負荷抵抗Rc1，Rc2と抵抗ＲB
７，ＲB8の接続点より、抵抗ＲB7，ＲB8を介し
て、混合用トランジスタのベース電圧の印加と、
局部発振周波数の注入が行なわれる。 In Figure 2, when receiving VHF, Bv
The power obtained through the power supply block A is applied to the base of the transistor Tr1 . transistor
Tr 1 operates, and the collector voltage of Tr 1 decreases due to the voltage drop across resistor R 1 . The collector of Tr 1 is connected to the base of transistor Tr 2 via a resistor R 3 . Therefore, PNP type transistor
The emitter and base of Tr 2 become conductive, the transistor Tr 2 operates, and a voltage is applied to the base of the next stage transistor Tr 3 from the collector of Tr 2 . tr3
operates, voltage is generated at the emitter of Tr 3 ,
The local oscillation frequency amplification circuit composed of Tr 10 and Tr 11 operates. Also, load resistance Rc 1 , Rc 2 and resistance R B
Applying the base voltage of the mixing transistor from the connection point of 7 and R B8 through the resistors R B7 and R B8 ,
A local oscillator frequency injection is performed.

一方UHF受信時に於いては、電源Bvが印加さ
れず、従つてトランジスタTr1のベースには電圧
は印加されない。このためトランジスタTr1のコ
レクタはＢM電圧が保持された状態であり、抵抗
R3を介して、PNP型トランジスタTr2のベースに
はＢM電圧が印加される。従つて前記PNPトラン
ジスタTr2のベース・エミツタ間の電位差は、ゼ
ロボルトであり、トランジスタTr2は動作しな
い。又次段のトランジスタTr3のベースにも電圧
は伝達されず動作しない状態となる。このためト
ランジスタTr10，Tr11で構成された差動増幅回路
のコレクタ電圧は、抵抗R5，R6で分圧された電
圧まで低下させ、ミキサートランジスタのTr4，
Tr5，Tr6，Tr7のコレクタ―ベース間ダイオード
を、十分に逆バイアス状態とする。従つてコレク
タより、ベースへの信号のリークは発生しない。
従つてUHF受信時に於いて、UIF中間周波増幅
回路を成すTr14，Tr15およびTr12，Tr13のトラン
ジスタ対の増幅回路の入出力特性は、大巾に改善
され、出力電圧として、120dBμＶ以上の出力電
圧が得られるまで、入出力特性の直線性が維持さ
れることになつた。 On the other hand, during UHF reception, the power source Bv is not applied, so no voltage is applied to the base of the transistor Tr1 . For this reason, the collector of transistor Tr 1 is in a state where the B M voltage is held, and the resistor
The B M voltage is applied to the base of the PNP transistor Tr 2 via R 3 . Therefore, the potential difference between the base and emitter of the PNP transistor Tr 2 is zero volts, and the transistor Tr 2 does not operate. Further, the voltage is not transmitted to the base of the transistor Tr3 in the next stage, resulting in a non-operating state. Therefore, the collector voltage of the differential amplifier circuit composed of transistors Tr 10 and Tr 11 is lowered to the voltage divided by resistors R 5 and R 6 , and the collector voltage of the mixer transistor Tr 4 and
The collector-base diodes of Tr 5 , Tr 6 , and Tr 7 are sufficiently reverse biased. Therefore, no signal leaks from the collector to the base.
Therefore, during UHF reception, the input/output characteristics of the amplifier circuit of transistor pairs Tr 14 , Tr 15 and Tr 12 , Tr 13 forming the UIF intermediate frequency amplifier circuit are greatly improved, and the output voltage is 120 dBμV or more. The linearity of the input/output characteristics was maintained until an output voltage of

第３図においてａは従来例、ｂは本発明回路の
入出力特性を示している。 In FIG. 3, a shows the input/output characteristics of the conventional circuit, and b shows the input/output characteristics of the circuit of the present invention.

本発明は上記のような構成であり、本発明によ
ればUHF時における入出力特性が大幅に改善さ
れ、Ｓ／Ｎ特性が向上する利点を有するものであ
る。 The present invention has the above configuration, and has the advantage that the input/output characteristics at UHF are significantly improved and the S/N characteristics are improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のテレビジヨンチユーナ回路の電
気回路図、第２図は本発明の一実施例におけるテ
レビジヨンチユーナ回路の電気回路図、第３図は
従来例および本発明のテレビジヨンチユーナ回路
の入出力特性図である。 イ……RF信号入力端子、ロ……局部発振周波
数入力端子、ハ……UIF信号（UHF中間周波信
号）入力端子、ニ……IF出力端子、I1，I2，I3…
…電流源、C1，C2，C3……バイパスコンデンサ
ー、ＲB1〜ＲB8……ベース抵抗、Ａ，Ｂ，Ｃ……
電源回路、Tr1，Tr2，Tr3……電源切換用トラン
ジスタ、Tr4，Tr5，Tr6，Tr7，Tr8，Tr9……ダ
ブルバランス型ミキサー用トランジスタ、Tr10，
Tr11……局部発振周波数増幅用トランジスタ、
Tr12，Tr13……ベース接地型トランジスタ対、
Tr14，Tr15……UIF増幅用トランジスタ、R1……
コレクタ抵抗、R2……エミツタ抵抗、R3……ベ
ース抵抗、R4……ベース抵抗、Rc1，Rc2……コ
レクタ負荷抵抗、R5，R6……分圧抵抗。 FIG. 1 is an electric circuit diagram of a conventional television tuner circuit, FIG. 2 is an electric circuit diagram of a television tuner circuit according to an embodiment of the present invention, and FIG. 3 is an electric circuit diagram of a conventional television tuner circuit and a television tuner circuit of the present invention. FIG. 3 is an input/output characteristic diagram of the Yuna circuit. A...RF signal input terminal, B...Local oscillation frequency input terminal, C...UIF signal (UHF intermediate frequency signal) input terminal, D...IF output terminal, I 1 , I 2 , I 3 ...
... Current source, C 1 , C 2 , C 3 ... Bypass capacitor, R B1 to R B8 ... Base resistor, A, B, C...
Power supply circuit, Tr 1 , Tr 2 , Tr 3 ... Transistors for power switching, Tr 4 , Tr 5 , Tr 6 , Tr 7 , Tr 8 , Tr 9 ... Transistors for double-balanced mixer, Tr 10 ,
Tr 11 ...Transistor for local oscillation frequency amplification,
Tr 12 , Tr 13 ...Pair of common base transistors,
Tr 14 , Tr 15 ... UIF amplification transistor, R 1 ...
Collector resistance, R 2 ... Emitter resistance, R 3 ... Base resistance, R 4 ... Base resistance, Rc 1 , Rc 2 ... Collector load resistance, R 5 , R 6 ... Voltage division resistance.

Claims (1)

【特許請求の範囲】[Claims] １ 局部発振周波数の増幅回路となる差動増幅回
路を構成するトランジスタのコレクタとコレクタ
負荷抵抗の接続点より、抵抗を介して、VHFチ
ユーナの混合回路であるダブルバランス型混合回
路の直流ベースバイアス電圧の印加と局部発振周
波数成分が注入されるようにした混合回路の平衡
出力を、中間周波数トランスに印加し、且つ
UHF中間周波数増幅回路の平衡出力を、前記中
間周波数トランスとに印加してなるテレビジヨン
チユーナ回路において、UHF受信時に、前記局
部発振周波数の増幅回路である差動増幅回路の電
源電圧を低下させることを特徴とするテレビジヨ
ンチユーナ回路。1 The DC base bias voltage of the double-balanced mixing circuit, which is the mixing circuit of the VHF tuner, is applied via the resistor from the connection point of the collector of the transistor that constitutes the differential amplifier circuit, which is the local oscillation frequency amplifier circuit, and the collector load resistance. The balanced output of the mixing circuit in which the local oscillation frequency component is injected is applied to the intermediate frequency transformer, and
In a television tuner circuit in which the balanced output of a UHF intermediate frequency amplifier circuit is applied to the intermediate frequency transformer, the power supply voltage of the differential amplifier circuit, which is the local oscillation frequency amplifier circuit, is lowered during UHF reception. A television channel circuit characterized by:
JP56011885A 1981-01-28 1981-01-28 Television tuner circuit Granted JPS57125532A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56011885A JPS57125532A (en) 1981-01-28 1981-01-28 Television tuner circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56011885A JPS57125532A (en) 1981-01-28 1981-01-28 Television tuner circuit

Publications (2)

Publication Number Publication Date
JPS57125532A JPS57125532A (en) 1982-08-04
JPS6259936B2 true JPS6259936B2 (en) 1987-12-14

Family

ID=11790172

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56011885A Granted JPS57125532A (en) 1981-01-28 1981-01-28 Television tuner circuit

Country Status (1)

Country Link
JP (1) JPS57125532A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH027817A (en) * 1988-06-15 1990-01-11 Fuji Electric Co Ltd Gas-sealed container for compressed-gas-insulated switchgear

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0786375B2 (en) * 1985-09-19 1995-09-20 日本発条株式会社 Clamp parts for leaf spring device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH027817A (en) * 1988-06-15 1990-01-11 Fuji Electric Co Ltd Gas-sealed container for compressed-gas-insulated switchgear

Also Published As

Publication number Publication date
JPS57125532A (en) 1982-08-04

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