JPS6259831B2 - - Google Patents
Info
- Publication number
- JPS6259831B2 JPS6259831B2 JP54140564A JP14056479A JPS6259831B2 JP S6259831 B2 JPS6259831 B2 JP S6259831B2 JP 54140564 A JP54140564 A JP 54140564A JP 14056479 A JP14056479 A JP 14056479A JP S6259831 B2 JPS6259831 B2 JP S6259831B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- light emitting
- check
- time
- predetermined
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000004044 response Effects 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 230000003287 optical effect Effects 0.000 claims description 3
- 238000007493 shaping process Methods 0.000 description 15
- 230000004043 responsiveness Effects 0.000 description 6
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Description
【発明の詳細な説明】
本発明は光学マーク読取装置等における光電系
に不良を検出する光電系チエツク回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a photoelectric system check circuit for detecting defects in a photoelectric system in an optical mark reading device or the like.
従来、光学マーク読取装置の多くは、発光源お
よび光電変換手段からなる光電系において、読み
取りの信頼度を上げるために、発光源が全く点灯
しないような固定障害を検出する光電系チエツク
回路が付いている。しかし一般的に光電系が固定
障害を発生する前に、応答性不良を発生するのが
普通で、しかもこの応答性不良により読み取りエ
ラーを発生する可能性が多分にある。しかし、従
来の光電系チエツク回路ではこの種の応答性不良
を検出出来ないと言う欠点があつた。 Conventionally, most optical mark reading devices have been equipped with a photoelectric system check circuit that detects a fixed failure, such as when the light source does not light up, in order to increase the reliability of reading in the photoelectric system, which consists of a light emitting source and a photoelectric conversion means. ing. However, in general, before a fixed failure occurs in a photoelectric system, poor responsiveness usually occurs, and there is a high possibility that a reading error will occur due to this poor responsiveness. However, conventional photoelectric check circuits have the disadvantage of not being able to detect this type of poor response.
本発明は光電系の応答性不良、固定障害を検出
できる光電系チエツク回路を提供するものであ
る。 The present invention provides a photoelectric system check circuit that can detect poor responsiveness and fixed failures in the photoelectric system.
本発明によれば、発光源と、この発光源を点灯
状態から滅灯したのち再び点灯させる電源制御信
号を発生しこの電源制御信号により前記発光源が
滅灯してから所定の時間の後に第１のチエツクタ
イミング信号を発生し前記電源制御信号により前
記発光源が点灯してから所定の時間の後に第２の
チエツクタイミング信号を発生させるタイミング
発生手段と、前記発光源の光を受けているときに
第１の状態となり受けていないときに第２の状態
となる整形信号を出力する光電変換手段と、前記
第１のチエツクタイミング信号が発生したときに
前記整形信号が第１の状態である場合に所定の信
号を出力する第１のチエツク手段と、前記第２の
チエツクタイミング信号が発生したときに前期整
形信号が第２の状態である場合に所定の信号を出
力する第２のチエツク手段とを含むことを特徴と
する光電系チエツク回路が得られる。 According to the present invention, a light emitting source and a power control signal are generated to turn the light emitting source off from a lighting state and then back on again, and the power source control signal causes the light emitting source to turn off after a predetermined period of time. timing generation means for generating a second check timing signal after a predetermined time after the light emitting source is turned on by the power supply control signal; and when receiving light from the light emitting source. a photoelectric conversion means for outputting a shaping signal which is in a first state when the signal is received and is in a second state when the signal is not received; and when the shaping signal is in the first state when the first check timing signal is generated. a first check means for outputting a predetermined signal when the second check timing signal is generated; and a second check means for outputting a predetermined signal if the first shaping signal is in a second state when the second check timing signal is generated. A photoelectric check circuit is obtained, which is characterized in that it includes the following.
次に本発明の実施例について図面を参照して説
明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第１図はマークカード読取装置における本発明
の一実施例で、１はタイミング発生回路、２は電
源制御信号１０２によつて出力のオン・オフが可
能な電源回路、３は12入力のNAND回路、４は12
入力のOR回路、５と６は第１および第２のチエ
ツク手段であるフリツプフロツプ、１１〜１２は
発光源となる発光ダイオード、３１〜４２は受光
素子、５１〜６２は受光素子３１〜４２の信号１
１１〜１２２を増巾・整形する増巾・整形回路で
ある。第２図にマークカード２００のデータ禁止
エリア２０１である０カラムの位置を示す。 FIG. 1 shows an embodiment of the present invention in a mark card reading device, in which 1 is a timing generation circuit, 2 is a power supply circuit whose output can be turned on and off by the power supply control signal 102, and 3 is a 12-input NAND circuit. , 4 is 12
Input OR circuit, 5 and 6 are flip-flops as first and second check means, 11-12 are light emitting diodes serving as light emission sources, 31-42 are light-receiving elements, 51-62 are signals of the light-receiving elements 31-42. 1
This is a widening/shaping circuit that widens/shapes 11 to 122. FIG. 2 shows the position of the 0 column, which is the data prohibited area 201 of the mark card 200.
マーク読取装置にマークカード２００がセツト
され、フイード命令によつてマークカード２００
が送られ、リードステーシヨンまでデータ禁止エ
リア２０１である０カラムが来ると、カラス位置
検出回路（ここでは特に説明せず）によつてカラ
ム０信号１０１が、タイミング発生回路１に供給
される。タイミング発生回路１ではカラム０信号
１０１の立ち上がりを基準にして第３図に示すよ
うに、電源制御信号１０２を所定の時間だけ
“０”とし、チエツクタイミング信号１０３と１
０４を発生する。ここで電源制御信号１０２の立
ち下がりからチエツクタイミング信号１０３の立
ち上がりまでの時間t1及び電源制御信号１０２の
立ち上がりからチエツクタイミング信号１０４の
立ち上がりまでの時間t2は、正常な場合の受光素
子３１〜３２の立ち上がり、立ち下がりの応答最
大時間より少し長い時間に設定されている。 The mark card 200 is set in the mark reading device, and the mark card 200 is read by the feed command.
is sent, and when the 0 column, which is the data prohibited area 201, reaches the read station, a column 0 signal 101 is supplied to the timing generation circuit 1 by a crow position detection circuit (not specifically explained here). In the timing generation circuit 1, the power supply control signal 102 is set to "0" for a predetermined period of time as shown in FIG.
04 is generated. Here, the time t 1 from the fall of the power supply control signal 102 to the rise of the check timing signal 103 and the time t 2 from the rise of the power supply control signal 102 to the rise of the check timing signal 104 are the times when the light receiving elements 31 to 104 are normal. The time is set to be slightly longer than the maximum response time for the rise and fall of 32.
第３図を参照して第１図に示す実施例の正常な
動作を説明する。ここで、簡単にするため受光素
子３１〜４２は、ばらつきなく同一の波形を発生
するものとする。電源制御信号１０２が“０”に
なると、電源回路２は出力電圧１０５を0Vに
し、発光ダイオード１１〜２２は点灯から滅灯へ
変化する。一方受光素子３１〜４２は発光ダイオ
ード１１〜２２からの光を受けて第３図に示す信
号１１１〜１２２を出力する。増巾整形回路５１
〜６２は信号１１１〜１２２を入力し、信号１１
１〜１２２が一定値以下のとき“１”で、一定値
以上のとき“０”である整形信号１３１〜１４２
を出力する。整形信号１３１〜１４２を入力する
NAND回路３及びOR回路４により、オールライ
ト信号１０７、オールダーク信号１０６が出力さ
れる。そしてフリツプフロツプ５，６の出力信号
１０８，１０９は、初め“０”にリセツトされて
おり、チエツクタイミング信号１０３，１０４の
立ち上がりで、その時のオールダーク信号１０
６、オールライト信号１０７の値にセツトされ
る。正常な場合、チエツクタイミング信号１０３
の立ち上り時には、第３図に示す様にオールダー
ク信号１０６は“０”であるためフリツプフロツ
プ５の出力信号１０８は“０”を保持する。次に
電源制御信号１０２が“０”から“１”に復帰す
るとそれに伴ない電源回路２の出力電圧１０５も
従来のレベルに復帰し、発光ダイオード１１〜２
２は、再度点灯する。そして、受光素子３１〜４
２の出力信号１１１〜１２２は白レベルまで立ち
上がり、１３１〜１５２の整形信号は“１”から
“０”へ変化する。チエツクタイミング信号１０
４の立ち上がり時には、既に整形信号１３１〜１
４２は全て“０”で、これによりオールライト信
号１０７が“０”になつているためフリツプフロ
ツプ６の出力信号１０９は“０”を保持してい
る。 The normal operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. Here, for the sake of simplicity, it is assumed that the light receiving elements 31 to 42 generate the same waveform without variation. When the power supply control signal 102 becomes "0", the power supply circuit 2 sets the output voltage 105 to 0V, and the light emitting diodes 11 to 22 change from lighting to extinguishing. On the other hand, the light receiving elements 31-42 receive the light from the light emitting diodes 11-22 and output signals 111-122 shown in FIG. 3. Width shaping circuit 51
~62 inputs signals 111~122, and inputs signal 11
Shaping signals 131 to 142 that are “1” when 1 to 122 are below a certain value and “0” when they are above a certain value
Output. Input the shaping signals 131 to 142
The NAND circuit 3 and OR circuit 4 output an all-write signal 107 and an all-dark signal 106. The output signals 108 and 109 of the flip-flops 5 and 6 are initially reset to "0", and at the rise of the check timing signals 103 and 104, the all dark signal 10 at that time is reset.
6. Set to the value of the all write signal 107. If normal, check timing signal 103
At the rising edge of , the all dark signal 106 is "0" as shown in FIG. 3, so the output signal 108 of the flip-flop 5 remains "0". Next, when the power supply control signal 102 returns from "0" to "1", the output voltage 105 of the power supply circuit 2 also returns to the conventional level, and the light emitting diodes 11 to 2
2 lights up again. And the light receiving elements 31 to 4
The output signals 111-122 of No. 2 rise to the white level, and the shaping signals 131-152 change from "1" to "0". Check timing signal 10
At the rise of 4, the shaping signals 131 to 1 are already
42 are all "0", which causes the all write signal 107 to become "0", so the output signal 109 of the flip-flop 6 holds "0".
以上に対し、応答性に不良がある場合の動作を
第４図を参照して説明する。発光ダイオード１２
〜２２、受光素子３２〜４２および増巾整形回路
５２〜６２すべてが正常で発光ダイオード１２〜
２２の点灯→滅灯→点灯の変化により信号１１２
〜１２２と整形信号１３２〜１４２が出力され、
発光ダイオード１１、受光素子３１のいずれかが
不良で、出力信号１１１′と整形信号１３１′が出
されているとする。するとNAND回路３によつて
出力されるオールダーク信号１０６′は第３図に
示す信号１０６と比べ“０”の時間が短くなり、
一方、OR回路４によつてつくられるオールライ
ト信号１０７′は“１”の時間が長くなる。結
局、光電系の不良により発光ダイオード滅灯時の
整形信号１３１′の応答性が悪く、チエツクタイ
ミング信号１０３の立ち上がり時にオールダーク
信号１０６′は未だ“１”であるため、フリツプ
フロツプ５の出力信号１０８′は“１”に変る。
この様にして発光ダイオード滅灯時の光電系の応
答性不良が検出される。また同様に発光ダイオー
ド点灯時の整形信号１３１′の応答が悪く、チエ
ツクタイミング信号１０４の立ち上がり時に、オ
ールライト信号１０７は未だ“１”であるため、
フリツプフロツプ６の出力信号１０９′は“１”
に変る。これによつて発光ダイオード点灯時の光
電系の応答性不良が検出される。 In contrast to the above, the operation when the response is poor will be explained with reference to FIG. 4. light emitting diode 12
~22, light receiving elements 32~42 and width shaping circuits 52~62 are all normal and light emitting diode 12~
Signal 112 due to the change of 22 lighting → off → lighting
~122 and shaping signals 132~142 are output,
Assume that either the light emitting diode 11 or the light receiving element 31 is defective, and an output signal 111' and a shaping signal 131' are output. Then, the all-dark signal 106' output by the NAND circuit 3 has a shorter "0" time than the signal 106 shown in FIG.
On the other hand, the all-write signal 107' generated by the OR circuit 4 remains "1" for a long time. In the end, due to a defect in the photoelectric system, the response of the shaping signal 131' when the light emitting diode is turned off is poor, and the all-dark signal 106' is still "1" when the check timing signal 103 rises, so the output signal 108 of the flip-flop 5 ' changes to "1".
In this way, poor responsiveness of the photoelectric system when the light emitting diode goes out is detected. Similarly, the response of the shaping signal 131' when the light emitting diode is turned on is poor, and the all-write signal 107 is still "1" at the rise of the check timing signal 104.
The output signal 109' of flip-flop 6 is "1"
Changes to As a result, poor responsiveness of the photoelectric system when the light emitting diode is turned on is detected.
また、従来の検出回路でチエツクされていた光
電系の固定障害に関しては、応答性不良の応答時
間が無限大になつた状態と同じであるので、本発
明の光電系チエツク回路でも検出出来る事は勿論
である。 Furthermore, regarding fixed faults in the photoelectric system that were checked by conventional detection circuits, the situation is the same as when the response time of poor response becomes infinite, so the photoelectric system check circuit of the present invention cannot detect them. Of course.
また本実施例において、特に説明をしないがデ
ータ禁止エリア２０１である０カラム目にマーク
データがある媒体不良も、セルの固定障害の時と
同様に検出される。 Further, in this embodiment, although not specifically explained, a medium failure in which there is mark data in the 0th column, which is the data prohibited area 201, is also detected in the same way as a fixed cell failure.
本発明は以上説明したように、発光源を点灯→
滅灯→点灯させる事により、光電系の固定障害、
応答性不良を検出できる効果がある。 As explained above, the present invention turns on the light emitting source→
By turning the light off → on, a fixed failure of the photoelectric system,
This has the effect of detecting poor responsiveness.
第１図は本発明の一実施例のブロツク図、第２
図はマークカード２００のデータ禁止エリア２０
１を示す図、第３図は第１図に示す実施例の正常
な動作を説明する図、第４図は不良がある場合の
第１図に示す実施例の動作を説明する図である。
１……タイミング発生回路、２……電源回路、
３……NAND回路、４……OR回路、５，６……
フリツプフロツプ、１１〜２２……発光ダイオー
ド、３１〜４２……受光素子、５１〜６２……増
巾・整形回路、２００……マークカード。
FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The figure shows the data prohibited area 20 of the mark card 200.
1, FIG. 3 is a diagram for explaining the normal operation of the embodiment shown in FIG. 1, and FIG. 4 is a diagram for explaining the operation of the embodiment shown in FIG. 1 when there is a defect. 1... Timing generation circuit, 2... Power supply circuit,
3...NAND circuit, 4...OR circuit, 5, 6...
Flip-flop, 11-22...Light emitting diode, 31-42...Light receiving element, 51-62...Width amplification/shaping circuit, 200...Mark card.
Claims (1)
灯指示および滅灯指示を行なう電源制御信号を発
生しチエツク時に該電源制御信号により前記発光
源に該滅灯指示を行つた時点から予め定めた第１
の応答最大時間だけ経過した時点で第１のチエツ
クタイミング信号を発生し該電源制御信号により
前記発光源に該点灯指示を行つた時点から予め定
めた第２の応答最大時間だけ経過した時点で第２
のチエツクタイミング信号を発生するタイミング
発生手段と、前記発光源からの光信号レベルを電
気信号レベルに変換する光電変換手段と、前記第
１のチエツクタイミング信号が発生した時点で前
記電気信号レベルが予め定めた第１のレベル以上
であるとき所定の信号を出力する第１のチエツク
手段と、前記第２のチエツクタイミング信号が発
生した時点で前記電気信号レベルが予め定めた第
２のレベル以下であるとき所定の信号を出力する
第２のチエツク手段とを含むことを特徴とする光
電系チエツク回路。1 Generates at least one light emitting source and a power control signal that instructs the light emitting source to turn on and turn off, and at the time of checking, a predetermined period starts from the time when the power control signal instructs the light emitting source to turn off the light. 1
A first check timing signal is generated when a predetermined second maximum response time has elapsed from the time when the power supply control signal instructs the light emitting source to turn on. 2
a timing generation means for generating a check timing signal; a photoelectric conversion means for converting an optical signal level from the light emitting source into an electric signal level; a first check means for outputting a predetermined signal when the electric signal level is equal to or higher than a predetermined first level; and the electric signal level is equal to or lower than a predetermined second level at the time when the second check timing signal is generated. 1. A photoelectric system check circuit comprising: second check means for outputting a predetermined signal when
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14056479A JPS5665270A (en) | 1979-10-31 | 1979-10-31 | Photoelectric system check circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14056479A JPS5665270A (en) | 1979-10-31 | 1979-10-31 | Photoelectric system check circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5665270A JPS5665270A (en) | 1981-06-02 |
| JPS6259831B2 true JPS6259831B2 (en) | 1987-12-12 |
Family
ID=15271607
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14056479A Granted JPS5665270A (en) | 1979-10-31 | 1979-10-31 | Photoelectric system check circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5665270A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05266242A (en) * | 1992-03-23 | 1993-10-15 | Tokyo Electric Co Ltd | Laser scanner device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4928438U (en) * | 1972-06-13 | 1974-03-11 | ||
| JPS4979125A (en) * | 1972-12-01 | 1974-07-31 |
-
1979
- 1979-10-31 JP JP14056479A patent/JPS5665270A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4928438U (en) * | 1972-06-13 | 1974-03-11 | ||
| JPS4979125A (en) * | 1972-12-01 | 1974-07-31 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5665270A (en) | 1981-06-02 |
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