JPS6258355A - Interruption control circuit - Google Patents

Abstract

PURPOSE:To perform the optimum interruption in accordance with each state by changing optionally the interruption priority among plural devices by the designation of a program and informing the interruption request having the highest priority to a central processing circuit among plural interruption requests. CONSTITUTION:In case two devices have interruption requests, an interruption priority varying circuit 5 allocates both interruption requests to interruption request lines 6 and 7 through interruption request lines 3 and 4 according to the information designated previously by a central processing circuit 9. The lines 6 and 7 have different levels of priority and an interruption priority control circuit 8 informs the interruption request having higher priority to the circuit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt control circuit in an information processing apparatus that performs program control.

[Conventional technology]

Conventionally, this type of interrupt control circuit has a configuration as shown in the block diagram of Figure 3, in which a fixed priority is assigned to each interrupt request from each device. The interrupt priority control circuit 8 accepts the interrupt of the highest priority among the interrupt requests from each device ST.

[Problems to be Solved by the Invention] In the conventional interrupt control circuit described above, the interrupt priority of each device is fixed at a certain level. This method has the disadvantage that it is not possible to change the priority for processing, making it difficult to control the system flexibly.

SUMMARY OF THE INVENTION An object of the present invention is to solve such problems and provide an interrupt control circuit that can flexibly control a system by varying the interrupt priority of each device.

[Means for solving problems]

The present invention provides an interrupt control circuit for an information processing apparatus including an interruptible central processing circuit and a plurality of devices each having means for requesting an interrupt to the central processing circuit. an interrupt priority control circuit that notifies the central processing circuit of the interrupt request with the highest priority; and an interrupt priority control circuit that arbitrarily changes the interrupt priority of each device according to a designation from a program to give priority to the interrupt. and an interrupt priority variable circuit having means for supplying the signal to the control circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

This embodiment shows a case where there are two interrupt requesting devices (devices 1 and 2). These device 1 and device 2
When making an interrupt request, it notifies the interrupt priority variable circuit 5 through each interrupt request line 3.4. This interrupt priority variable circuit 5 distributes each interrupt request to an interrupt request line 6.7 according to information specified in advance from the central processing circuit 9.

These interrupt request lines 6.7 have different interrupt priorities. Among the interrupt requests from the interrupt request lines 6 and 7, the interrupt priority control circuit 8 accepts the interrupt request with higher priority and notifies the central processing circuit 9 of the interrupt request.

FIG. 2 is a circuit diagram of an example of the interrupt priority variable circuit 5. As shown in FIG.

Interrupt priority information from the central processing unit 9 is supplied from an input terminal 25 to a 4-bit register 10 and set therein. The control gates 11-14 are controlled by the output signal from the 4-pin I register 10, and the electrical connection between the interrupt input line 21.22 and the interrupt output line 23.24 is controlled.

Although this embodiment shows a case where there are two interrupt request devices, it is also possible to easily realize a case where there are three or more interrupt request devices with a similar circuit configuration.

〔Effect of the invention〕

As explained above, by dynamically changing the interrupt priorities of multiple devices using a program, the present invention can configure a system with optimal interrupt priorities depending on the current state. This has the effect of allowing the system to be operated flexibly and improving system performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of an example of the interrupt priority variable circuit of FIG. 1, and FIG. 3 is a block diagram of a conventional interrupt control circuit. 1.2. N...Device, 3.4...Interrupt request line,
5... Interrupt-priority variable circuit, 6, 7... Interrupt request line, 8... Interrupt priority control circuit, 9... Central processing circuit,
10... 4-bit register, 11-14... Control gate circuit, 21.22... Interrupt input line, 23.24...
...Interrupt output line, 25...control input terminal.

Claims (1)

[Claims] In an interrupt control circuit of an information processing apparatus that includes a central processing circuit capable of processing interrupts and a plurality of devices each having means for requesting an interrupt to the central processing circuit, the interrupt request having the highest priority among the plurality of interrupt requests is an interrupt priority control circuit for notifying the central processing circuit of a higher priority; and a means for arbitrarily changing the priority of the interrupt request from each device according to a designation from a program and supplying the same to the interrupt priority control circuit. An interrupt control circuit comprising: an interrupt priority variable circuit having a variable interrupt priority level;