JPS6257839U - - Google Patents
Info
- Publication number
- JPS6257839U JPS6257839U JP14660385U JP14660385U JPS6257839U JP S6257839 U JPS6257839 U JP S6257839U JP 14660385 U JP14660385 U JP 14660385U JP 14660385 U JP14660385 U JP 14660385U JP S6257839 U JPS6257839 U JP S6257839U
- Authority
- JP
- Japan
- Prior art keywords
- counting means
- error detection
- reporting
- information processing
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 7
- 230000010365 information processing Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図はこの考案の一実施例による情報処理装
置のエラー検出・報告装置を示すブロツク図、第
２図は従来のエラー検出・報告装置を示すブロツ
ク図である。
１はエラー検出回路、２はエラー信号、３Ａは
エラー報告回路、４は計数手段、５はキヤリー信
号、６はリセツトパルス発生器、７はクロツク信
号、８はリセツトパルスである。尚、図中、同一
符号は同一、又は相当部分を示す。
FIG. 1 is a block diagram showing an error detection/reporting device for an information processing apparatus according to an embodiment of this invention, and FIG. 2 is a block diagram showing a conventional error detection/reporting device. 1 is an error detection circuit, 2 is an error signal, 3A is an error reporting circuit, 4 is a counting means, 5 is a carry signal, 6 is a reset pulse generator, 7 is a clock signal, and 8 is a reset pulse. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
を検出するエラー検出回路と、このエラー検出回
路で検出されたエラー信号の発生回数を計数する
計数手段と、所定間隔でリセツトパルスを発生し
て前記計数手段をリセツトさせるためのリセツト
パルス発生器と、前記計数手段からのキヤリー信
号をソフトウエアへ報告するためのエラー報告回
路とを備え、前記計数手段に所定回数のエラー信
号が印加された場合にのみ、前記計数手段４から
前記キヤリー信号が発生されることを特徴とする
情報処理装置のエラー検出・報告装置。 (2) 計数手段がＮ進カウンタであり、リセツト
パルス発生器がＭ進カウンタである（たゞし、Ｎ
およびＭは正の整数である。）ことを特徴とする
実用新案登録請求の範囲第１項記載の情報処理装
置のエラー検出・報告装置。[Claims for Utility Model Registration] (1) An error detection circuit for detecting a hardware failure in an information processing device, a counting means for counting the number of occurrences of an error signal detected by the error detection circuit, and A reset pulse generator for generating a reset pulse to reset the counting means, and an error reporting circuit for reporting a carry signal from the counting means to software, the counting means having a predetermined number of errors. An error detection/reporting device for an information processing device, characterized in that the carry signal is generated from the counting means 4 only when a signal is applied. (2) The counting means is an N-ary counter, and the reset pulse generator is an M-ary counter (only
and M is a positive integer. ) An error detection/reporting device for an information processing device according to claim 1 of the utility model registration claim.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14660385U JPS6257839U (en) | 1985-09-27 | 1985-09-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14660385U JPS6257839U (en) | 1985-09-27 | 1985-09-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6257839U true JPS6257839U (en) | 1987-04-10 |
Family
ID=31059220
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14660385U Pending JPS6257839U (en) | 1985-09-27 | 1985-09-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6257839U (en) |
-
1985
- 1985-09-27 JP JP14660385U patent/JPS6257839U/ja active Pending
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