JPS6256997A - Pattern matching apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a speech recognition device, and particularly to a pattern matching device suitable for performing pattern matching between an input speech pattern and a standard pattern.

[Background of the invention]

A voice AM device divides the voice uttered by a specific person into words, for example, and stores them as patterns representing their characteristics in advance, and then inputs a voice pattern (hereinafter referred to as
It recognizes the input voice by comparing the input voice pattern) with the stored voice pattern (hereinafter referred to as the standard pattern), and recognizes the voice of a specific person whose voice is stored as the standard pattern. It is something that is recognized and made possible.

By the way, in conventional speech recognition devices, since each input speech pattern is compared with all the standard patterns, a large number of standard patterns are stored, and a large number of feature points are represented by the standard patterns. In this case, it takes a long time to match each input speech pattern, reducing recognition efficiency.

There was a problem.

In order to solve this problem, for example,
Hopefully it will be disclosed in Publication No. 29293.

By storing standard patterns in a standard pattern storage device with systematic levels assigned to them, and comparing the input audio pattern with the standard pattern of the corresponding level, the input audio signal and the standard pattern (hereinafter referred to as A speech recognition device has been proposed that has certain limitations (called standard patterns to be recognized).

By the way, in such a speech recognition device, depending on the level of the input speech pattern, the start address and the end address of the storage area of the standard pattern storage device in which the standard pattern of the level matching the level is stored are specified.
The standard pattern read from this storage area is selected as the standard pattern to be recognized.

However, in the standard pattern storage device, the standard patterns are stored in the order in which they are input, so the storage areas in which the standard patterns of the same level are stored are often divided into a large number of areas. Therefore, in order to find out whether or not the standard pattern stored in the standard pattern storage device is a standard pattern to be recognized at the same level as the input voice pattern, first all standard patterns are stored in the standard pattern storage device. It is necessary to be able to determine whether or not the level of each input voice pattern is the same as that of the input voice pattern.

By making such a determination, it is possible to know the storage area of the standard pattern to be recognized in the standard pattern storage device.

Therefore, even in this conventional technique, the amount of data to be processed is extremely large, and pattern recognition also requires a long time tt.

[Purpose of the invention]

The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art, efficiently limit standard patterns to be recognized, increase recognition speed in a speech recognition device, improve recognition efficiency, and avoid expanding the scale of hardware. An object of the present invention is to provide a pattern matching device capable of suppressing pattern matching.

[Summary of the invention]

To achieve this objective, the present invention stores, for each stored standard pattern, information indicating whether or not the standard pattern becomes a standard pattern to be recognized for an input speech pattern. Although the storage addresses of the standard patterns are specified sequentially, the system is characterized in that only the standard pattern to be recognized is read out based on the information.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of a pattern matching device according to the present invention, in which 1 is a microcomputer, 2 is a standard pattern memory, 3 is an interface, and 4 is a block diagram showing an embodiment of a pattern matching device according to the present invention.
5 is an input frame memory, 5 is a distance calculation section, 6 is a menu interface section, 7 is a control section, 8 is a collation section, 9 is a determination section, and 10 is a character pattern generator.

In the figure, this embodiment is a microcomputer]
operates under the control of The control unit 7 has a built-in microprogram that stores the start address and number of standard patterns of the standard pattern memory 2 in which standard patterns set in advance are stored.

Verification processing content 1 Processing is performed according to a predetermined graph according to parameters such as a determination threshold value.

The characteristic parameters of the input voice pattern are obtained by processing the voice input to a voice input section (not shown) in an analysis section, and are transferred to the micro combiator 1. Further, the characteristic parameters are transferred from the microcomputer 1 to the input frame memory 4 via the interface and the data bus a. This allows input frame memory 4
Stores feature parameters for one frame of the input audio pattern.

Note that a frame is a division of the input audio pattern into units of time.

When the above transfer to the input frame memory 4 is completed ↑, the control unit 7 detects this based on the control signal group 1-m-14C, and the distance calculation unit 5. Control the matching section 89 and the determining section 9 to perform pattern matching processing as follows.

First, the control section 7 drives the distance calculation section 5 using the control signal group 1-m-2, and drives the meso interface section 6 using the control signal group 1-m-3. : jlA, put pattern memory 2 in access state. Then, control signal group 1-m-
1, the feature parameter X- of the input voice pattern is read in and out from the input frame memory 4 and transferred to the distance calculation section 5, and in synchronization with this, the feature parameter Yjk of the standard pattern is read out from the standard pattern memory 2 and is sent to the distance calculation section. 5
Transfer to.

Here, Xlk is the feature parameter of the i-th frame of the input audio pattern (k channel), and Y
jk is the feature parameter of the jth frame (k channel) of the standard pattern.

The distance calculation unit 5 synchronizes and sequentially imports feature parameters from the input frame memory 4 and the standard pattern memory 2, but the feature parameters that are simultaneously fetched from these are those of the same channel, and processes these kl frames to calculate, for example, , the Chebyshev distance di is calculated using the following equation.

d, = Σ () (, to - Y, k) represents the difference of k = 1. This distance dij is control 1! l
The words are transferred to the matching unit 8 driven by the control signal group 1-m-4 from s7, and are subjected to word matching processing to obtain a matching value. This matching value is
It is sent to the determination unit 9 driven by control signal group 1-m-5 from , and finds candidates from all the words.

The matching section 811 and the fixed section 9 are, for example, disclosed in Japanese Unexamined Patent Application Publication No. 57-838.
Those disclosed in No. 80 can be used, and for details thereof, please refer to the above-mentioned patent publication.

A large number of standard patterns are stored in the standard pattern memory 2, and each standard pattern &
C is whether pattern matching processing should be performed with the input audio pattern input via the microcomputer 1;
That is, information (hereinafter referred to as a skip flag) indicating whether or not this input speech pattern is a standard pattern to be recognized is added, and this skip flag causes the input speech pattern to be imported from the standard pattern memory 2 to the distance calculation unit 5. A standard pattern is determined.

This point will be explained in more detail with reference to FIG. 2 showing a specific example of a data storage method in the standard pattern memory 2. Before that, each symbol in FIG. 2 will be defined as follows.

The figure shows the storage areas of the first standard pattern, the nth standard pattern, and the last 8PNth standard pattern in the standard pattern memory 2. 5P(n): Skip flag of the nth standard pattern .

PL(n): Frame length of the standard pattern of nth 1 (1″
i.e. number of frames).

8pF'(n,j): jth frame of the nth standard pattern.

Y(n,j,k): the th feature parameter (channel, which is the previous feature parameter Y,) of that frame.

CH: Number of feature parameters (number of channels) within one frame.

Toteru.

In the storage area of each standard pattern, taking the storage area of the nth standard pattern as an example, the MOB (most significant bit) at the beginning address is the skip flag SF (in Fig. 2, the skip flag of the nth standard pattern is The lower bits removed are the frame length FL (in Fig. 2, the frame length of the n-th standard pattern is expressed as FL(n)). It represents. At subsequent addresses, each frame S PF (
.

n, 1), 5PF (n, 2 L------...-, 8
PF(n, j), ......... are stored in the header, but the storage area of each of these frames is the feature parameter Y(nt je IL Y(
n, je 2), ・・・・・・・・・＊ Y (ne
It consists of the address where J e CH) is stored.

The skip flag 8F(n) is set to 'O1' when the nth standard pattern is a standard pattern to be recognized, and to 1 when it is not a standard pattern to be recognized.
1” respectively.

In FIG. 1, when the memory interface unit 6 specifies the read address of the standard pattern memory 2 and reads a standard pattern, it first reads and reads the skip flag 8F added to the standard pattern to be read/output. , thereby determining whether this standard pattern is a standard pattern to be recognized. If this is a standard pattern to be recognized, as explained above, for all of this standard pattern σ, the distance meter Distance from frame d, (however, j=1.2°3,...
. , PL, this PL is sent as defined earlier.

When it is determined that the standard pattern is not a standard pattern to be recognized, this standard pattern is not read from the standard pattern memory 2, and the same determination is made for the next standard pattern from the skip flag 8F.

In this way, only the 7 Rems of the standard pattern determined to be the recognition target by the skip flag 8PK are read out from the standard pattern memory 2, and the input frame memory 4
Pattern matching processing is performed with the frames stored in .

When the pattern matching process is performed on one frame of the input audio pattern, the next frame is stored in the input frame memory 4, and the same pattern matching process is performed on all frames of the input audio pattern. A pattern matching process is performed to select a standard pattern for the input audio pattern.

The skip flag SF in the standard pattern memory 2 is
Each time an input voice pattern is input, it is changed and set according to this input voice pattern.

This is done using the data stored in the memory 10, which will be explained below.

A method of storing a standard pattern in the standard pattern memory 2 and a method of storing data in the memory 10 will be described.

In the host computer A, category numbers are set in advance for each type of word, and these category numbers are stored in the internal memory. For example, if a word represents a number, use ``1'', if the word represents a place name, use ``2'', and so on. Give each type a different category number.

The standard pattern is that a specific person using a voice recognition device
Before using this, please register your voice in advance.
The sound to be emitted is patterned by the analysis section, and when this standard pattern is supplied, the host computer A sends it together with the standard pattern to the microcomputer 1 with the corresponding category number. Microcomputer 1 detects the frame length of this standard pattern,
[Sequentially designate the 20th address of the 4-pattern memory, write the frame length FL to the first address as shown in Figure 2,
Each frame of the standard pattern is written in SPF order starting from the next address.

Along with this, the microcomputer 1 has a memory 10
Write the storage address based on the leading address and the final address of the storage area of the m pattern (this consists of the starting address for storing the frame length and the storage address of each frame of the standard pattern) in the standard pattern memory 2, Next, write the category number of this standard pattern. Therefore, the storage address and category number for each standard pattern stored in the standard pattern memory 2 are stored in the memory 10, as shown in FIG.

At this time, nothing is written to the MSB (most significant bit) of the first address of each standard Pacui storage area in which the frame length PL of the standard pattern memory 2 is written.

Next, setting and changing of the skip flag SF in the m quasi-pattern memory 2 will be explained.

These operations are performed for each input voice pattern. When an input voice pattern is input, the host computer A sends the category number for this input voice pattern to the microcomputer 1. Microcomputer 1 is memory 1
0ρ), read out the pair of storage address and category number,
Based on this category number and the category number input by the host computer person, it is determined whether the standard pattern stored at the storage address read from the memory 10 of the standard pattern memory 2 is the standard pattern to be recognized. Out. When this standard pattern is determined to be a standard pattern to be recognized, the MOB at the first address of the storage area of this standard pattern in the standard pattern memory 2 is IQI? , and when it is determined that it is not a standard pattern to be recognized, this MOB is set to '1'' and a skip flag 8F is added to each standard pattern as shown in Figure 2. Ru.

This operation is performed for each input audio pattern, and the skip flag SF is rewritten according to the input audio pattern.

FIG. 4 is a flowchart showing the above operation, in which steps 1 to 3 are the process of writing the standard pattern to the standard pattern memory 2 and data writing to the mesh 10, and steps 4 and 5 are the processes of writing the standard pattern to the standard pattern memory 2 and the process of writing data to the standard pattern memory 10. This is a process of writing and changing the skip flag 8F to 2.

FIG. 5 is a block diagram showing a specific example of the selection section for reading data from the standard pattern memory 2 of the memory interface section 6 in FIG. Below, SPMS
13 is a standard pattern number register (hereinafter referred to as 8PNR), 14 is a frame characteristic parameter (channel) number register (hereinafter referred to as CHR), 1
5 is the standard pattern memory address register (hereinafter referred to as 8P)
16 is a frame length register (hereinafter referred to as F
17 is a frame length counter (hereinafter referred to as FL).
18 is a frame characteristic parameter (channel) number counter (hereinafter referred to as CHC), 19 is a standard pattern number counter (hereinafter referred to as 5PNC), 20
2 is a standard pattern frame register (hereinafter referred to as 8PFR), 21 is a calculating section, and 22 to 25 are comparators.

In the figure, the start address representing the first address of the standard pattern memory 2 supplied from the control unit 7 (FIG. 1) via bus b is stored in 8PMSAR12, the final standard pattern number is stored in 5PNR13, and The number of feature parameters (number of channels) per frame is CH
Stored in RI4. The SPMAR 4 stores an address value representing the address to be specified in the standard pattern memory 2, and this address value is calculated by the calculating section 10 and sent to the standard pattern memory 21C via the bus cf. As a result, when the starting address of the standard pattern storage area is specified in the standard pattern memory 2, the frame length read from there is stored in FLS"1 FLR16.
The comparator 22 compares the skip flag 8F with the reference data of 1". When the skip flag 8F is 1", the comparator 22 outputs 1" data, and the skip flag E3F is 0". At times, the comparator 22 outputs "0" data. The output data of the comparator 22 is sent to the control section 7 (
Figure 1). The control unit 7 thereby controls the 8PNC.
Send a pulse to 19 and increase its count value by 1.

The frame length PL stored in the FLRI 6 is determined by the comparator 23.
is compared with the count value of the FLC 17, and when the latter is larger than the former, the comparator 23 outputs data of 1'' and sends it to the control unit 7.
Send a pulse to 19th.

Increase the count value by 1. The count value of CHC 18 is compared with the number of channels CH per frame stored in CHRI 4 by comparator 24, and when the former exceeds the latter, comparator 24 outputs data of ``1''. It is sent to the control section 7.

The control unit 7 thereby sends pulsed FLC17&C,
Increase that count value by tt1. CHCl8 is
Every time a designated address value such as an address in the standard pattern memory 2 is set in SPMAR15, a pulse is sent from the control section 7, and the count value is increased by one.

, CHCl8 indicates the number of read characteristic parameters of a certain frame in the standard pattern stored in the standard pattern memory 2.

If this count value exceeds the number of channels stored in CHRx4vc, it means that the characteristic parameters of this entire frame have been read and output, and the comparator 24 outputs data of 1"1", so the FLC17 counts by 1. It's up. The count value of FLC17 represents the number of read frames in the standard pattern,
The fact that the count value is amplified by 1 when the comparator 24 outputs data of 11'' indicates that the next 7 frames will be read from the standard pattern memory 2.Then, the count value of the FLC 17 will be amplified by 1. FL, R161
Exceeding the stored frame length FL- means that
This means that all frames of one standard pattern have been read out, and at this time, the comparator 23 outputs data of '1' and the count value of the f!3PNC 19 is increased by 1.

The 8PNC190 count value represents the number of the standard pattern to be read/output from the standard pattern memory 2. Therefore, when the reading of one standard pattern is completed and the comparator 23 outputs data @1'', the count value of the 8PNC 19 is incremented by 1 to hold the number of the next standard pattern to be read.

However, the 8PNC190 count value indicates that the comparator 22 is '1'.
'' data is also counted up by 1, so the standard pattern of the number represented by the 8PNC190 count value is the skip flag 8F added to it.
When it is determined that it is not a standard pattern to be recognized because K is 11", K is 5PNC19.
will be immediately changed to the next standard pattern number.

Every time an address value is set in SPMARl5, the characteristic parameter is output from the address specified by this address value from the standard pattern memory 2, and the next parameter is outputted from the standard pattern memory 2.
Once the feature parameters of one frame have been stored, they are taken into the distance calculation unit 5.

Next, the operation of this specific example will be explained using the flowchart shown in FIG.

First, before reading/outputting the standard pattern memory 2, the start address value SPM8A representing the first address of the standard pattern memory 2, the final standard pattern number SPN, and the number of characteristic parameters per frame CH are set in the microcomputer 1 (the 1) via bus b,
They are stored in SPMSAR12, 8PNR13, and CHR14, respectively. Along with this, FLC17, CHC18 and 5PNC19 should be reset.

Once such initial settings are made, the 8PM8AR1
The stored value [: SPMSAR:l (This is the start 7 code vx value SPMSA representing the first address of standard pattern memory 2) is transferred to SPMARl 5,
Further, a pulse is supplied to 8PN019, and its count value becomes 1 (step 1).

Next, the control unit 7 takes in the output data of the comparator 24, and the count value of 5PN019 (1:5PNc) is 5PNR.
It is determined whether the stored value of 2 (8PNR) (this is the final standard pattern number 8PN) has been exceeded (step 2).

In this case, since the count value [5PNC'') represents the first standard pattern number, it is determined as "no", and the address value set in 8PMAR15 (SPMAR
) is read out from the standard pattern memory address 20 specified by . This address is the starting address of the storage area of the first standard pattern in the standard pattern memory 2, and as is clear from the explanation in FIG.
F) is M8B9I: The frame length (SP
M~AR) MliB (Ding, PL) is read in and out respectively, and this frame length [S P MA R] M8B is FL
Along with being stored in IL 16 (step 3), the skip flag (SPMAR) Mll is provided to comparator 22. control! The IS7 receives the output data of the comparator 22 and determines whether the skip flag (SPMAT L) M8B is '1' (step 3).

Skip flag (8PMA4) When old l is 1”,
It is determined that the first standard pattern is not the standard pattern to be recognized, and either the process proceeds to step 13 to read and read the next standard pattern, or the skip flag (sPMA
R] When Mai+ is 1''' and it is determined that the first standard pattern is the standard pattern to be recognized, the control unit 7
A pulse is sent to LCI 7, and the count value is IK''f (step 5).Then, this count value (FLCI and the frame length (F'LC' stored in FLRI 6) is
The output data of the comparator 23 that compares ff (same as the previous (:8PMAR) r tube) is taken into the control section 7, and the magnitude relationship between the two is determined (skip 6).

The count value (FLC) of FLCI7 at this time represents the first frame of the first standard pattern, and is (FLCP((FLR)).

Therefore, the control unit 7 sends a pulse to the CHC 18 and increases the count value (CHC) by 1 VC (step 7). This count value (CHC:l) is compared with the number of feature parameters per frame [CH] stored in the CHRI 4 by the comparator 24, and their magnitude relationship is determined (step 8).

Here, the count value (CHC) of CHC18 is
It represents the number of the first feature parameter in the th frame, and is (CHC)((CH㇠).

Therefore, next, the calculation unit 21 receives the stored value of SPMARI5 (8PMAR), the count value of FLCI7 (FLC), and the stored value of CHRI4 (CHR), and calculates the value (8PMAR) + ((FLC) - 1). *CCHR)+1
...The calculation in (1) is performed, and the result of this calculation is transferred to 8PMAR15&C as the next address. Here, star) 7 tov x (S P M 8 A R
) = 1 7) Since [FLC)' = 1, the above calculation result is 2, and the value stored in SPMARI5 (SPMAR) is 2, which is the first standard pattern in standard pattern memory 2. The second address of the storage area is specified. As is clear from FIG. 2, the first characteristic parameter of the first frame of this standard pattern is stored at this address. This is represented by the symbol Y(1,1-1) in FIG. In addition, in the same way, in general, the th feature parameter of the jth frame of the nth standard pattern is expressed as Y(n.

Lk) and Omotesawa Ding.

Further, a pulse is sent to CHCl8 from the control unit 7,
The count value (CHC) is 1+1=2 (above,
Step 9).

Then, the address [(S
PMARI specifies the second address of the storage area of the first standard pattern in the standard pattern memory 2, and the feature parameter Y(1,1
, 1) are supplied to 8PFRQ&C via bus d (step 10).

Thereafter, the loop of steps 8, 9, and 10 is repeated, and the address value (8PMAR''3) stored in SPMARI 5 changes by 1 according to the above equation (1). The feature parameters Y(1
, 1, k) (k=1°2.3..., OH) are output in order @IIC reader and stored in 5PFR20.

All feature parameters of this frame are read and 8
Once stored in the PFR 20, this frame is taken into the distance calculation unit 5.

Along with this, the count value (CHC) of CHCl8 is
The number of feature parameters (CHR) per frame stored in the HRI 4 exceeds v, and in step 8, the control unit 7 determines this from the output data of ``1'' of the comparator 24, and sets the count value of the FLCI 7 ( FLC) ft1 and 2 and tero (step 11) and CHC
l 8'a' reset 2 pieces.

This changes the number of the second frame to FLCI7.
, and the feature parameter reading operation for this frame is performed from step 6.

In the same manner, each frame of the first standard pattern is sequentially read out from the standard pattern memory 2 to form 5PFR.
20 to the distance calculation unit 5, step IIK
Therefore, the count value (FLC) of the FLC 17 increases by VC1 every time reading of a frame is completed.

When the count value [FLC] exceeds the number of frames (frame length) of the first standard pattern stored in the FLRI 6, the output data of the comparator 23
Since the value is "1", control 117 is determined (step 6). This means that reading of all frames of the first standard pattern has been completed.

Therefore, the control unit 7 resets FLC17 and CHCl8, and sends /<rus to 8PN019.
Increase the count value [8PNC] by 1 to 1
+1 = 2. This indicates that the reading/reading of the next second standard pattern is to be started. At the same time, the calculation unit 21 fetches the address value (SPMAR) stored in SPMARl5, (8PMAR)+1...
...Perform the calculation in (2) and use the calculation result as the address representing the start address of the storage area of the wczth standard pattern in the standard pattern memo IJ2K.
Transfer to MAR15 (hereinafter, step 12).

That is, since the address value [8PMAR] representing the final address of the storage area of the first standard pattern in the standard pattern memory 2 is stored in SPMARl 5, the address value (SPMAR) obtained by the above equation (2) is
) specifies the starting address of the storage area of the second standard pattern.

Therefore, the frame length (SPMAR) for the second standard pattern from this address is read out, and the FLR
stored in l 6 (step 3) and also skips 7 lag (8PMAR) MS! When I is read or output, it is either “1” or 00.
” is determined (step 4).Then, this is the same as the first standard pattern, and the series of operations from step 5 to step 11 (from the second standard pattern) Reading and reading are performed.

Hereafter, in the same way, skip flag (SPMA 几) M8
．． A similar read operation is performed for all the standard patterns in which the value is 0''.

Skip flag [1!3PMA几]□ in step 4.

is determined to be 11'', the standard pattern to be read is not the standard pattern to be recognized, and for this reason, control g7 sends a pulse Y to 8PNCx9 to amplify its count value (8PNC) by 1. , shall be the number of the next standard pattern.

Along with this, the calculation unit 21 performs SPMARl 5. FLR
I6 and CHR14 stored value withdrawal, (8PM
AR)+(FLR1*[CHR)+1 ・・dan・(3
) is performed, and the result of the calculation is transferred to SPMAR15 as an address value (step 13).

8PMARI5σ immediately before the operation of step 13
]Address value (i.e., in formula (3) above) (SPMA
R) represents the starting address of the storage area in the standard pattern memory 2 of the standard pattern that is determined not to be the standard pattern to be recognized, and (R) in equation (3)
PL 几) *(C)in, ] represents the number of addresses in this memory area, so the address value 1: SPMAR] obtained from equation (3) was determined to be not a standard pattern to be recognized. It represents the starting address of the storage area of the standard pattern following the standard pattern.

As shown in σ), when the skip flag (SPMAR) M8° is '1'', &C skips over the address of the standard pattern to which it has been added, and specifies the first address of the storage area of the next standard pattern.

For the final standard pattern, the count value of 5PNC19 (8
When PNC:l exceeds the final standard pattern number [5PNR] stored in the 5PNR 13, the control unit 7 determines that this is the case based on the fact that the output data of the comparator 25 has become '1' (step 2).

This means that the reading operation of the standard pattern memory for one frame of input audio data stored in the input frame memory 4 (Fig. 1) has been completed, and the next frame is stored in the input frame memory 4. In addition to being stored, standard pattern memo IJ is sent from SPMSAR12.
The start address that represents the first address of 12 is SPMAR.
Transfer to 15tt,,b Todo4)&C1FLC17,
CHC18, [)'5PNC19 is reset.

Then, the same standard pattern reading operation as described above is performed on this frame stored in the input frame memory 4.

As described above, among the standard patterns stored in the standard pattern memory 2, the input audio pattern with the standard pattern to be recognized is subjected to pattern matching processing.

In the above embodiment, pattern matching is performed with all frames of the standard pattern to be recognized, such as frames of the input audio pattern, but pattern matching is performed only with a specific number of such standard patterns or frames with a specific number. Matching processing may also be performed.

〔Effect of the invention〕

As explained above, according to the present invention, the standard pattern is 1m! ! By simply adding a small amount of information to each standard pattern to indicate whether or not it is a target, the number of standard patterns to be pattern matched with the input voice pattern can be reduced, and unnecessary standard patterns and In addition to pattern matching processing, it is also possible to easily determine whether or not a standard pattern is to be recognized using the above information, greatly improving recognition efficiency and rate and significantly increasing recognition processing speed.

It would be possible to provide a pattern matching device with excellent functionality by eliminating the drawbacks of the prior art described above.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of the pattern matching device according to the present invention, Figure 2 is a schematic diagram showing a data storage method in the standard pattern memory in Figure 1, and Figure 3 is the memory in Figure 1. FIG. 94 is a flowchart showing the standard pattern and skip flag write operation in FIG. 1, and FIG. 5 is a specific example of the main part of the memory interface section in FIG. 1. The block diagram and FIG. 6 are flowcharts showing the operation of a specific example thereof. 1...Microcomputer, 2...
all pattern memory, 4... input frame memory, 5... distance calculation section, 6... memory interface section, 7... control section, 8...・
... Verification section, 9... Judgment section, 10...
·memory. Agent: Kenjibe Take, patent attorney (and one other person) Figure 2, Figure 3. Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] In a pattern matching device that performs pattern matching processing on an input voice pattern and a standard pattern and selects the standard pattern that matches the input voice pattern, the standard pattern memory that stores the standard pattern includes, for each standard memory, Information indicating whether or not the standard memory is to be subjected to pattern matching processing with the input audio pattern is stored, and based on the information, information indicating whether or not the standard memory is to be subjected to pattern matching processing with the input audio pattern is selected from the standard pattern memory. A pattern matching device characterized in that it is configured to be able to read only standard patterns.