JPS6255574A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction during the testing of a single integrated circuit, by a method wherein an output buffer circuit is kept at a high impedance while the internal circuit of the integrated circuit is in operation and waiting for the end of the operation, it is put to the normal output state by lagging time in each group to minimize the peak value of current flowing through a buffer section. CONSTITUTION:A disable signal to be applied to an internal terminal 1 gives '1' before a test data is inputted, and so 3-state output buffer circuit 100-400 are all at a high impedance (HZ) when a test data is inputted. There is no variation in the output during the operating of the internal circuit of an integrated circuit after the inputting of the test data and waiting for the end of operation, the circuits 100 alone are put to the normal output state from the HZ state, and then the circuit 200 is put to the normal output state at the timing delayed by a time determined by a resistance R1 and a capacitance C1. Thereafter, likewise, the output is varied by a delay time up to the circuits 400, thereby allowing the circuits to avoid the flowing of a large current there through at one time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a plurality of output buffer circuits.

"Prior Art" Conventionally, this type of semiconductor integrated circuit does not have a special means for controlling the operation of the output buffer circuit, and output signals are adjusted according to appropriate input signals during the operation of the semiconductor integrated circuit. It was about to come out.

[Problem that the invention seeks to solve]

Unit tests of semiconductor integrated circuits, such as non-defective product selection tests and characteristic evaluation tests, generally involve socket mounting, long lead wires, and are conducted under conditions worse than actual usage conditions. Furthermore, during testing, input signals are usually applied to all terminals at the same time, so simultaneous operation of a similar number of outputs, which is prohibited in actual use, often occurs. Therefore, when many output buffer circuits operate simultaneously, a very large amount of current flows, and due to poor mounting conditions, a large amount of noise is generated, and what should be a good product may be considered defective due to malfunction. be.

An object of the present invention is to provide a semiconductor integrated circuit that can prevent erroneous movements during testing.

[Means for solving problems]

The semiconductor integrated circuit of the present invention includes an internal circuit that outputs one or more signals, and a plurality of 3-state output covers whose inputs are connected to the outputs of the internal circuits.1. , a NOR circuit group, one or more external terminals that externally supply a disable signal to the three-state output buffer circuit, and each of the three-state output buffer circuit groups based on the disable signal applied to the external terminal. High impeda by shifting time [Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

The external terminal 1 is connected to the input of a buffer gate 10 on the input side of the signal distribution circuit 2, and the output of the buffer gate 10 is connected to the three-state output buffer circuits 101, 102 .・
..., is applied to the disable signal terminal of 10J, and is also applied to the input of 20 to buffer gate 1 through an integrating circuit consisting of resistor R8 and capacitor C3, and the outputs of buffer gates 1 to 20 are 3. It is applied to the disable signal terminals of the state output buffer circuits 201, 202, . The output is 3-stay I
Output buffer times i? 8301,302. ....

30L is applied to the disable signal terminal, and is also applied to the input of the buffer gate 40 through an integrating circuit consisting of a resistor R3 and a capacitor C3, and the output of the buffer gate 40 is applied to the 3-stage 1 to output cover circuit. 401
．． 402. ...Added to the 40M disable terminal. 100,200. ....

400 is a 3-state output buffer circuit group.

An output of an internal circuit (not shown) provided inside the integrated circuit is connected to each data input of the three-state output buffer circuit.

FIG. 2 is a signal waveform diagram for explaining the operation of the circuit of FIG. 1.

The disable signal applied to external terminal 1 is 1°' before the test data is input, and at the time the test data is input, all three-state output buffer circuits are in a high impedance state (hereinafter referred to as HZ). state). After the test data is input and sufficient time has elapsed for all the internal circuits of the integrated circuit to finish operating (timing T), external terminal 1 is set to “°1°” and the Hz
Solve the condition. As shown in the signal waveform diagram, timing T.

Until then, as the internal circuitry of the integrated circuit moves,
State output buffer circuits 101, 102°..., 4
The 0M input varies widely, and sometimes a large number of signals may vary in the same direction at the same time. At this time, if these 3-state output buffer circuits are not in the H2 state, the outputs of the 3-state output buffer circuits will all fluctuate in the same direction, causing a momentary large current to flow, causing large noise and malfunction. may occur. In this embodiment, all of these three-state output buffer circuits are in the H2 state until timing T1, so there is no fluctuation in the output.
At timing T, 3-state output cover sofa circuit group 10
0 from the H2 state to the normal output state and the primary resistor R1
The 3-state output buffer circuit group 200 is brought into the normal output state at timing T2 of i'& (set to approximately 10 nanoseconds), which is determined by the capacitance C1 and the capacitance C1. Similarly, 3
By allowing time to flow up to the state output sofa circuit group 400 and varying the C output, it is possible to avoid flowing a large current at one time.

In the above example, there is one external terminal 1 and a delay circuit is used as the signal distribution circuit 2.・You may also shift the position.

〔Effect of the invention〕

As explained above, the present invention enables the output cover/777 circuit to be set to H2 while the internal circuit of the integrated circuit is in operation during a unit test of an IC.
By leaving the output buffer circuit in the H2 state and waiting for the end of the operation, and then changing the time from the H2 state to the normal output state by shifting the time for each group, the peak of the current flowing in the output buffer section can be reduced. Since the value is kept small and the generation of noise is alleviated, it is effective in eliminating malfunctions during unit testing of integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the present invention, and FIG. 2 is a signal waveform diagram for explaining the operation of the circuit of FIG. 1. 1... External terminal, 2... Signal distribution circuit, 10.20
゜30.40...Buffer gate, 100. ...
, 400... 3-state output buffer circuit group, 101
゜102,...,40M...3-state output buffer circuit.

Claims (1)

[Claims] an internal circuit that outputs one or more signals, a plurality of 3-state output buffer circuit groups each having an output of the internal circuit connected to its input, and one that supplies a disable signal to the 3-state output buffer circuit from the outside. the above external terminal; and a signal distribution circuit that generates a set of disable signals that respectively shift the times and put the three-state output buffer circuit group into a high impedance state based on the disable signal applied to the external terminal. A semiconductor integrated circuit characterized by: