JPS6255568A - Inspection for short-circuit disconnection of multiple wiring - Google Patents

Inspection for short-circuit disconnection of multiple wiring

Info

Publication number
JPS6255568A
JPS6255568A JP60196315A JP19631585A JPS6255568A JP S6255568 A JPS6255568 A JP S6255568A JP 60196315 A JP60196315 A JP 60196315A JP 19631585 A JP19631585 A JP 19631585A JP S6255568 A JPS6255568 A JP S6255568A
Authority
JP
Japan
Prior art keywords
wiring
terminal
short
inspected
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60196315A
Other languages
Japanese (ja)
Inventor
Tsutae Shinoda
傳 篠田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60196315A priority Critical patent/JPS6255568A/en
Publication of JPS6255568A publication Critical patent/JPS6255568A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Abstract

PURPOSE:To achieve a higher reliability and higher working efficiency of inspection, by providing an input switch and an output switch from a power source on each of wiring to be inspected to scan the application of voltage connecting them sequentially. CONSTITUTION:Leader terminals Tn are connected to ends (A) of respective wiring of a wiring group to be inspected; power sources are connected in parallel to the respective terminals through input switch elements Sin, and so are current detection resistances (R) through output switches Son and simultaneously short-circuiting means 1 are provided at the ends (B) thereof in such a manner as to free to separate therefrom and approach them. A current source is supplied with the short-circuiting means 1 separating from the ends (B) through a switch elements Sin connected to a specified leader terminal Tn while a short-circuiting between adjacent wires is detected according to the presence of the detection of current when a switch element Son+1 is connected to an adjacent leader terminal. A power source current is supplied through a switch element Sin to a specified leader terminal Tn with the short-circuiting means 1 contacting the ends (B), and a disconnection of the wire linked to a specific terminal is detected depending on the presence of current flowing through at least one switch Sox connected to a remaining leader terminal.

Description

【発明の詳細な説明】 〔概 要〕 電子機器に用いられる多数高密度並行微細配線の各被検
査配線に電源からの入力スイッチと出力スイッチを設け
、それらを順次選択、接続しながら電圧印加の走査をお
こない、各配線の短絡断線を検出し、その走査ステップ
回数の計数により被検査端子を識別するような検査方法
を提供し、検査の信頼性と効率の向上をもたらすもので
ある。
[Detailed Description of the Invention] [Summary] An input switch and an output switch from a power supply are provided for each wiring to be inspected of a large number of high-density parallel fine wiring used in electronic equipment, and voltage is applied while sequentially selecting and connecting them. The present invention provides an inspection method that performs scanning, detects short circuits and disconnections in each wiring, and identifies terminals to be inspected by counting the number of scanning steps, thereby improving the reliability and efficiency of inspection.

〔産業上の利用分野〕[Industrial application field]

この発明は、電子機器に用いられる多数高密度並行微細
配線、なかでもディスプレイパネルのような数百ミクロ
ンの幅とピッチの膜配線の短絡断線を検出するための検
査方法に関する。
The present invention relates to an inspection method for detecting short-circuits and disconnections in a large number of high-density parallel fine interconnects used in electronic equipment, particularly in film interconnects with a width and pitch of several hundred microns, such as those in display panels.

この種微細配線は、部品の状態で短絡断線の検査が行わ
れるがパネル一枚当たり1000本におよぶ配線を、正
確に効率良く検査する方法の確立が要望されていた。
This type of fine wiring is inspected for shorts and breaks in the component state, but there has been a need to establish a method for accurately and efficiently inspecting up to 1,000 wirings per panel.

〔従来の技術〕[Conventional technology]

従来この種漱細配線の検査を行うには、八)顕微鏡によ
る目視検査、 B)被検査配線に電流を通じながら、電磁誘導コイルを
被検査配線に近接させて、該配線に直fluこ移動させ
ることにより該配線中の電流の有無を検出する、 などの方法がとられていた。
Conventionally, in order to inspect this kind of thin wiring, 8) Visual inspection using a microscope; B) Bringing an electromagnetic induction coil close to the wiring to be inspected and moving it directly to the wiring while passing a current through the wiring to be inspected. The following methods have been used to detect the presence or absence of current in the wiring.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、上記従来の方法の、 八)の目視検査では、幅100 ミクロン、長さ300
ミリメータ、1000本におよぶ膜配線を逐一検査する
ことは、検査作業者の熟練と緊張に依存するところあま
りにも大であって、検査の信頼性の低さと効率の悪さが
問題である。
However, in the visual inspection in step 8 of the above conventional method, the width is 100 microns and the length is 300 microns.
Inspecting 1,000 millimeter-sized membrane wirings one by one depends too much on the skill and tension of the inspection worker, which poses problems of low inspection reliability and efficiency.

B)の電流検出コイルを用いる方法は、断線の検査には
有効であるが、隣接した配線との短絡の検査には不十分
である。さらに、検出コイルが検査中の配線の番地を知
るための複雑な機構を必要とした。
Method B) using a current detection coil is effective for inspecting disconnections, but is insufficient for inspecting short circuits with adjacent wiring. Furthermore, a complicated mechanism was required for the detection coil to know the address of the wiring under test.

この発明は、このような問題を解決し、電子的に、また
自動的に、多数高密度並行微細配線の検査を行う方法を
提供し、その検査の信頼性と作業効率の向上を図るもの
である。
This invention solves these problems and provides a method for electronically and automatically inspecting a large number of high-density parallel fine interconnects, thereby improving the reliability and work efficiency of the inspection. be.

〔問題点を解決するための手段〕[Means for solving problems]

第1図に本発明の原理ブロック図を、第2図に第1図に
関連して被検査配線の端子を示す。
FIG. 1 shows a block diagram of the principle of the present invention, and FIG. 2 shows terminals of the wiring to be inspected in relation to FIG. 1.

被検査配線群の各配線、例えば第n番目の配′IaL7
に対し、該配線の一端、A端部にて、引き出し端子T7
を設は接触接続し、該端子を入力スイッチ素子S1を通
じ電源゛2に接続し、出力スイッチ素子S。7を通じ電
流検出抵抗Rに接続する。
Each wire in the group of wires to be inspected, for example, the n-th wiring IaL7
On the other hand, at one end of the wiring, the A end, the lead terminal T7
The terminals are connected to the power source 2 through the input switch element S1, and the output switch element S is connected to the power source 2 through the input switch element S1. Connect to the current detection resistor R through 7.

該電流検出抵抗Rの端子電圧と、同期信号発生回路3か
らの同期信号は良否判定回路4に入力される。
The terminal voltage of the current detection resistor R and the synchronization signal from the synchronization signal generation circuit 3 are input to a quality determination circuit 4.

配線間短絡の検査には、被検査配線L7のもう一方の端
、即ちB端部を開放し、°入力スイッチ素子Slnを閉
じ、隣接配線L n+ lに連なる出力スイッチ素子S
。□1を閉じ、電源2より電圧を端子1゛1を経て被検
査配線しnに印加する。この操作を、被検査配線群配列
の一端り、から、他の一端へ順次走査しながら繰り返し
おこなう。
To test for a short circuit between wires, open the other end of the wire to be tested L7, that is, the B end, close the input switch element Sln, and connect the output switch element S connected to the adjacent wire Ln+l.
. □1 is closed, and a voltage is applied from the power supply 2 to the wiring to be inspected via terminal 1'1 to n. This operation is repeated while sequentially scanning from one end of the wiring group array to be inspected to the other end.

配線断線の検査には、被検査配線の、上記短絡検査にて
開放した側の、B端部を接触端子群よりなる一斉短絡手
段1にて全部短絡し、n番目の配線に対する入力スイッ
チ素子S+r+を閉じ、n番目の配置り。に対する以外
の少なくとも一つの出力スイッチ素子S08を閉じ、電
源2から端子T、、を経て被検査配線し7に印加する。
To test for wire breakage, all the B ends of the wire to be tested on the side opened in the short circuit test are short-circuited by the simultaneous shorting means 1 consisting of a group of contact terminals, and the input switch element S+r+ for the nth wire is connected. Close and place nth. At least one output switch element S08 other than that for the voltage is closed, and a voltage is applied to the wiring from the power source 2 through the terminals T, .

また入力スイッチ素子群S、と出力スイッチ素子群S。Also, an input switch element group S and an output switch element group S.

それぞれに入力スイッチ走査回路5と、出力スイッチ走
査回路6を設け、上に述べた検査操作を、被検査配線群
配列の一端の!1aLlから、他の一端へ順次走査しな
がら繰り返しおこなう。
An input switch scanning circuit 5 and an output switch scanning circuit 6 are provided for each, and the above-mentioned inspection operation is performed on one end of the wiring group array to be inspected. This is repeated while sequentially scanning from 1aLl to the other end.

これら走査回路5.6は同期信号発生回路3からの1回
の同期信号により走査の1ステツプを進むよう構成され
、該同期信号発生回路はまた計数器7に接続される。
These scanning circuits 5 , 6 are configured to advance one step of scanning by one synchronizing signal from the synchronizing signal generating circuit 3 , which is also connected to the counter 7 .

良否判定回路4の出力は記憶装置8に入力され、さらに
該記憶装置には、記憶された検査結果の出力装置9とし
て、ディスプレイ装置9−1やプリンタ装置9−2が接
続される。
The output of the pass/fail judgment circuit 4 is input to a storage device 8, and a display device 9-1 and a printer device 9-2 are connected to the storage device as an output device 9 for the stored test results.

〔作 用〕[For production]

「問題点を解決するための手段」にて述べた結線を各検
査目的別に原理図と判定表にて説明する。
The wiring connections described in "Means for solving problems" will be explained using principle diagrams and judgment tables for each inspection purpose.

短絡検査の場合、第3図と第4図に接続と判定表を示す
。例えば被検査配線し7とその隣接配線L+、+1の間
には導通があってはならない。従って、第3図のような
スイッチ素子の接続状態、即ちSln+  Son++
が閉路、S OI’l+  S I++1が開路で電源
電圧が被検査配線し。に印加されると、これら隣接2線
間に短絡不良がある場合のみ、検出抵抗Rに印加電圧が
電流として流入し電圧降下(出力電圧)が発生し、短絡
不良が無ければ、電圧降下は発生しない。
In the case of short circuit inspection, connections and judgment tables are shown in Figures 3 and 4. For example, there must be no conduction between the wiring to be inspected 7 and its adjacent wirings L+ and +1. Therefore, the connection state of the switch elements as shown in FIG. 3, that is, Sln+Son++
is closed, S OI'l+ S I++1 is open, and the power supply voltage is on the wiring to be tested. When a short circuit occurs between these two adjacent wires, the applied voltage flows into the detection resistor R as a current and a voltage drop (output voltage) occurs.If there is no short circuit, a voltage drop occurs. do not.

断線検査の場合、第5図〜第6図に接続と判定表を示す
。例えば被検査配線しfiと単に戻り用として選ばれた
少なくとも1本以上の配線しXはその先端Bで一斉短絡
手段1により短絡されているので、これらには当然導通
がなければならない。
In the case of a disconnection test, connection and determination tables are shown in FIGS. 5 and 6. For example, the wiring fi to be inspected and at least one wiring X selected simply for return are short-circuited at their tips B by the simultaneous shorting means 1, so naturally there must be continuity between them.

従って、第5図のようなスイッチ素子の接続状態でパル
スが印加されると、被検査配線Ln或いば戻り線り、に
断線不良がない場合のみ、検出抵抗Rに印加電圧が電流
として流入し出力電圧が発生し、断線不良があれば、電
圧は発生しない。
Therefore, when a pulse is applied with the switch element connected as shown in Figure 5, the applied voltage will flow into the detection resistor R as a current only if there is no disconnection in the wiring Ln or the return line to be inspected. However, if there is an open circuit failure, no voltage will be generated.

戻り線LXの断線は複数の配線を用いることにより、そ
の確率は非常に低く、また該戻り線を被検査線として検
査することにより除去出来る。
The probability of disconnection in the return line LX is extremely low by using a plurality of wiring lines, and it can be eliminated by inspecting the return line as a line to be inspected.

このように接続条件と、検出抵抗Rに発生する出力電圧
の有無の組み合わせにより、第4図、第6図に示す判定
表に従い短絡、断線不良の有無を判定するよう良否判定
回路4を予めプログラムしておく。
In this way, the pass/fail judgment circuit 4 is programmed in advance to judge whether there is a short circuit or disconnection according to the judgment table shown in Figs. I'll keep it.

一方被検査配線群の配列の一端し+から、検査を開始し
、その第1番目の被検査配線り、に電圧の印加を指示し
た同期信号を第1番目として、順次隣接配線に電圧印加
の走査を行い、その走査のステップの回数、即ち同期信
号印加回数の計数結果が被検査配線の番地として使用さ
れる。
On the other hand, the test is started from one end of the array of wirings to be inspected, and the synchronization signal that instructs the application of voltage to the first wiring to be inspected is the first, and the voltage is applied to the adjacent wirings in sequence. Scanning is performed, and the result of counting the number of scanning steps, that is, the number of times the synchronizing signal is applied, is used as the address of the wiring to be inspected.

従って記憶装置8には各被検査配線の番地と検査結果が
関連づけられて記録される。
Therefore, the address of each wiring to be inspected and the inspection result are recorded in the storage device 8 in association with each other.

(実施例〕 第7図にこの発明の実施例を示す。(Example〕 FIG. 7 shows an embodiment of the invention.

入力スイッチ素子S1として、PNP型トランジスタが
用いられ、これは負のゲートパルスP1がコンデンサC
を経てベースに印加された期間導通する。また出力スイ
ッチ素子S。とじて、NPN型トランジスタが用いられ
、これは正のゲートパルスP2がコンデンサCを経てベ
ースに印加された期間導通ずる。図におけるゲートパル
スPI、Pgは配線り、とL n+ 1間の短絡検査を
おこなうためのものである。
A PNP transistor is used as the input switch element S1, and the negative gate pulse P1 is connected to the capacitor C.
conducts for the period applied to the base. Also, an output switch element S. As a result, an NPN type transistor is used, which conducts during the period when a positive gate pulse P2 is applied to the base via the capacitor C. The gate pulses PI and Pg in the figure are for testing a short circuit between wiring and L n+1.

同期信号発生回路3、計数器7、良否判定回路4、記憶
装置8は一体となった小型電子計算機Q(0であり、出
力装置9はディスプレイ装置9−1或いはプリンタ9−
2が用いられる。なお、2は電源である。    ゛ 入力スイッチ走査回路5、出力スイッチ走査回路6は検
査目的に応じ各々の走査開始位置が良否判定回路4から
指定され、同期信号1個を受は取る毎にゲートパルスP
IIP2を指定のトランジスタのベース回路に印加し、
更に次のトランジスタへ走査の1ステツプをすすめる。
The synchronizing signal generation circuit 3, the counter 7, the pass/fail determination circuit 4, and the storage device 8 are integrated into a small electronic computer Q (0), and the output device 9 is a display device 9-1 or a printer 9-
2 is used. Note that 2 is a power source.゛The input switch scanning circuit 5 and the output switch scanning circuit 6 each have their respective scanning start positions specified by the pass/fail judgment circuit 4 according to the inspection purpose, and each time they receive or receive one synchronization signal, a gate pulse P is generated.
Apply IIP2 to the base circuit of the specified transistor,
Further, one step of scanning is carried out to the next transistor.

第2図に示す引き出し端子Tおよび一斉短絡手段1は接
触端子の配列したコネクタであり、該一斉短絡手段はそ
の各端子が互いに接続されている。
The extraction terminal T and the simultaneous short-circuiting means 1 shown in FIG. 2 are connectors in which contact terminals are arranged, and the respective terminals of the simultaneous short-circuiting means are connected to each other.

なお、上記には典型的な回路例を示したが、一斉短絡手
段1には、コネクタでな(板状導電体を用いてもよ(、
或いはトランジスタなどの電子的スイッチを用いること
もできる。
Although a typical circuit example is shown above, the simultaneous shorting means 1 may be a connector (a plate-shaped conductor may also be used).
Alternatively, electronic switches such as transistors can also be used.

〔発明の効果〕〔Effect of the invention〕

この発明の検査法を用いることにより、多数配線の短絡
断線検査にP練作業者を必要とせず、短絡、断線ともに
、検査の正確さは100χに、また作業工数は1710
以下でかつ作業時間が1分弱に短縮され、電子機器の製
造コストの低減に極めて有用である。
By using the inspection method of this invention, there is no need for a P-trainer to inspect multiple wiring for shorts and breaks, the accuracy of inspection for both shorts and breaks is 100x, and the number of man-hours is 1710.
In addition, the working time is shortened to less than 1 minute, which is extremely useful for reducing manufacturing costs of electronic devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の原理ブロック図、。 第2図は被検査配線群とその端子との接続関係図、 第3図は短絡検査時の被検査配線の接続図、第4図は短
絡検査の判定表、 第5図は断線検査時の被検査配線の接続図、第6図は断
線検査の判定表、 第7図はこの発明の1実施例構成図である。 図において、 L、はn番目の被検査配線、 T7はn番目の引き出し端子、 SI、、はn番目の大カスインチ素子、So、、はn番
目の出カスインチ素子、Rは電流検出抵抗、 1は一斉短絡手段、 2は電源、 3は同期信゛号発生回路、 4は良否判定回路、 5は入カスイソチ走査回路、 6は出力スイソチ走査回路、 7は計f2I器、 8は記憶装置、 9は出力装置である。 第3図    第43 第5図    第6図
FIG. 1 is a block diagram of the principle of this invention. Figure 2 is a connection diagram of the wiring group to be inspected and its terminals, Figure 3 is a connection diagram of the wiring to be inspected during short-circuit inspection, Figure 4 is the judgment table for short-circuit inspection, and Figure 5 is during open-circuit inspection. A connection diagram of the wiring to be inspected, FIG. 6 is a determination table for disconnection inspection, and FIG. 7 is a configuration diagram of an embodiment of the present invention. In the figure, L is the nth wiring to be inspected, T7 is the nth lead-out terminal, SI, is the nth large scale inch element, So, is the nth output scale inch element, R is the current detection resistor, 1 2 is a simultaneous short circuit means, 2 is a power supply, 3 is a synchronization signal generation circuit, 4 is a pass/fail judgment circuit, 5 is an input switching circuit, 6 is an output switching circuit, 7 is a total f2I device, 8 is a storage device, 9 is the output device. Figure 3 Figure 43 Figure 5 Figure 6

Claims (3)

【特許請求の範囲】[Claims] (1)被検査配線群の各配線の一方の端部(A)に、配
線対応の引出し端子(Tn)を接続し、 該端子に入力スイッチ素子(S_1_n)を介して電源
と、出力スイッチ素子(S_0_n)を介して電流検出
抵抗(R)を並列接続し、 上記各配線の他方の端部(B)を共通に短絡する一斉短
絡手段(1)を該端部列に対して離接自在に設け、 上記短絡手段(1)を配線端部(B)から離した状態で
、特定の引出し端子(Tn)に連なる入力スイッチ素子
(S_1_n)を通じて電源電流を供給すると共に、隣
接した引出し端子に連なる出力スイッチ素子(S_0_
n_+_1)を閉じた時の電流検出の有無に応じて当該
隣接配線間の短絡を検出し、 また上記短絡手段(1)を端部(B)に接触せしめた状
態で、特定の引出し端子(Tn)に連なる入力スイッチ
素子(S_1_n)を通じて電源電流を供給すると共に
、残り引出し端子と連なる少なくとも一つの出力スイッ
チ(S_0_x)を通じて流れる電流の有無により、特
定端子に連なる配線の断線を検出するようにしたことを
特徴とする多数配線の短絡断線検査法。
(1) Connect the lead terminal (Tn) corresponding to the wiring to one end (A) of each wiring in the wiring group to be inspected, and connect the power supply to the terminal via the input switch element (S_1_n) and the output switch element. Current detection resistors (R) are connected in parallel via (S_0_n), and the simultaneous shorting means (1) that commonly shorts the other end (B) of each of the above wirings can be freely connected to and separated from the end row. With the shorting means (1) separated from the wiring end (B), supply current is supplied through the input switch element (S_1_n) connected to a specific lead-out terminal (Tn), and the supply current is supplied to the adjacent lead-out terminal. A series of output switch elements (S_0_
A short circuit between the adjacent wirings is detected depending on whether or not current is detected when the terminal (Tn_+_1) is closed. ) A power supply current is supplied through the input switch element (S_1_n) connected to the remaining lead terminal, and a break in the wiring connected to a specific terminal is detected based on the presence or absence of current flowing through at least one output switch (S_0_x) connected to the remaining extraction terminal. A short circuit/disconnection inspection method for multiple wiring lines.
(2)断線検査の際、一斉短絡手段(1)を出力スイッ
チ(S_1)と電流検出抵抗(R)との接続点に接続し
、被検査配線端子に連なる出力スイッチ(S_0_n)
を開放することを特徴とする特許請求範囲第(1)項記
載の多数配線の短絡断線検査法。
(2) When inspecting for disconnection, connect the short-circuiting means (1) to the connection point between the output switch (S_1) and the current detection resistor (R), and connect the output switch (S_0_n) connected to the wiring terminal to be inspected.
A method for inspecting multiple wirings for short circuits and disconnections as set forth in claim (1), characterized in that: .
(3)上記特定の被検査配線端子に係わる入力および出
力スイッチ素子を1同期信号パルス毎に順次走査してオ
ンオフする走査回路(5)、(6)と、該パルスの数を
計数する計数回路とを備え、該パルス計数回路の出力に
より当該被検査配線の番地を識別することを特徴とする
特許請求範囲第(1)項および第(2)項記載の多数配
線の短絡断線検査法。
(3) Scanning circuits (5) and (6) that sequentially scan and turn on and off the input and output switch elements related to the specific wiring terminal to be inspected for each synchronizing signal pulse, and a counting circuit that counts the number of pulses. A method for inspecting multiple wirings for short circuits and disconnections according to claims (1) and (2), characterized in that the address of the wiring to be inspected is identified by the output of the pulse counting circuit.
JP60196315A 1985-09-04 1985-09-04 Inspection for short-circuit disconnection of multiple wiring Pending JPS6255568A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60196315A JPS6255568A (en) 1985-09-04 1985-09-04 Inspection for short-circuit disconnection of multiple wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60196315A JPS6255568A (en) 1985-09-04 1985-09-04 Inspection for short-circuit disconnection of multiple wiring

Publications (1)

Publication Number Publication Date
JPS6255568A true JPS6255568A (en) 1987-03-11

Family

ID=16355766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60196315A Pending JPS6255568A (en) 1985-09-04 1985-09-04 Inspection for short-circuit disconnection of multiple wiring

Country Status (1)

Country Link
JP (1) JPS6255568A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02188187A (en) * 1989-01-11 1990-07-24 Jidosha Denki Kogyo Co Ltd Motor driver
JP2006008112A (en) * 2004-05-21 2006-01-12 Showa Denko Kk Steering support beam and instrument panel mounting structure
JP2008058481A (en) * 2006-08-30 2008-03-13 Brother Ind Ltd Image forming apparatus and disconnection inspection method therefor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02188187A (en) * 1989-01-11 1990-07-24 Jidosha Denki Kogyo Co Ltd Motor driver
JP2006008112A (en) * 2004-05-21 2006-01-12 Showa Denko Kk Steering support beam and instrument panel mounting structure
JP2008058481A (en) * 2006-08-30 2008-03-13 Brother Ind Ltd Image forming apparatus and disconnection inspection method therefor

Similar Documents

Publication Publication Date Title
CN1186643C (en) Method and apparatus for testing signal paths between integrated circuit wafer and wafer tester
JP2664429B2 (en) Circuit board inspection apparatus and method
JPH04309875A (en) In-circuit tester
KR920010309A (en) LCD panel array inspection method and device
JP3151203B2 (en) Integrated circuit self-inspection equipment
US5747999A (en) Feed control element used in substrate inspection and method and apparatus for inspecting substrates
JP2008203077A (en) Circuit inspection device and method
KR100496861B1 (en) Test apparatus having two test boards to one handler and the test method
EP0773445A2 (en) Inspection apparatus of conductive patterns
US4922184A (en) Apparatus and process for the simultaneous continuity sensing of multiple circuits
JPS6255568A (en) Inspection for short-circuit disconnection of multiple wiring
CA1156722A (en) Electrical short locator
JP3163265B2 (en) Inspection apparatus and inspection method for flat cable and multilayer board
WO2007138831A1 (en) Board examination method and board examination device
US4038598A (en) Probe contact and junction detector
US20020145434A1 (en) Interconnect package cluster probe short removal apparatus and method
JP3227697B2 (en) Circuit board inspection method and apparatus
JP2903686B2 (en) Inspection method of LED panel
JPH05264633A (en) Continuity testing circuit for test board wiring
JPS6371669A (en) Inspecting method for electronic circuit device
JPH0421106Y2 (en)
JP2003255007A (en) Method and apparatus for verifying circuit wiring
CN111999626A (en) Configurable I-V characteristic testing device and testing method thereof for semiconductor device
JPH01182763A (en) Checking of continuity for substrate having circuit
JPS62182677A (en) Detection of defective insertion of integrated circuit into socket