JPS6254899A - Programmable read only memory and its writing method - Google Patents

Abstract

PURPOSE:To prevent insulation breakage of the capacitor of an unwritten memory cell by so constituting the titled method that the level of a word line is made '0', a node is made floating by turning OFF a transistor, the potential of the node is raised by means of capacitive coupling in order not to impress a high voltage to a capacitor. CONSTITUTION:Respective word lines WL are made of level '1' during the front half of each cycle of write period and all of the nodes A of respective memory cells are connected to the grounding line GND making them of low level '0'. In the same duration, respective bit lines BL also are made of level '0'. After initializing the word line WL of a memory cell desired to be written is made of level '1' as well as its bit line WL. Consequently, a high voltage is impressed to the capacitor of the memory cell to be written, causing a breakage in the insulating film that constitutes the capacitor C and the flowing of current. At this time, the word line WL of memory cell not written are made '0'. Therefore, even if the bit line BL is '1', because the node A is floating, the level of the node A rises close to the level of the bit line BL because of the capacitive coupling, preventing any large potential difference in the capacitor C from occurring.

Description

[Detailed Description of the Invention] [Summary] BIC-PROM (Breakdown of In
5ulator for Cond-uction-P
rogramable Read 0nly Memo
ry (hereinafter abbreviated as BIC-ROM), a high voltage is applied to the capacitor of the non-written memory cell, which causes dielectric breakdown and prevents damage. For this purpose, the electrode connected to the transistor on the opposite side of the electrode connected to the bit line to which a high voltage is applied is made floating by controlling the level of the word line and turning off the transistor. Protect the capacitor by raising the potential and preventing high voltage from being applied to the capacitor.

[Industrial application field]

The present invention relates to a BIC-ROMO write method that can protect non-write memory cells with a minimum circuit configuration.

BIC-ROM is a ROM that performs writing by applying a high voltage to the capacitors that make up the memory cells to cause dielectric breakdown and make them conductive.The writing time is short, only a few microseconds, and it is suitable for various information devices. It has come to be used.

In BIC-ROM, in order to protect non-write memory cells connected to the selected bit line during writing,
It is necessary to devise a writing method and writing circuit.

[Conventional technology]

Since the structure of the BIC-ROM is a new structure proposed by the applicant, a new writing method is also required.

If writing is performed only by a combination of high and low levels, as in conventional fuse ROMs, the diodes or transistors that make up the memory cells will be destroyed, and the dielectric breakdown of the capacitors of non-written memory cells will occur. Since such cases may occur, it is necessary to devise ways to prevent these situations.

[Problem that the invention seeks to solve]

When writing to a BIC-ROMO, complicating the circuit configuration or adding a power supply to protect non-written memory cells reduces the degree of integration of the memory device and increases power consumption. become.

[Means for solving problems]

The solution to the above problem is to use a transistor (Q) whose gate is connected to the word line (ridge), one electrode connected to the bit line (hole), and the other electrode connected to the ground via the transistor (Q). A memory cell consisting of a capacitor (C) connected to (GND) is connected to each word line (WL) and each bit line (BL).
), and when writing by selecting a predetermined memory cell and dielectrically breaking down the capacitor (C), each word line is (WL) is set to a high level, and each pin line (BL) is set to a low level, and the other electrode (the electrode opposite to the electrode connected to the bit line) of the capacitor (C) of all memory cells is set to a high level. Initialize the selected memory cell by grounding it, and set the word line (ridge) and bit line (BL) connected to the selected memory cell to a low level in the second half of the cycle, write to the memory cell, and write to the non-programmed memory cell. A peripheral circuit including a write circuit (14) that protects the insulating layer of the capacitor (C) by setting the word line (WL) connected to the low level to turn off the transistor (Q). A programmable read-only memory according to the present invention and a transistor (
fl), one electrode is connected to the bit line (ILL), and the other electrode is connected to the ground line (GND) via the transistor (Q).
) and a capacitor (C) connected between each word line (WL) and each bit line (BL). When writing by dielectrically breaking down the capacitor (C), controlling the level of the word line (WL) connected to the non-writing memory cell to turn off the transistor (Q) of the non-writing memory cell. This is achieved by the I programmable read-only memory write method according to the present invention, which uses capacitive coupling of the capacitor (C) to protect non-write memory cells from destruction.

[Effect]

FIG. 1 (1) shows a BIC-ROM that explains the present invention in detail.
FIG. 2 is an equivalent circuit diagram of a cell.

In the figure, the tag is a word line, BL is a bit line, q is a transistor, C is a capacitor, GND is a ground line, and node 8 is a connection point between transistor Q and capacitor C.

At the time of writing, the selected bit line becomes "1", and the node A (, [1,!l) of the capacitor C of the non-written memory cell connected to this bit line is pulled up, and the potential of the capacitor C becomes high. No voltage is applied to prevent dielectric breakdown of the capacitor C of the non-written memory cell.

To this end, the present invention sets the level of the word line to "0" and turns off the transistor Q, thereby making the node A floating and raising the potential to the node through capacitive coupling to prevent high voltage from being applied to the capacitor C. protection.

〔Example〕

For the sake of simplicity, an example of a BIC-ROM having the following configuration will now be described.

Figure 1 (2) shows a BIC-ROM with a (2x3) bit configuration.
FIG. 2 is a schematic diagram of a cell array.

In the figure, (1,1), (1,2), (2,1),
(2,2), (3,1).

(3, 2) is a memory cell, the first number represents the word line to be connected, and the second number represents the number of the bit line to be connected.

The equivalent circuit of each memory cell is the same as that shown in FIG. 1(1).

1. Oath L2 Urashi 3 is word line, BLI, BL2
．． BL3 is a bit line.

The same number of ground lines GND are provided in parallel to the word lines.

FIG. 1(3) is a block diagram showing the configuration of a BIC-ROM according to the present invention.

In the figure, 11 is a cell array of BIC-ROM.

The peripheral circuits include a row (rotv) decoder 12 connected to the word line hole and a column (co) connected to the bit vABL.
lumn) decoder 13, successive output/write (R/+4) circuit 14, and address register 15.

Row decoder 12, column decoder 13, R/W circuit 1
4 is a peripheral circuit including a write circuit of the present invention.

Address register 15 receives address signals from bus 16 to perform program control, and sends its output to row decoder 13 and column decoder 14.

The R/- circuit 14 is connected to the column line of the cell array 11 and exchanges data with the bus 16.

Next, the BIC with the (2×3) bit configuration in Figure 1 (2)
- The ROM writing method according to the present invention will be explained according to a timing diagram.

FIG. 2 is a timing diagram of the write method according to the present invention.

The figure shows the timing when writing to memory cells (1, 1) and (2, 2).

In the figure, (1) is a clock indicating the write cycle.

The basic operation is as follows.

(1) During the first half of each cycle of the initialization write cycle, each word line ML
is set to "1", all nodes A of each memory cell are short-circuited to the ground line GND, and set to a low level "0". Also, during this period, each bit line BL is also set to "0".

(2) After the write initialization is completed, the word line hole of the memory cell to be written is set to 1", and the bit line BL is also set to "1".

As a result of the above, a high voltage is applied to the capacitor C of the memory cell to be written, and the insulating film that constitutes the capacitor C is torn.
Conduct.

For memory cells that are not written at this time, the word iW
Let L be “0”. Therefore, even if the bit line BL is "1", since the node A is floating, the level of the node Δ rises to near the level of the bit line BL due to capacitive coupling.Therefore, the capacitor C has dielectric breakdown. There is no potential difference that would cause this.

By adopting the above method, writing to BrC-ROM can be performed.

FIG. 3 is a circuit diagram showing an example of a write circuit used in the present invention.

In the figure, Q2 and Q5 are n-channel depletion type transistors, old 0, Qll, Ql3, Q17 to Q19 are p-channel enhancement type transistors, Ql,
Q3, ro4, 06, 07, Q8, ro9, Ql2
, Q14 to Q16 are n-channel enhancement type transistors, and Q3 to lower are high voltage transistors.

The power supply uses two voltage levels: +25V and +5V.
Each is distinguished by the symbol shown in the diagram.

T is write data to FROM, and φ is a clock used during writing. The write circuit is controlled by R/W and R/W.
Do it at a traffic light.

When writing, by setting R/W to "1" and R/W to "0", Ql5 is turned on, old 9 is turned off, and Ql5 is turned on and old 9 is turned off.
8 is off and QIO is on.

When φ is "1", a logic level in phase with T is output from the signal line connected to the column decoder.

In the above state, when the bottom is "0", Ql is turned on and Q6 is turned off, so that the GND level is output to the signal line.

When the bottom is "1", Ql is turned off and Q6 is turned on, so +25V is output to the signal line.

When φ is "0", Ql is turned on and Q6 is turned off, so that the GND level is output to the signal line.

When +25V is supplied to the signal line and the transistor of the memory cell is turned on, dielectric breakdown of the capacitor C occurs and writing is performed.

When reading, by setting R/W to "0" and R/W to "1", Ql5 is turned off, Ql9 is turned on, Q8 is turned on, and QIO is turned off.

At this time, since Q6 and Ql are both turned off, the signal line of the column decoder is in a high impedance state. Here, the data can be read by the successive circuit connected to the signal line.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the circuit configuration,
It is possible to protect non-written memory cells of a BIC-ROM from dielectric breakdown without adding a power source (by using capacitive coupling by capacitors forming memory cells).

[Brief explanation of drawings]

FIGS. 1 (1), (2), and (3) are equivalent circuit diagrams of a BIC-ROM cell explaining the present invention in detail, and (2X
3) A schematic diagram of a memory cell of a BIC-ROM with a bit configuration, a block diagram showing the configuration of a BIC-ROM according to the present invention, FIG. 2 is a timing diagram of a write method according to the present invention, and FIG.
The figure is a circuit diagram showing an example of a write circuit used in the present invention. In the figure, 11 is a memory cell array, 12 is a row decoder, 13 is a column decoder, 14 is an R/- circuit, 15 is an address register, 16 is a bus, ML, WLI, ML2. Rei 3 is word line, BL, BLL
, BL2. BL3 is a bit line, Q is a transistor, C is a capacitor, GND is a ground line, A is a connection point between transistor Q and capacitor C, (1, 1
), (1,2), (2,1), (2,2), (3,1)
, (3,2) is the memory cell (2) (2X3 hit)p+door"1oBlc-R
OI'1 阜1 圀(3) Tree call rgB/C-ROIV1 Kaya 1 Kanfu 2 匡Goramde'Goku゛〒 +25V T+5V Suibakumei/f) Turn to the left 3rd listen

Claims (2)

[Claims] (1) A transistor (Q) whose gate is connected to the word line (WL), one electrode connected to the bit line (BL), and the other electrode connected to the ground line (GN) via the transistor (Q).
Selecting a memory cell array (11) consisting of a capacitor (C) connected to D) and a memory cell connected between each word line (WL) and each bit line (BL), and a predetermined memory cell. , when writing by dielectrically breaking down the capacitor (C), the charge of the capacitor (C) of all memory cells is set to 0 during the first half of the write cycle, and the selected memory is set to 0 during the second half of the write cycle. A programmable read-only memory characterized by having a peripheral circuit including a write circuit (14) that turns on a transistor (Q) of a cell and turns off a transistor (Q) of an unselected memory cell. (2) A transistor (Q) whose gate is connected to the word line (WL), one electrode connected to the bit line (BL), and the other electrode connected to the ground line (GN) via the transistor (Q).
Select a predetermined memory cell of a memory cell array (11) formed by connecting a memory cell consisting of a capacitor (C) connected to D) between each word line (WL) and each bit line (BL), When writing by breaking down the capacitor (C), the level of the word line (WL) connected to the non-writing memory cell is controlled to turn off the transistor (Q) of the non-writing memory cell. A method for writing in a programmable read-only memory, characterized in that the capacitive coupling of the capacitor (C) is used to protect non-writing memory cells from destruction.