JP2006338766A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize simultaneous writing of multibits in an OTP memory. <P>SOLUTION: A wordline control circuit WS is arranged, and a clock signal CLK is applied to the gate of a cell transistor connected to respective wordlines in common. In a period when the clock signal CLK is at a low level, the central transistor is off, so that no current flows through any memory cells including a memory cell related with an insulation breakdown capacitor. Thus, even when the high voltage value of a common power voltage VCC is lowered temporarily by first writing to be equal to or lower than a writable voltage, the common power voltage VCC and a data line DL are raised to the writable voltage in the period when the clock signal CLK is at a low level. Then, the clock signal CLK is changed from the low level to a high level after obtaining sufficient current supplying ability by restoration of the common power voltage VCC and the data line DL, so that writing to residual memory cells is carried out to the residual memory cells. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a writing technique for a one-time programmable (OTP) memory element.

    In recent years, electronic tags used for non-contact type individual recognition (for example, logistics management using RFID tags, entrance / exit management, checkout management, etc.) have become widespread. RFID (Radio Frequency Identification) is a mechanism for identifying and managing people and things with a minute electronic tag. It is not limited to product identification and management technology that replaces barcodes, and promotes the use of IT and automation in society. Attention is growing as a fundamental technology in Japan.

  From the viewpoint of reducing the chip size as much as possible and reducing the manufacturing cost, a one-time programmable memory (referred to as an OTP memory) is suitable as a memory used for an electronic tag or the like. As its name suggests, the OTP memory is used without erasing data or further programming after the first write. In addition, since the stored information cannot be transformed, the OTP memory is rarely used as a product by itself, but as a means for executing an auxiliary function in a semiconductor device as well as an electronic tag, Demand is increasing.

  FIG. 3 is a circuit diagram of an OTP memory according to a conventional example. In the OTP memory, one set of cell transistors T1, T2 and capacitors C1, C2 constitute one cell (Cell1, Cell2) of the OTP memory.

The word lines WLL and WLR are electrically connected to the gates of the cell transistors T1 and T2, respectively. The drains of the cell transistors T1 and T2 are connected to the first electrodes of the capacitors C1 and C2, respectively, and the voltages at these connection points are VL and VR, respectively.
Parasitic capacitances CP1 and CP2 exist at the drains of the cell transistors T1 and T2 (first electrodes of the capacitors C1 and C2). The parasitic capacitors CP1 and CP2 are mainly PN junction capacitors.

  The sources of the cell transistors T1 and T2 are grounded via the ground line GNDL, and the second electrodes of the capacitors C1 and C2 are electrically connected to the data line DL common to the two cells. A write voltage or a read voltage is supplied to the data line DL from the voltage supply circuit VS. At the time of data reading, the voltage of the data line DL is output to the outside through the output buffer BF.

  Next, write and read operations for storing the digital data “1” or “0” in the OTP memory (see FIG. 3) will be described with reference to FIGS. 4 (a) and 4 (b). FIG. 4A shows changes in potentials of the data lines DL, VL, VR, the word line WLL, and the word line WLR during the data write operation. FIG. 4B shows changes in potentials of the data lines DL and VL, the word line WLL, and the word line WLR during the data read operation.

  First, a case where digital data “1” is written to the cell transistor T1 will be described. First, a predetermined write voltage is applied to the data line DL (for example, 11V). Here, the predetermined write voltage refers to a high voltage that can break down the capacitors C1 and C2. Next, the potential of the word line WLL connected to the cell transistor T1 changes from a low level (L) to a predetermined high level (H). Then, the cell transistor T1 is turned on.

  At this time, since the cell transistor T1 is turned on by the high level potential (H) of the word line WLL, the drain of the cell transistor T1 becomes the ground potential. Therefore, a predetermined write voltage applied to the data line DL is concentrated and applied to the capacitor existing between the data line DL and the drain, that is, the capacitor C1. As a result, the capacitor C1 is broken down, and the drain of the cell transistor T1 and the data line DL corresponding thereto are electrically connected. Hereinafter, the cell transistor T1 in which the data line DL and the drain are connected by the dielectric breakdown is referred to as a cell transistor in the storage state “1”.

  On the other hand, the cell transistor T2 is connected to the data line DL. However, if the cell transistor T2 remains in the OFF state, the capacitor C2 is not broken down, and the digital data “1” is written to the cell transistor T2. Not.

  Even when the cell transistor T1 is in the on state and a write voltage for applying dielectric breakdown to the capacitor C1 is applied from the data line DL, if the cell transistor T2 is in the off state, the capacitor C2 is not broken down.

  Next, a case where digital data “0” is written to the cell transistor T1 will be described. When writing the digital data “0”, no specific writing operation is required. For example, when it is desired to set the memory state of the cell transistor T1 to “0”, it is not necessary to apply a write voltage that can break down the capacitor C1 to the corresponding data line DL.

  Further, the cell transistors T1 and T2 may be turned off by setting the potentials of the word lines WLL and WLR to a low level (L). In the off state, the drains of the cell transistors T1 and T2 do not become the ground potential (GND), and a predetermined write voltage applied to the data line DL is not applied to the capacitors C1 and C2 in a concentrated manner. It is. Hereinafter, a cell transistor in which the data line DL and the drain are insulated without destroying the capacitor is referred to as a cell transistor in the storage state “0”.

  Next, an operation of reading “1” or “0” digital data from the above-described OTP memory cell will be described with reference to FIG. Here, first, an operation of reading digital data from the cell transistor T1 in the storage state “1” will be described.

  In this case, the potential of the word line WLL electrically connected to the gate of the cell transistor T1 is changed from the low level (L) to the high level (H). Here, the data line DL is initially set to a predetermined precharge potential (for example, power supply potential Vdd = 3 V) in advance by the voltage supply circuit VS.

  When the potential of the word line WLL becomes high level (H), the cell transistor T1 is turned on. In the state where “1” is written as described above, since the capacitor C1 is broken down, the drain of the cell transistor T1 and the corresponding data line DL are electrically connected to each other. Then, the ground potential (GND) of the ground line GNDL is output to the data line DL through the cell transistor T1.

  For this reason, as shown in FIG. 4B, the potential of the data line DL changes from the precharge potential (for example, Vdd = 3 V) to the inverted voltage of the output buffer BF or less. At this time, the potential of the data line DL is output as digital data “1” from the data line DL to the outside of the OTP memory through the output buffer BF.

  Next, an operation of reading digital data from the cell transistor T1 in the storage state “0” will be described with reference to FIG. In this case, the potential of the word line WLL connected to the cell transistor T1 is changed from the low level (L) to the high level (H). Here, the data line DL is initially set to a predetermined precharge potential (for example, power supply potential Vdd = 3 V) in advance by the voltage supply circuit VS.

  When the potential of the word line WLL becomes high level (H), the cell transistor T1 is turned on. In the state where “0” is written as described above, the capacitor C1 is not dielectrically broken, so that the drain of the cell transistor T1 and the corresponding data line DL are not electrically connected. Then, as shown in FIG. 4B, the potential of the data line DL remains the precharge potential (for example, Vdd = 3V). At this time, the precharge potential of the data line DL is output as digital data “0” from the data line DL to the outside of the OTP memory through the output buffer BF.

  As described above, either “1” or “0” is selected based on whether or not the capacitor is broken down by applying a predetermined write voltage (high voltage, for example, 11 volts) from the corresponding data line DL. Data is written into the OTP memory cell and the data is read out.

  As shown in FIG. 5, the actual OTP memory is configured so that multi-bit data can be written simultaneously. For example, the OTP memory includes four memory blocks MB0 to MB3. In the memory blocks MB0 to MB3, a plurality of OTP memory cells including cell transistors TnL and TnR (n is an integer of 0 or more) and capacitors CLn and CRn as described in FIG. 3 are arranged. These OTP memory cells are connected to common data lines DL0 to DL3.

  The word lines WLnL and WLnR are commonly connected to the gates of the corresponding cell transistors TnL and TnR of the memory blocks MB0 to MB3. For example, the word line WL1L is commonly connected to a total of four cell transistors T1L arranged in each of the memory blocks MB0 to MB3.

  Further, 4-bit data signals (φD0, φD1, φD2, and φD3) are input to the CMOS inverters INV provided in the memory blocks MB0 to MB3, respectively. A common power supply voltage VCC is supplied to the CMOS inverter INV via a resistor R. The outputs of these CMOS inverters INV are supplied to the data lines DL0 to DL3, respectively. In FIG. 5, the parasitic capacitance CP shown in FIG. 3 is not shown.

The following patent documents are listed as technical documents related to the present invention.
JP 2004-193606 A JP 2004-356931 A

  However, when multi-bit data is simultaneously written using the above-described OTP memory cell (see FIG. 5), there is a problem that data is not written in some memory cells. This will be described with reference to the circuit diagram of FIG. 5 and the timing chart of FIG.

  For example, consider a case where a 4-bit data signal ((φD0, φD1, φD2, φD3) = (0, 0, 0, 0)) is simultaneously written into four cell transistors T1L commonly connected to the word line WL1L.

  When a 4-bit data signal (0, 0, 0, 0) is written, a current of about 1.6 mA flows as a current that can cause dielectric breakdown of the capacitors CL1 arranged in the memory blocks MB0 to MB3. Therefore, when 4-bit data is written simultaneously, a large current of about 6.4 mA flows through the data lines DL0 to DL3. As a result, all four capacitors CL1 are ideally broken down at the same time.

  However, during the write operation, the common power supply voltage VCC is a high voltage (for example, 11 V) generated by an RF (Radio Frequency) carrier wave or a charge pump circuit, but a large current that flows when each capacitor CL1 is dielectrically broken down. As a result, the common power supply voltage VCC decreases (see FIG. 6A).

  For this reason, the write voltage also decreases, some capacitors CL1 are not electrostatically damaged, and there is a case where such memory cells cannot be written. For example, consider a case where the capacitor CL1 associated with the memory blocks MB0 and MB2 is broken down and the capacitor CL1 associated with the memory blocks MB1 and MB3 is not broken down.

  In this case, since the drains of the cell transistors T1L of the memory blocks MB0 and MB2 and the corresponding data lines DL0 and DL2 are electrically connected, the potentials of the data lines DL0 and DL2 are lowered (in FIG. 6B). (See solid line). However, since the capacitor CL1 of the memory blocks MB1 and MB3 is not broken down, the drains of the cell transistors T1L of the memory blocks MB1 and MB3 and the corresponding data lines DL1 and DL3 are not electrically connected, and the data lines DL1 and DL3 are not electrically connected. The potential of DL3 does not fall completely (see the broken line in FIG. 6B). If the potential does not drop completely, data writing has failed.

  The memory cell that has undergone dielectric breakdown has a resistance of about 1 kΩ and a current of about 0.2 mA flows. For this reason, once the write operation is performed, the common power supply voltage VCC will not recover to a high voltage value thereafter, and even if it recovers more than the writable voltage, the recovery speed is slow, so sufficient current supply capability is generated The remaining capacitors that were not broken down could not be broken down within a predetermined write time (for example, within 5 ms).

  As described above, it is difficult for the conventional OTP memory to simultaneously write a large amount (for example, 4 bits or more) of bit data at the same time. To write data, a powerful common power supply, a charge pump circuit and the like are required.

  The present invention has been made in view of the above problems, and its main features are as follows. That is, a nonvolatile semiconductor memory device according to the present invention includes a plurality of memory blocks, and each memory block includes a memory cell formed by connecting a capacitor and a cell transistor in series, a data line connected to the capacitor, A data write circuit that supplies a common power supply voltage and supplies a write voltage to the data line in accordance with a data signal so as to insulate the capacitor, and is common to the gates of the cell transistors of the plurality of memory blocks And a word line control circuit for supplying a clock signal to the word line in accordance with a word line selection signal.

  The word line selection circuit includes a clock generation circuit that generates the clock signal, and an AND circuit that receives the clock signal and the word line selection signal.

  Furthermore, the clock generation circuit is a CR oscillation circuit.

  In the OTP memory according to the present invention, the pulse clock signal (WL-CLK) is applied to the gates of the cell transistors commonly connected to each word line by the word line control circuit WS. Then, during the period when the clock signal (WL-CLK) is at the low level, current is prevented from flowing through all the memory cells including the memory cell related to the capacitor whose dielectric breakdown has already occurred.

  For this reason, even if the high voltage value of the common power supply voltage VCC once decreases at the first writing and becomes equal to or lower than the writable voltage, the common power supply voltage VCC and the data line DL are in the period when the clock signal (WL-CLK) is at the low level. Raised to a writable voltage. Then, after the common power supply voltage VCC and the data line DL are restored to a writable voltage or more and have sufficient current supply capability, the clock signal (WL-CLK) is changed from the low level to the high level, thereby remaining memory cells. Write about.

  As described above, according to the present invention, even if a relatively small common power source has a large amount of simultaneously written bit data and does not have a current supply capability for simultaneously writing all the bits, writing can be performed using the word line control circuit. By controlling the operation and writing in several times, writing of all bits can be reliably performed substantially simultaneously.

  In addition, since a powerful charge pump or the like for increasing the current supply capability is not required, the OTP memory can be reduced in size and cost can be reduced. The electronic tag including the OTP memory cell of the present invention and other semiconductors incorporating the same Product manufacturing costs can be kept low.

  Next, embodiments of the present invention will be described with reference to the drawings. Note that the same symbol is used for the same configuration as that of the conventional OTP memory (see FIGS. 3, 4 and 5) already described. Since the data read operation is the same as that of the conventional OTP memory described above (see FIG. 4B), the description thereof is omitted.

  As shown in FIG. 1, the present embodiment is configured so that 8-bit data can be written simultaneously, and consists of eight memory blocks MB0 to MB7. In each of the memory blocks MB0 to MB7, a plurality of OTP memory cells formed by serially connecting cell transistors TnL and TnR (n is an integer of 0 or more) and capacitors CLn and CRn as described above are arranged. These OTP memory cells are connected to common data lines DL0 to DL7.

  The word lines WLnL and WLnR are commonly connected to the gates of the corresponding cell transistors TnL and TnR of the memory blocks MB0 to MB7. For example, the word line WL1L is commonly connected to a total of eight cell transistors T1L arranged in each of the memory blocks MB0 to MB7.

  Each word line WLnL, WLnR is controlled by a word line control circuit WS.

  Data signals φD0 to φD7 are input to CMOS inverters INV provided in the memory blocks MB0 to MB3. The CMOS inverter INV is formed by connecting in series a P-channel MOS transistor whose source is connected to the common power supply voltage VCC and an N-channel MOS transistor whose source is connected to the ground line.

  A common power supply voltage VCC is supplied to the CMOS inverter INV via a resistor R. The outputs of these CMOS inverters INV are supplied to the data lines DL0 to DL7, respectively.

  As described above, the CMOS inverter INV in this embodiment serves as a data write circuit that supplies a predetermined write voltage to the data lines DL0 to DL7 in accordance with the data signal φD. When a low level data signal φD (φD = 0) is input, the P-channel MOS transistor of the CMOS inverter INV is turned on, and the common power supply voltage VCC and the data line DL are connected. On the contrary, when the high level (H) data signal φD (φD = 1) is input, the P-channel MOS transistor of the CMOS inverter INV is turned off, and the common power supply voltage VCC and the data line DL are not connected.

  Note that the common power supply voltage VCC, the resistor R, and the CMOS inverter INV in this embodiment generally have a role similar to that of the voltage supply circuit VS (see FIG. 3), and the common power supply voltage VCC is used during the write operation. Is a predetermined high voltage (for example, 11V), and is a predetermined precharge potential (for example, 3V) in the read operation. In FIG. 5, the parasitic capacitance CP shown in FIG. 3 is not shown.

  A difference from the conventional OTP memory is that the potential of the word lines WLnL and WLnR (n is an integer of 0 or more) is controlled based on the clock signal CLK using the word line control circuit WS.

  The word line control circuit WS includes, for example, an AND circuit 10 having a first input terminal and a second input terminal, the output terminals of which are connected to the corresponding word lines WLnL and WLnR. Although not shown, the word lines including the word line selection signal generating circuit for generating the word line selection signal φwj (j = 1 to n) which is a signal for selecting the cell transistors TnL and TnR for performing the data write operation are included. The control circuit WS may be used.

  A clock signal CLK for controlling a data write operation and a charge period (recovery period) of the common power supply voltage VCC by the clock generation circuit CS is input to the first input terminal of the AND circuit 10, and a word line is input to the second input terminal. A selection signal φwj is input. Then, a clock signal (WL-CLK) is input from the output terminal of the AND circuit 10 to the gates of the cell transistors TnL and TnR as an output signal of the word line control circuit WS. Note that the clock signal (WL-CLK) is in phase with the clock signal CLK when the word line control signal φwj is at a high level, that is, during a data write operation.

  The clock signal CLK is output from a known CR oscillation circuit or other clock generation circuit CS used in a microcomputer or the like. The clock signal CLK is controlled by the clock generation circuit CS so that the low level period is, for example, 100 μs.

  Next, a write operation for storing “1” or “0” digital data in the OTP memory (see FIG. 1) according to the present invention will be described with reference to FIGS. FIG. 2 shows changes in potentials of the common power supply voltage VCC, the data lines DL0 to DL7, the clock signal CLK (= WL-CLK), and the word line selection signal φwj during the data write operation.

  An 8-bit data signal ((φD0, φD1, φD2, φD3, φD4, φD5, φD6, φD7) = (0, 0, 0, 0, 0, 0) is simultaneously applied to the eight cell transistors T1L connected to the word line WL1L. , 0, 0)), that is, the case of writing “1” digital data. First, since both the clock signal CLK and the word line selection signal φwj are at the low level, all the cell transistors T1 are in the off state. The common power supply voltage VCC is a high voltage of about 11 V due to the RF carrier wave (not shown) and the boosting of the charge pump circuit.

  Next, low level data signals φD0 to φD7 (= 0) are input to the CMOS inverters INV of all the memory blocks MB0 to MB7. Then, since the P-channel MOS transistor of each CMOS inverter INV is turned on, the data lines DL0 to DL7 rise to a predetermined write voltage (= VCC) as shown in FIG.

  Next, the clock signal CLK and the word line selection signal φwj change from a low level (L) to a predetermined high level (H). Note that the word line selection signal φwj is maintained at a high level during the writing period (see FIG. 2D). Therefore, during the writing period, a high level (H) clock signal (WL-CLK) is input to the word line WL1L from the word line control circuit WS, and the cell transistors of the memory blocks MB0 to MB7 are turned on.

  Then, since the cell transistor T1L is on, the drain of the cell transistor T1L becomes the ground potential. A predetermined write voltage (about 11 volts) applied to the data lines DL0 to DL7 is a capacitance existing between the data lines DL0 to DL7 and the drain of each cell transistor T1L, that is, a lower electrode (first electrode) of the capacitor. The electrode is concentrated and applied between the upper electrode (second electrode) and the upper electrode (second electrode).

  As a result, if not all of the capacitors CL1 of some memory blocks MB (for example, MB0 to MB4) are broken down, the drain of the cell transistor T1L and the corresponding data lines DL (DL0 to DL4) are electrically connected. Connected to. Then, the potential of the data line DL (DL0 to DL4) drops sharply (see the broken line 20 in FIG. 2B), and the digital data “1” (for 5 bits) is supplied to the cell transistor T1L of the memory block MB (MB0 to MB4). Data) is written. This writing operation is referred to as first writing for convenience. Here, the potential of the data lines DL (DL5 to DL7) does not drop and data is not written to the memory blocks MB (MB5 to MB7) (see the solid line 30 in FIG. 2B).

  Next, the clock signal CLK changes from the high level (H) to the low level (L) (see FIG. 2C). Then, since the low level (L) clock signal (WL-CLK) is input from the word line control circuit WS to each gate of the cell transistor T1L, all the cell transistors T1L commonly connected to the word line WL1L are turned off. .

  During a period when the clock signal CLK is at a low level (for example, about 100 μs), since the cell transistor T1L is off, a current is supplied to all the memory cells including the memory cell related to the capacitor that has already been broken down by the first writing. Not flowing. Then, the common power supply voltage VCC and the data lines DL0 to DL7 are restored to the writable voltage during the period when the clock signal CLK is at the low level (see FIG. 2A). In the present embodiment, the period during which the clock signal CLK is at a low level is controlled to be about 100 μs. However, the period is not particularly limited as long as the common power supply voltage VCC is sufficient to recover to a writable voltage.

  Next, the clock signal CLK changes from the low level (L) to the high level (H). Then, since the high level clock signal (WL-CLK) is input from the word line control circuit WS to the gates of all the cell transistors T1L, the cell transistors T1L are turned on. Since the common power supply voltage VCC and the data lines DL0 to DL7 have recovered to the writable voltage, the capacitor CL1 of the memory block MB (MB5, MB6, MB7) that has not been broken down in the first writing is broken down. Thus, the potential of the data line DL (DL5 to DL7) drops sharply (see the broken line 21 in FIG. 2B), and the digital data “1” (for 3 bits) is supplied to the cell transistor T1L of the memory block MB (MB5 to MB7). Data) is written. This writing operation is referred to as second writing for convenience.

  Since the capacitor for 5 bits is broken down in the first writing, the broken capacitor becomes a resistance of about 1 kΩ in the second writing, and a current of about 0.2 mA flows. Therefore, at the time of the second writing, about 5.8 mA (current flowing through the dielectric breakdown capacitor about 1 mA (0.2 mA × 5) + about 4.8 mA (when the remaining three bits of the capacitor are broken down) If the common power supply VCC has the current supply capability of the current flowing through the capacitor, the capacitor for 3 bits is broken down in the second write, and a total of 8 bits of data is written together with the first write. .

If all bits of data are not written in the first and second writing, the clock signals CLK may be changed in a pulse manner to write the third, fourth,...
Since data is written only once in the OTP memory, it is important that data is reliably written. According to the present invention, even with a small common power source that has a large amount of bit data for simultaneous writing and does not have a current supply capability for simultaneously writing all the bits, the write operation is controlled using the word line control circuit. By performing the writing separately, all the bits are written substantially at the same time and reliably, which is suitable for the OTP memory.

  The OTP memory according to the present embodiment is composed of eight memory blocks MB0 to MB7 so that 8-bit data can be written at the same time. However, the present invention is not limited to this, and the number of memory blocks and the number of memory blocks can be simultaneously determined. The number of bit data to be written can be appropriately selected as necessary.

1 is a circuit diagram illustrating a nonvolatile semiconductor device of the present invention. It is a figure explaining operation | movement of the non-volatile semiconductor device of this invention. It is the schematic explaining the conventional non-volatile semiconductor device. It is a figure explaining operation | movement of the conventional non-volatile semiconductor device. It is a circuit diagram explaining the conventional non-volatile semiconductor device. It is a figure explaining operation | movement of the conventional non-volatile semiconductor device.

Explanation of symbols

CLn, CRn, C1, C2 capacitors
T1, T2, TnL, TnR Cell transistors CP1, CP2 Parasitic capacitances WLL, WLR, WLnL, WLnR Word line
VCC common power supply φD data signal WL-CLK clock signal CLK clock signal φw word line selection signal DL data line GNDL ground line MB memory block BF output buffer VS voltage supply circuit CS clock generation circuit R resistor INV inverter VCC common power supply 10 AND circuit 20 , 21 Data line potential when capacitor is broken down 30 Data line potential when capacitor is not broken down

Claims (5)

With multiple memory blocks,
Each memory block includes a memory cell formed by connecting a capacitor and a cell transistor in series,
A data line connected to the capacitor;
A data write circuit that is supplied with a common power supply voltage and supplies a write voltage to the data line in accordance with a data signal so as to insulate the capacitor.
A word line commonly connected to the gates of the cell transistors of the plurality of memory blocks;
A nonvolatile semiconductor memory device comprising: a word line control circuit that supplies a clock signal to the word line in response to a word line selection signal. The nonvolatile semiconductor memory device according to claim 1, wherein the data write circuit includes a CMOS inverter to which the data signal is input. 2. The nonvolatile semiconductor device according to claim 1, wherein the word line control circuit includes a clock generation circuit that generates the clock signal, and an AND circuit that receives the clock signal and the word line selection signal. Storage device. 4. The nonvolatile semiconductor memory device according to claim 3, wherein the clock generation circuit is a CR oscillation circuit. The nonvolatile semiconductor memory device according to claim 1, wherein the cell transistor is grounded.

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