JPS6254869A - Information recording disc and its recorder - Google Patents

Abstract

PURPOSE:To reproduce the second information exactly corresponding to the first one by making plural blocks of the second information correspondent during a period of integer multiple of a period of the first synchronous signal, and recording the end information the same in clock as the 2nd information which does not include the 2nd synchronous signal in the rest period of integer multiple of period of the 1st synchronous signal. CONSTITUTION:An inputted video information is frequency-modulated by an FM modulator 1 and then is outputted to a mixing circuit 2. Meanwhile a controller 3 detects the vertical synchronizing signal (a) of the video signal and outputs a signal corresponding to the vertical synchronizing signal to a buffer memory 4. The buffer memory 4, after the detection signal of the vertical synchronizing signal is outputted from the controller 3, serially outputs the digital data signals (b) and (c) already inputted and stored (delayed) to a selector 5 at the timing of the clock that arrives immediately after the outputting of the said detection signal. Of the signal (b), its prescribed length of A, B, and C are made to be the unit of correction, the prescribed number of units of correction constitute one data block.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information recording disk such as a video disk on which a television video signal is recorded, and a recording device thereof.

[Summary of the invention]

The present invention multiplexes and records first information classified for each first synchronization signal and second information classified for each second synchronization signal that is not synchronized with the first synchronization signal. In this case, an integral number of sections of the second information are made to correspond to periods that are an integral multiple of the period of the first synchronizing signal, and during the remaining period of the period that is an integral multiple of the period of the first synchronizing signal, The third information, which does not include the second synchronization signal and has the same clock as the second information, is recorded, so that the second information corresponds to the first information.
This allows the information to be reproduced accurately.

[Conventional technology]

Recently, disks that record information at high density have been developed and commercialized. Typical examples are video discs and digital audio discs.

There are several types of methods, but in the case of optical video discs, the television video signal has a sync chip level of 7.6 MHz and a white level of 9.3 MHz.
By frequency modulating the carrier wave of 8.1M1 (z), and by frequency modulating the carrier wave of 2.3MHz and 2.8MHz, the accompanying audio signals such as left and right stereo signals and bilingual signals Each is recorded.

On the other hand, PC in optical digital audio disc
The spectrum of the EFM signal of the M-converted left and right stereo audio signals occupies a band of approximately 2 MHz or less. Since the band below 2 MHz is almost empty on a video disc, such an EFM signal can be frequency division multiplexed and recorded on the video disc.

[Problem that the invention seeks to solve]

By the way, it is conceivable to record a digital data signal instead of an audio signal as such an EFM signal. Since digital data signals, unlike audio signals, are not necessarily continuous signals, it may be advantageous to have a block structure. However, the clock frequency of the EFM signal is approximately 44.1kHz.

The frequency of the vertical synchronization signal is 29.97 Hz, and there is no simple multiple relationship between the two, making it difficult to select the position of each data block and its length.

[Means for solving problems]

FIG. 1 is a block diagram of the recording device of the present invention, and FIG. 2 is a block diagram of the reproducing device. In FIG. 1, reference numeral 1 denotes an FM modulator that frequency-modulates an input video signal, and its output is supplied to a mixing circuit 2. A controller 3 detects a vertical synchronization signal from an input video signal and outputs a signal with a timing synchronized with the vertical synchronization signal to the buffer memory 4 and the selector 5. A digital data signal is input to the buffer memory 4, delayed by a predetermined time, and output to the selector 5. A scrambler 6 scrambles an input predetermined signal, for example a blank signal consisting of all O's, and outputs the scrambled signal to the selector 5. The output of the selector 5 is input to the encoder 7, and the encoded signal is supplied to the mixing circuit 2.

On the other hand, in FIG. 2, reference numeral 11 denotes a video disk as an information recording disk, which is rotated by a motor 12. As shown in FIG.

13 is a pickup that irradiates light onto the video disk 11 and reproduces information from the reflected light; its RF output is amplified by an amplifier circuit 14 and supplied to bandpass filters 15 and 17; The RF video signal separated by the bandpass filter 15 is supplied to a demodulation circuit 16 and demodulated. The digital data signal separated by the bandpass filter 17 is input to a clock extraction circuit 16 to extract its clock component, and is also supplied to a decoder 19 to be decoded based on the clock. . The decoded digital data signal is input to a sync detection circuit 2o, and a sync (synchronization signal) is detected. Further, the digital data signal is input to the latch circuit 21 and is latched based on the sync.

[Effect]

The effect will now be explained. First, in the recording apparatus, an input video signal is frequency-modulated by an FM modulator 1 and then output to a mixing circuit 2. On the other hand, the controller 3 receives the vertical synchronization signal of the video signal (Fig. 4(a)).
is detected, and a signal corresponding to the vertical synchronization signal is output to the buffer memory 4. The buffer memory 4 operates at a predetermined clock timing that arrives immediately after the vertical synchronization signal detection signal is output from the controller 3.
The digital data signals (FIG. 4(b) and (c)) that have been input and stored (delayed) up to that point are serially output to the selector 5.

On the other hand, the selector 5 is supplied with a blank signal scrambled by a scrambler 6.

For example, as shown in FIG. 3, the scrambler 6 includes a 15-bit shift register 31 and its 14th and 15th bits.
An exclusive OR circuit 32 outputs the exclusive OR of the outputs of the bits to the first bit, and an exclusive OR circuit 33 outputs the exclusive OR of the 15th bit of the shift register 31 and the input signal. It is configured. When the initial state of this shift register 31 is set so that the 1st to 14th bits are 0 and the 15th bit is 1, the scramble signal output from the 15th bit to the exclusive OR circuit 33 is , 1 at the first clock, 0 at the next second to 15th clock, 1 at the 16th clock, 0 from the 17th clock to the 29th clock, 3
If the exclusive OR circuit 33 calculates the exclusive OR of a blank signal in which all bits are 0 and this scramble signal becomes 1 when the clock is 0 (the same applies hereafter), the result is the same as the scramble signal. A signal is output.

The selector 5 adds the signal supplied from the scrambler 6 to the digital data signal supplied from the buffer memory 4 and outputs the resultant as parallel data. The amount (length) to be added is determined in accordance with the control signal from the controller 3 so that an integral number of data blocks correspond to a period that is an integral multiple of the period of the vertical synchronization signal.

In other words, the digital data signal as shown in FIG. 4(b) is as shown in FIG. 4(Cc) with a portion enlarged.
A predetermined length (indicated by A, B, C, etc. in the figure) is used as a unit of correction, and a predetermined amount of the units of correction are collected to form one data block. Therefore, for example, as shown in FIG. 4(d), one data block (DBl, DB
When the buffer memory 4 finishes sending out one data block, the controller 3 detects this and subsequently outputs a scrambled blank signal (the shaded area in the figure). The selector 5 is controlled to add . At the beginning of a data block of a digital data signal, for example, as shown in FIG. 5, a 96-bit sink is located where the first and last 8 bits are 0 and the intervening 80 bits are 1. There is.

However, as described above, since the vertical synchronization signal of the video signal and the sync (or clock) of the digital data signal are not synchronized, each data block DB1. DB2. Beginning of DB3 etc. (sink)
The position of is not necessarily constant (the maximum error is one clock).

Therefore, the length of the added signal is also not constant, but the digital data signal and the signal added to it are made to have the same clock. In other words, both clocks have the same frequency and are continuous in phase.

Of course, a blank signal may be added so that two data blocks correspond to one TV frame, as shown in FIG. 4(e), or a blank signal may be added so that two data blocks correspond to one TV frame, or as shown in FIG. It is also possible for seven data blocks to correspond to a frame (6 television fields).

Note that FIGS. 4(d), (e), and (f) are schematic representations of only data extracted from each correction unit of the digital data signal.

The encoder 7 adds a correction code to the parallel digital data signal supplied from the selector 5 or performs interleaving to perform predetermined encoding, and then outputs the signal to the mixing circuit 2 . Therefore, the frequency modulated video signal and the digital data signal are mixed in the mixing circuit 2 and output. This output signal is recorded on the video disc 11.

Next, the regeneration effect will be explained. Pickup 13 is
A video disc 11 rotated by a motor 12 is irradiated with laser light, and recorded information is reproduced from the reflected light. The reproduced RF signal is amplified by the amplifier circuit 14 and output to bandpass filters 15 and 17. Bandpass filter 1
5 extracts the video RF signal. This signal is transmitted to the demodulation circuit 1
6, the frequency is demodulated by C.
It is output to RT etc.

The digital data signal components separated by the bandpass filter 17 are output to a clock extraction circuit 18 and a decoder 19. Clock extraction circuit 18 extracts a clock component and supplies it to decoder 19. Since the clock signal is extracted continuously not only during the data block period but also during the blank signal period, there is no grace period for synchronizing the PLL circuit (not shown) etc. included in the clock extraction circuit 18 with the clock. It is not necessary except at the beginning of playback.

The decoder 19 performs necessary decoding such as error correction and deinterleaving in response to the clock, and outputs the result to the sync detection circuit 20 and latch circuit 21 . Sink detection circuit 2
0 outputs the detection signal to the latch circuit 21 when detecting the sync located at the beginning of each data block. A blank signal originally does not have a sync, but if there is a dropout or the like, a pattern identical to a sync may occur. However, since the blank signal is scrambled, the probability that a pattern identical to the sync pattern will occur due to an error or the like is very low, so the sync detection circuit 20 can accurately detect the sync of each data block. The latch circuit 21 latches and outputs data that arrives after the sync detection signal.

Note that blank data itself has a fixed pattern, so if it is not scrambled, it is likely to generate DC components or certain low frequency components, but scrambling prevents such situations from occurring. There is.

When reproducing still images from the video disc 11, the pickup 13 performs a jump back operation in units of cycles of the vertical synchronization signal. For example, when a video signal of one frame per revolution is being recorded, the pickup 13 repeats one track jump back at or near the position of the vertical synchronization signal for each revolution. Even in this case,
An integral number of data blocks are associated with a period that is an integral multiple of the period of the vertical synchronization signal, and a blank signal of the same clock is recorded in the remaining period, so the data blocks can be reliably reproduced. Is possible.

In the above, when a digital data signal whose data part has already been scrambled is input to the buffer memory 4 during recording, the remaining blank part is scrambled to make the signal as shown in FIG. Although the case where the signal is input to the encoder 7 has been described, if the data part of the signal input to the buffer memory 4 is not scrambled, it can be configured as shown in FIG. 6, for example. That is, the controller 3 causes the generator 4
1 and is reset to make its output logic O at the time of sync read, and generates a scramble signal at other times. Then, by using an exclusive OR circuit as the mixing circuit 42 and taking the exclusive OR of the output of the buffer memory 4 and the output of the generator 41, the buffer memory 4
The empty signal is output to the encoder 7 with its sync intact and the other parts scrambled, as shown in FIG.

〔effect〕

As described above, the present invention multiplexes the first information classified for each first synchronization signal and the second information classified for each second synchronization signal that is not synchronized with the first synchronization signal. In the case where an integral number of periods of the first synchronization signal are recorded, an integral number of sections of the second information are made to correspond to periods that are an integral multiple of the period of the first synchronization signal, and the remaining periods of the integral multiple of the period of the first synchronization signal are During the period, the second
Since the third information, which does not include a synchronization signal and has the same clock as the second information, is recorded, the second information can be reliably reproduced in correspondence with the first information.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the recording device of the present invention, FIG. 2 is a block diagram of the playback device, FIG. 3 is a block diagram of the scrambler, FIG. 4 is a timing chart during recording and playback, and FIG. FIG. 6 is a sync waveform diagram, FIG. 6 is a block diagram of a recording device of another embodiment, and FIG. 7 is a conceptual diagram of the digital data signal. 1... FM modulator 2... Mixing circuit 3, controller 4... Buffer memory 5... Selector 6...
Scrambler 7...Encoder 11...Video disc 12...Motor 13...Pickup 14...Amplification circuit 15.17...Band pass filter 16...Demodulation circuit 18...Clock extraction Circuit 19... Decoder 20... Sink detection circuit 21... Latch circuit 31... Shift register or higher

Claims (3)

[Claims] (1) Multiplexing and recording of first information classified for each first synchronization signal and second information classified for each second synchronization signal that is not synchronized with the first synchronization signal In the information recording disc, the second synchronization signal is transmitted during a period that is an integral multiple of the period of the first synchronization signal.
A clock that is the same as the second information, which corresponds to an integral number of the divisions of the information, and does not include the second synchronization signal in the remaining period of a period that is an integral multiple of the period of the first synchronization signal. the third
An information recording disc characterized by recording information of. (2) Multiplexing and recording of first information classified for each first synchronization signal and second information classified for each second synchronization signal that is not synchronized with the first synchronization signal. A recording device that detects the first synchronization signal and records an integral number of the divisions of the second information in correspondence during a cycle that is an integral multiple of the cycle of the first synchronization signal, and detecting the end of recording of the second information, and detecting that the second synchronization signal is not included in the remaining period of a period that is an integral multiple of the period of the first synchronization signal;
A recording device that records third information having the same clock as the information. (3) The recording device according to claim 2, wherein the third information is scrambled and recorded.