JPS6253868U - - Google Patents
Info
- Publication number
- JPS6253868U JPS6253868U JP14492085U JP14492085U JPS6253868U JP S6253868 U JPS6253868 U JP S6253868U JP 14492085 U JP14492085 U JP 14492085U JP 14492085 U JP14492085 U JP 14492085U JP S6253868 U JPS6253868 U JP S6253868U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- pulse
- resistor
- lush
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims 3
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 238000000926 separation method Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Studio Circuits (AREA)
- Color Television Systems (AREA)
Description
第１図は本考案の実施例に係る映像信号処理回
路の要部を示した回路図、第２図は第１図に示し
た回路の動作説明図、第３図は本考案及び従来回
路に共通するブロツク図、第４図及び第５図は従
来回路に含まれるワイパ回路の構成を示した回路
図である。
１……同期分離回路、２……Ｙ／Ｃ分離回路、
３……制御信号発生回路、４，４′……ワイパ回
路、５……インターフエイス、６……ＲＧＢ混合
エンコーダ回路、４１……単安定マルチバイブレ
ータ回路、４２，４２′……タイミング回路。
Fig. 1 is a circuit diagram showing the main parts of a video signal processing circuit according to an embodiment of the present invention, Fig. 2 is an explanatory diagram of the operation of the circuit shown in Fig. 1, and Fig. 3 is a circuit diagram showing the main parts of a video signal processing circuit according to an embodiment of the present invention. The common block diagrams, FIGS. 4 and 5, are circuit diagrams showing the configuration of a wiper circuit included in the conventional circuit. 1... Synchronization separation circuit, 2... Y/C separation circuit,
3... Control signal generation circuit, 4, 4'... Wiper circuit, 5... Interface, 6... RGB mixed encoder circuit, 41... Monostable multivibrator circuit, 42, 42'... Timing circuit.
Claims (1)
一パルスと、外部ＲＧＢ信号との論理積を取り、
かつ、前記単一パルスのパルス幅を可変すること
によつて、ブラウン管画面上の任意の領域に映像
を重ね合わせて表示させるワイパ機能を備えた映
像信号処理回路であつて、 前記単一パルスは、前記走査信号に同期した入
力パルス信号を与えられるＴＴＬ構成の単安定マ
ルチバイブレータ回路から出力され、また、この
単安定マルチバイブレータ回路は出力パルスのパ
ルス幅を可変するためのタイミング回路が付設さ
けており、このタイミング回路は、可変抵抗、耐
ラツシユ用抵抗及び第１のコンデンサと、前記耐
ラツシユ用抵抗に並列接続される第２のコンデン
サとを含み、かつ、前記第２のコンデンサは、こ
の単安定マルチバイブレータ回路への入力パルス
信号の周波数に対して、前記タイミング回路のイ
ンピーダンスが小さくなるように設定されたもの
であることを特徴とする映像信号処理回路。[Claim for Utility Model Registration] A single pulse emitted at a timing related to a scanning signal is ANDed with an external RGB signal,
and a video signal processing circuit equipped with a wiper function that displays an image superimposed on an arbitrary area on a cathode ray tube screen by varying the pulse width of the single pulse, wherein the single pulse is , is output from a TTL-configured monostable multivibrator circuit which is given an input pulse signal synchronized with the scanning signal, and this monostable multivibrator circuit is equipped with a timing circuit for varying the pulse width of the output pulse. The timing circuit includes a variable resistor, a anti-lush resistor, a first capacitor, and a second capacitor connected in parallel to the anti-lush resistor, and the second capacitor is connected in parallel to the anti-lush resistor. A video signal processing circuit characterized in that the impedance of the timing circuit is set to be small with respect to the frequency of the input pulse signal to the stable multivibrator circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985144920U JPH0731647Y2 (en) | 1985-09-20 | 1985-09-20 | Video signal processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985144920U JPH0731647Y2 (en) | 1985-09-20 | 1985-09-20 | Video signal processing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6253868U true JPS6253868U (en) | 1987-04-03 |
| JPH0731647Y2 JPH0731647Y2 (en) | 1995-07-19 |
Family
ID=31055975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985144920U Expired - Lifetime JPH0731647Y2 (en) | 1985-09-20 | 1985-09-20 | Video signal processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0731647Y2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4962027A (en) * | 1972-09-11 | 1974-06-15 | ||
| JPS53142120A (en) * | 1977-05-18 | 1978-12-11 | Tokyo Hoso:Kk | Special effect signal generator |
| JPS5742268A (en) * | 1980-08-28 | 1982-03-09 | Toshiba Corp | Horizontal synchronizing phase variable circuit |
-
1985
- 1985-09-20 JP JP1985144920U patent/JPH0731647Y2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4962027A (en) * | 1972-09-11 | 1974-06-15 | ||
| JPS53142120A (en) * | 1977-05-18 | 1978-12-11 | Tokyo Hoso:Kk | Special effect signal generator |
| JPS5742268A (en) * | 1980-08-28 | 1982-03-09 | Toshiba Corp | Horizontal synchronizing phase variable circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0731647Y2 (en) | 1995-07-19 |
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