JPS6252907B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a multi-computer system in which a plurality of computers control a plurality of input/output devices connected to a common bus. The present invention relates to a system for controlling the configuration of multiple control stations.

Here, "configuration control" means that among multiple control stations connected to a common bus, only one control station is always the master station and performs overall management of the common bus, and if the master station fails, the control station is immediately This means that one of the remaining standby control stations (monitor stations) replaces the previous master station and controls the control station to perform overall management of the common bus.

Here, "overall management" refers to all control or management related to the use of the common bus, and the computer
In a system that occupies a common bus and controls specific input/output devices, controlling the occupancy of the common bus is a major task.

Below, the control station that performs overall management is the master CST, and when the master CST malfunctions,
The control station that can act as a master CST instead of this is called a monitor CST, and the other control stations are called idle CSTs.

[Prior art]

One form of the common bus is a loop-shaped transmission path.

In recent years, proposals have been made in which loop-shaped transmission lines are multiplexed to improve the reliability of the transmission lines themselves. In addition, multiple CSTs are connected to a loop-shaped transmission line, and any one is designated as a master CST, and the rest are designated as monitor CSTs or idle CSTs. By controlling the configuration of CSTs, even if a specific CST goes down, the loop-shaped transmission line The system connected to the transmission line is
I'm trying to keep the system from going down.

Conventionally, CSTs were connected to a common bus independently of computers, and each CST independently determined the master CST and monitor CST.

In other words, the monitor CST determines whether the master CST has failed by monitoring the signals on the common bus, and if it determines that the master CST has failed,
The own CST is designated as the master CST and performs overall management of the common bus. In this case, the monitor
If there are two or more CSTs, which monitor
In many cases, it is decided in advance whether a CST will become the master CST, but this is complicated to manage, and two
One monitor CST may attempt to become the master CST.

Further, even if there is no failure in the master CST itself, if the signal on the common bus is interrupted, the monitor CST may assume that the master CST has failed and attempt to become the master CST itself.

Conventionally, attempts have been made to prevent such inconveniences by providing a special signal line between CSTs and exchanging signals, but the control becomes complicated and it is difficult to ensure a reliable CST configuration. Control was difficult.

[Purpose of the invention]

The purpose of the present invention is to make only one of the plurality of CSTs on a common bus the master CST, and to
An object of the present invention is to provide a control station configuration control method in a multi-computer system that reliably controls a CST to become a monitor CST or an idle CST.

[Summary of the invention]

A feature of the present invention is that each CST is connected in correspondence with multiple computers that control input/output devices connected to a common bus, and the master CST is made into a monitor CST by a command from the corresponding computer. Each CST reports its own status and the status of the signals on the common bus to the corresponding computer. Information on which CST is the master CST is stored in a common memory commonly used by each computer. Store and update each calculator with the corresponding
Configuration control is performed by referring to the configuration control information of the common memory based on reports from CST and instructions from other computers, and the configuration of the common memory is controlled when the computer starts and stops operation. The configuration of the CST is controlled by referring to the control information. According to the present invention, since configuration control information is managed in one common memory, two or more CSTs will not become master CSTs by mistake.

When a computer connected to the master CST receives a failure report from the master CST, it refers to the configuration control information in the common memory and recognizes that the CST connected to itself has become the master CST. and immediately set this to idle CST
and report to other computers that the CST is down.

The computer that receives this report refers to the configuration control information in the common memory, and if the CST connected to itself is a monitor CST, it rewrites this to the master CST and makes the CST connected to itself the master CST. issue an order to do so.

In addition, when a computer operates, it refers to the configuration control information of the common memory, and if the common bus connected to the computer does not have a master control station that centrally manages the common bus, the computer Outputs a command to the connected control station to become the master control station.

Furthermore, when a computer stops, it refers to the configuration control information in the common memory, and only if the control station connected to the computer in question is the master, will it be able to control other computers that are connected to that computer. Outputs a command so that the control station becomes the master.

In this way, the configuration control of CST is performed by referring to the configuration control information in the common memory used by each computer, both when the computer is running and when it is stopped, so configuration control is reliable. becomes.

[Embodiments of the invention]

FIG. 1 shows an embodiment of a multi-computer system to which the present invention is applied.

In Figure 1, 1 to 3 are calculators (hereinafter referred to as
It has a built-in program and controls a plurality of input/output devices 16 to 18 by executing this program.

4 is a common memory commonly used by each CPU 1 to 3, and as described later, CST
configuration control information is stored.

5 to 7 are stations (hereinafter referred to as ST) that connect the CPUs 1 to 3 to a common bus, here the loop-shaped transmission lines 11 and 12 in opposite directions;
is a control station (CST) having an integrated control function for the loop-shaped transmission lines 11 and 12. CST8-10 are connecting wires 80 and 9 respectively
It is connected to the corresponding CPUs 1, 2, and 3 via 0 and 100. 13 to 15 connect input/output devices (hereinafter referred to as I/O) 16 to 18 to a loop-shaped transmission line 1
1 and 12 (hereinafter referred to as μST). 19 is each CPU 1, 2, 3
This common connection line 19 connects the computers, and as will be described later, commands to other computers are output via this common connection line 19. Each μST 13 to 15 has a configuration and a CST that stores which CPU's request the I/O connected under itself should service.
It has a function to loop back based on the command from. The request from which CPU should be serviced is stored when the μST receives an exclusive request from the CPU in a state where the CPU to be serviced has not been determined (this state is called a neutral state). , this occupation state is the occupied state
It is released when an exclusive release command is received from the CPU, or when an exclusive release command is forcibly received from another non-occupied CPU. This occupancy request command is CONC/RSV (Connect&Reserve) command, and the release command of occupancy status is CONC/FREE.
(Connect&Free) command, RESET/FREE (Reset&Free) command to forcibly release occupation
It is called a command. When a command is sent from the CPU to the I/O connected under μST, if the command is from a source other than the CPU that occupies the I/O, unless it is a RESET/FREE command, , will not accept the command. By providing this mechanism, the loop bus can be
I/O connected via ST is multiple CPU
be properly shared from. That is, even if an input/output request is erroneously issued from the user program of CPU 2 to the I/O 16 occupied by the CPU 1, the processing of the I/O 16 that is currently being serviced will not be disrupted.

This is because input/output requests from CPU 2 are rejected by μST.

Each CPU manages the I/O connection state, and a table for managing the I/O connection state is stored in the memory of each CPU. When the operating system (OS) of each CPU needs to switch the I/O occupation state, the operating system (OS) of the CPU that is currently occupying the I/O
Contact the I/O and request them to issue a CONC・FREE command to the I/O. received a request
The CPU issues a CONC.FREE command to the I/O, releases the occupancy, and returns a response to the requesting CPU indicating that the occupancy has been released. After receiving this response, the requesting CPU issues the CONC/RSV command and occupies the I/O. When it is detected that the CPU currently occupying the I/O is stopped or not operating normally, the requesting CPU
After issuing the RESET/FREE command to release the occupied state of the I/O, issue the CONC/RSV command to occupy the I/O. The management table within each CPU is rewritten according to the transition of these I/O occupancies, but this management table may be placed in the inter-CPU shared memory 4.

Multiple CSTs are connected to the same loop to increase system reliability. If there is one CST, then
Not only can a CST malfunction, but if an abnormality occurs in the stations on both sides of the CST, control information will no longer be transmitted from the CST to the other stations, and the loop will no longer function. If these multiple CSTs control independent loops, mutually contradictory control may occur, so one of the multiple CSTs may
Give only one person permission to control the loop. A CST that has been given this authority is called a Master mode CST (master CST). Other CSTs are in a mode that monitors the state of the loop (Monitor mode) or is in a mode that simply operates passively (Idle mode).
mode), and a CST in Monitor mode is called a monitor CST. master
Only CST can command MST and ST to loop back, and normal CPU and I/O
a loop 11 used for data transmission, and a loop 12 used for transmitting loop monitoring signals, etc.
Commands such as switching can be given. The master CST sends a supervisory signal to the loop.

The monitor CST monitors the monitoring signal sent from the master CST, and when this monitoring signal cannot be detected for a certain period of time, it determines that the master CST has failed, and issues an interrupt to the CPU to detect an abnormality in the master CST. report. When the master CST detects a loop signal disconnection, it attempts to switch the duplicated loops (switch between loop 11 and loop 12). If the operation can be continued, it is fine, but if it is not possible to continue, the operation will be performed based on the loop configuration information stored in the own CST (indicating which stations are connected in what mutual relationship and topology). Instruct each station to perform loopback operation. The loop configuration information is sent from the CPU when the CST is commanded to become the master.
It is forwarded to the CST, but it may be forwarded to each CST in advance before being commanded to become a master. Even if the master CST tries this kind of loop control, the signal is still disconnected.
, and when the monitor CST detects its own abnormality, the master CST
Interrupts the CPU and transitions from master CST to idle CST. Located in Idol CST
CST does not actively interact with the loop, nor does it monitor the state of the loop.

When the master CST or monitor CST receives a command from the CPU to become the master (this command is called a master command), it becomes the master and gains control of the loop. Also, the master CST is
Reset command from CPU (reset command)
Shift to monitor CST. FIG. 2 shows this state transition. When the power is turned on, CST enters idle mode, and from the CPU
When CONC/RSV command is received, it shifts to monitor mode. This is to avoid unnecessary error handling due to differences in the power-on sequence when starting the system for the first time. That is, when the CST is first powered on,
When CST is set to monitor mode, the corresponding monitor
CST starts monitoring the loop. Between this timing and the time when master mode CST is defined (master mode CST is defined by a command from the CPU, before the CPU is powered on and special production is possible, master mode CST The CST in the monitor mode will determine that the loop is abnormal (an abnormality in the master mode CST) when there is a period in which the error does not exist.
This problem does not occur if the transition to monitor mode is made by a command from the CPU.

FIG. 3 shows the transition of the operation mode of the loop bus. NL operation is a normal operation mode in which data is transmitted between the CPU and I/O on one side of the duplex loop (this is called NL: Normal Loop).
The other side (this is called BL) monitors the loop. If an abnormality is detected in the Normal Loop during NL operation, the CPU and I/O will be shut down in the Back Loop.
Data transmission between the two terminals is performed. Normal
When both the Loop and Back Line become abnormal (for example, when both loops are disconnected) and the loop complete signal is no longer detected, the master CST instructs each station to turn back the loop and complete the loop. (Loop connecting Normal Loop and turning point, Back Loop and turning point)
Instruct loop configuration control (loopback control) so that significant signals can be transmitted. This ensures that there is a significant signal that goes around the loop, allowing the mode of operation to function as a loop bus.
This is called LB operation (Loop Back operation), and the station sandwiched between the turning points becomes disconnected from the loop. In Figure 3, the dashed arrow indicates Master
Indicates that the operation mode will change when the CPU issues a command to return to normal operation (RLBC command) to the CST in the mode. CPU
You can issue a command (SLBC command) to the CST in Master mode to shift to LB operation. At this time, the CST in Master mode is instructed to the station that should be the turning point.
CST in Master mode performs processing according to the stored loop configuration information.

The above operation will be specifically explained using the drawings.

Here, the CPU 1 and the CPU 1-connected CST 8 will be explained as an example. CPU2, 3, and CST9,
The same applies to 10.

Figure 4 shows a block diagram of CST8. CST8
is a microprocessor 8-1 and a read-only memory (ROM) 8 containing a microprogram.
-2, Writable memory (RAM) 8-3,
Interrupt control LSI (PICU) 8-4, communication control LSI
(HDLC) 8-5, general-purpose input/output control LSI (PPI) 8
-6, a timer (PTM) 8-7, and an interrupt register 8-9 that stores the contents of an interrupt from the CPU 1, and these are connected by a common bus 8-8.

Furthermore, a supervisory signal generator 8-- which facilitates data transmission.
Multiplexer (MPXB) that selects either the monitoring signal from 11 or the data signal from HDLL 8-5 8-12, multiplexer (MPXB)
A multiplexer (MPXA) 8-17 that selects whether to transmit the signal selected by 8-12 or to transmit the signal on the loop as is (IDLE), and a reverse multiplexer (MPXD) 8-2.
2. Detector 8 that detects signal disconnection in all multiple loops
-15, LOOP CONTROL 8-14 that issues selection commands to these multiplexers, signal receiving circuits 8-20, 21, and signal transmitting circuits 8-18, 19.
It becomes more. There is also a report register 8-27 for reporting to the connected computers. Interrupt register 8-
9 and report register 8-27 are connected to CPU 1 via connection line 80. Using the above configuration, the specific processing is shown in FIGS. 5 to 9.
This will be explained using figures.

FIG. 5 shows a process in the CST 8 that is activated by a command from the CPU 1 or by turning on the power of the CST 8. First of all, when the power is turned on, CST8 unconditionally
At the same time as transitioning to IDLE mode,
Store in RAM8-3. In IDLE mode, it shifts to the Pass state for Loops 11 and 12. This is done by LooP CTL 8-14 and multiplexer 8-17 or 8-22. or,
If the command from CPU1 is the AMSTER command, RAM8-
3, and sends a monitoring signal to Loop 11 (Normal Loop), and starts a monitoring signal waiting timer 8-7. Also, if the command from CPU1 is reset, it will itself:
Transition to MONITOR mode, and transition to PASS state for Loops 11 and 12. Furthermore, the opponent
Monitoring signal wait timer 8 from MASTER CST
Start up 7. FIG. 6 shows an example of interrupt processing activated by an interrupt from the current loop. Here, current use means Loop11 during Normal Loop operation.
When driving Back Loop, refer to Loop 12. Interrupts received from Loo 11 or 12 are received by HDLC 8-5 via multiplexer 8-13,
Interrupts from HDLC8-5 are interrupt control LS18-4
A reception interrupt is input to MPU8-1. This interrupt starts the interrupt processing program shown in FIG. At this time, if the received data is a supervisory signal, MONITOR CST is activated by the supervisory signal wait timer 8.
-Restart 7. Also, this interrupt
In the event of an LSI failure, if the own CST is MASTER,
It is determined that the management of Loops 11 and 12 cannot be maintained, and the Loops are shifted to the Pass state and then to the IDLE mode. Furthermore, the own LST8 to the connected CPU1,
Sets and reports MASTER failure in report register 8-27.

FIG. 7 shows an example of the process of checking for signal disconnection in the current loop 11 or 12. Check for signal interruption
Performed only by MASTER CST, signal disconnection is detected by signal disconnection detector 8-15, and general-purpose input/output control LSI
It is detected by reflecting it on the status. If the signal disconnection occurs during normal operation (Loop 11), the current loop is switched to Back Loop (Loop 12). In the switching process, multiplexer A8-17 is cut off by the command of Loop CTL8-14, and multiplexer B is switched to multiplexer D8-22.
Send the signal from 8-12 to Loop12. Furthermore, it sends a monitoring signal to Back Loop (BL) 12 and detects Normal Loop failure.
Report to CPU1. If Back Loop operation is in progress when the signal is cut off, ST5, 6, 7 and MST13, 14, 1 connected to Loop 11, 12
5, sends a Loop Back command to Loop
Shift to Back mode. Furthermore, Back Loop abnormality
Report to CPU1. Also, if the signal is cut off, it will be Load Back.
If it is running, it will be determined that Loops 11 and 12 cannot be managed, and the local MASTER will be sent to the connected CPU1.
Report CST Give up. Figure 8 shows an example of timeout processing within CST.
3. When the mode of the stored CST is MONITOR mode, POL from the other party's MASTER mode CST
If the signal is not received within a predetermined period of time, this timeout occurs. If this timeout occurs, it is determined that the other MASTER mode CST has failed, and is reported to CPU1 by interrupt. or
When the CST mote stored in RAM8-3 is in MASTER mode, the monitoring signal sent by its own CST8 will time out within a certain period of time, but if this timeout occurs, the self
Report MASTER CST failure to CPU1 and shift to IPLE mode. FIG. 9 is an example of processing when the means of communication between the own CST and the CPU is interrupted. In this example, if the report to CPU1 is performed using DMA (direct memory access),
When a DMA error occurs, the means of communication between the own CST and the connected CPU is interrupted, and if the CST mode in RAM 8-3 is MASTER mode, it shifts to IDLE mode, and for Loop, it becomes PASS state.

Each of the I/Os 16 to 18 connected to the loop can be occupied by a different CPU, but
All I/Os connected to the loop are grouped together.
It can also be used exclusively by the CPU. To do this, the CPU that occupies the loop all at once
CONC for all I/Os under the loop from
Issue the FREE command and perform all I/O of the loop from the CPU that wants to newly occupy the loop.
Issue CONC/RSV command. At this time, when the loop is in the LB operation state and the I/O is disconnected from the loop, the CONC/RSV command will not reach the I/O, so the I/O will not receive the CONC/RSV command.
Only O will not be occupied by the CPU that newly occupied the loop. To prevent this inconvenience,
The CPU remembers which I/Os were detached as reported by interrupts from the CST in Master mode, and after returning the loop to normal operation (RLB
(After issuing the command)
Issue an RSV command. By doing this, it becomes possible to switch between occupancy and occupancy of the loop at once between each CPU, regardless of the operating state of the loop.

Now, in a multi-computer system, something called CPU configuration control is performed.
For example, in Figure 1, CPUs 1, 2, and 3 perform task A,
Assuming that tasks B and C are being executed separately, and task A is an important task for the entire system, if CPU1 fails due to an error, the remaining CPUs 2 and 3 will continue tasks B and C. may also be meaningless for the system as a whole. Therefore, in such a case, if you have CPU2 and CPU3
It is necessary to take over the task A that was being performed on CPU1, and also to release all the sources that were occupied by CPU1 that caused the error, and transfer them to other CPUs2 and 3.
The CPU 1 must be stopped so as not to cause any disturbance or disturbance while the CPU 1 performs processing. This kind of processing is called CPU configuration control. Also,
Even if there is no abnormality in the CPU, the operation of a certain CPU may be stopped in a planned manner or the content of work being performed within the CPU may be changed due to system operation reasons. This is also called CPU configuration control. When performing such configuration control,
When performing configuration control that would result in the termination of a CPU connected to a CST in Master mode, the CST connected to a CPU connected to other surviving CPUs must be placed in Master mode. Because the connected CPU
When CST is stopped, CST in Master mode
This is because the CPU cannot report loop abnormalities and cannot update the stored loop configuration information based on instructions from the CPU.

Also, if the CST is changed from CST in Master mode,
When the CPU receives notification that it is no longer able to maintain Master mode, it sends a notification to one of the other CPUs to change the connected CST to Master mode.

Master mode CST associated with CPU configuration control
The switching is performed as shown in FIG. In FIG. 10, "CPU separation" refers to the process of stopping the target CPU and releasing the resources occupied by the CPU. "CPU switching" means that the CPU
This is the process of stopping the business that was being executed up to that point, releasing the resources occupied by that business, and starting a new business. "Starting the CPU"
refers to the process of starting a previously stopped CPU and starting a new task. The processing flow for disconnecting and starting up the CPU is explained in the 11th chapter.
These are shown in Fig. 1 and Fig. 12, respectively. In Figure 12, whether the loop is connected to the CPU or not is determined by
For example, this can be checked by having a table as shown in FIG. In Figure 13, 31 is each CPU
It is stored in the common memory GM (4 in Figure 1), which is a shared memory between CPUs that can be commonly referenced from.
This table has as many loop buses as there are in the entire system (from loop 1 to loop n), and each bit 0, 1, 2, etc. corresponds to the CPU number. That is, if bit 2 for loop 2 is 1, then If it is 0, loop 2 is connected to CPU #2, and if it is 0, it means that loop 2 is not connected to CPU #2. Also, this table has other
It is also used when requesting that the CST under the CPU be set to Master mode. A table with the same structure as in Figure 13 is used to find out which of the CSTs connected to the loop is in Master mode. However, when managing the Master mode CST, if the Master mode CST is expressed as 1, the 13th
In the figure, there is only one bit in each column that is 1 in the table for each loop, which is different from the case where the connection relationship between each loop and the CPU is shown. 14th
The figure shows whether or not the Master mode CST is being set for each loop, and two CSTs can be set at the same time.
This is used to provide an interlock to prevent the device from entering Master mode. When referencing these tables, it is necessary to take an interlock so that multiple CPUs do not refer to them at the same time, so if this table is stored in GM4, which is the common memory between CPUs, it is necessary to interlock it using the TEST and SET command, etc. Take the lock.

Next, CST configuration control based on reports from the CST side is shown in FIGS. 15 and 16. In addition, in Figures 11, 12, and 16, other CPUs
When sending a message to set up Master mode on a computer, the method to determine the contact person is, for example, from the loop and CST connection information in Figure 13, find the CST connected to the loop, and connect that CST.
Among the CPUs, the CPU that is to be disconnected,
This can be done by arbitrarily selecting one of the CPUs excluding the currently stopped CPU. This is done using the common signal line 19 in FIG. Note that this notification may be issued after selecting one CPU as described above, but it is also possible to issue this notification after selecting one CPU, but it is also possible to issue the notification to all CPUs.
The CPU that received the message will win on a first-come, first-served basis.
The CST connected to the CPU may be set to Master mode. However, in that case,
CPU connected to CST in Master mode
must ignore this message.

〔Effect of the invention〕

As described above, according to the present invention, configuration control of multiple CSTs is performed by a computer connected to each CST, and
In addition, each computer performs configuration control by referring to configuration control information that is stored in a common memory that is commonly used by each computer and is constantly updated, even when the computer starts and stops, so reliable CST can be achieved. Configuration control can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of a multi-computer system to which the present invention is applied, FIG. 2 is a diagram showing the transition of configuration control of the CST, and FIG. 3 is a diagram showing the transition of the operation mode of the loop bus. Figure 4 is a block diagram of an embodiment of CST used in the present invention, and Figures 5 to 9.
The figure is a flowchart for explaining the operation in Figure 4, and Figure 10.
Figures 11 and 12 are diagrams showing the master mode CST switching associated with CPU configuration control.
The figures are flowcharts showing processing when disconnecting and starting up the CPU, respectively. Figures 13 and 14 are diagrams showing examples of configuration control information stored in the common memory, respectively. Figures 15 and 16 are diagrams showing examples of configuration control information stored in the common memory.
3 is a flowchart showing configuration control processing using an interrupt from CST. 1-3...Calculator, 4...Common memory, 8-10...
Control station, 19... common connection line.

Claims (1)

[Claims] 1 A plurality of computers, a common memory connected to the plurality of computers and used in common among the computers, a common bus connecting the plurality of computers, and a computer connected to the common bus and controlled by the computers. A multi-computer system having a plurality of input/output devices connected to the common bus and a plurality of control stations that are controlled so that only one of them acts as a master station and performs overall management of the common bus at a time. , each computer is associated with and connected to multiple control stations, each control station reports a status signal indicating whether the common bus is being used normally to the corresponding computer, and each computer communicates with the corresponding control station. Based on the status signal from the computer and instructions from other computers, refer to the configuration control information stored in the common memory, update the configuration control information, and issue a configuration control command to the corresponding control station; When a computer starts operating, the computer refers to the configuration control information of the common memory and determines whether there is a master control station on the common bus to which the computer is connected, which performs overall management of the common bus. If the computer does not exist, a command is issued to the control station connected to the computer to become the master control station, and when the computer stops, the computer refers to the configuration control information in the common memory. Check whether the control station connected to the computer in question is the master, and only if it is the master, the control station connected to that computer will be the master for other computers. A control station configuration control method in a multi-computer system characterized by issuing commands.