JPS6252796A - Memory access controller - Google Patents

Abstract

PURPOSE:To make average the number of times to write on or erase from a memory and to extend the access life of the memory by enabling the management of the addressing to the memory with providing a counting means. CONSTITUTION:A counter (COU) 3 counts the number of times of writing or erasing of an EEPROM2. An address pointer (ADP) 4 indicates in order a write address to the EEPROM2 through a data bus (DB) 5 in one direction from the high-order to the low-order or vice versa. When a data is written on the EEPROM2, the data is written on a prescribed address based upon the content of the address pointer 4 from a MPU1 through the data bus 5, also increasing the content of the ADP4 by '1'. At such a time, when the content of the ADP4 is progressed to the address of one chip share of the EEPRM2, the MPU1 initializes the content of the ADP4, increasing the content of the counting counter (COU) 3 by '1' through the DB5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device for controlling erasure or damage of an electrically erasable programmable ROM.

[Conventional technology]

Conventionally, in this type of device, when writing or erasing data to the EEFROM, a counter is provided to count the number of erasures or old data, and the counter is counted up or down every time the operation is executed. ? He was managing the office.

In other words, erasure that is compensated by the manufacturer or
1) We have adopted a method of using within the range of the number of times of inking.

[Problem that the invention seeks to solve]

However, if only a specific address is stale, the number of accesses at that address will reach the end of its lifespan earlier than other addresses, and the chip cannot be used even though other addresses can be accessed. There was a problem in that the efficiency of writing into the memory 1B was significantly lowered.

The present invention was made in order to solve the above-mentioned problems, and an object of the present invention is to provide a memory access control device that can prolong the access life of the memory by equalizing the number of times of writing or erasing to the memory. do.

[F-stage to solve problems]

The memory according to the present invention; the access control device includes an instruction stage for sequentially instructing 8 write or erase addresses of an electromagnetically erasable programmable read-only memory in one direction from a high level to a low level or from a low level to a high level; A counting means is provided for counting the number of times the indicating stage is used to write or erase the electrically erasable programmable read-only memory.

[Effect]

In the present invention, writing or writing is instructed by the instruction means. sequentially accesses the electrically erasable programmable read-only memory in one direction from high to low or from low to high according to the erase address,
Each time all addresses of the electrically erasable programmable read-only memory are accessed, the counting means counts the number of times the electrically erasable programmable read-only memory is written or erased.

〔Example〕

FIG. 1 is a block diagram for explaining a memory access control device showing an embodiment of the present invention, in which 1 is a microcomputer (MPU), and a ROM 1a that stores a control order as shown in FIG. (f). The MPU 1 collectively controls the writing and erasing of data 'i into the electrically erasable EEPROM 2 according to the control r stored in the ROM 1a. 3 is the counting means of the present invention. Eggplant counting counter (COU), E E F ROM
2 (7) Count the number of iB transfers or deletions. 4 is an address pointer (A
DP), a write address to the EEPROM 2 is sequentially instructed in one direction from high to low or from low to high through the data bus (DB) 5. EEFROM2
Data to! 3, data is read from the MPUI to a predetermined address based on the contents of the address pointer 4 via the data bus 5, and the contents of ADP4 are incremented by (IJ).

When the contents of ADP4 (7) advance to the address of 21 EEFROM chips, MPU 1 initializes the contents of ADP4 and increments the contents of counter C0U3 by rlJ via the DBS.

This series of operations is repeated until the contents of C0U3 reach a predetermined number of times (varies depending on the product).

Next, the memory access control operation according to the MPUI in the present invention will be explained with reference to FIG.

FIG. 2 is a flowchart illustrating the memory access control operation by the MPU 1 in the present invention. In addition,(
1) to (7) indicate each step. Also, EEFROM
The capacity of 2 is 1, for example 8 bytes (8192 words
8bit), the number of times it is erased or damaged is guaranteed to be 100.
00 times, the fortune-telling start address is r0000+i, ~
Suppose that it is 1FFFI6J.

First, MPU 1 initializes ADP4 and C0U3 according to the control procedure stored in ROM1a (1),
The contents of ADP4 and C0U3 are set to rOJ. Next, data is written to EEPROM2 under the control of MPU 1 (2), and immediately after that, rlJ is incremented to the contents of ADP4 (3). Then, the contents of ADP4 are r
Please judge whether it has reached 2000J 4), YES
Then, initialize ADP4, that is, change the contents of ADP4 to I
J, 6 (5), then -c', C0U5 (7)
The content is incremented by rlJ (6), and it is determined whether the content of C0U3 has reached r2710+J, that is, 10,000 times (7). In this judgment, if the number of times has reached 10,000, writing to the EEFROM 2 is finished, and if it is less than 10,000 times, the process returns to step (2).

On the other hand, if No in step (4), step (2)
Return to In this way, since writing to the EEFROM 2 is repeated circularly from the start address 1'000+J to rlFFF16J, the writing can be uniformized over the entire chip.

Note that although the write operation in memory access has been described in the above embodiment, the same applies to memory erasure. Furthermore, in the above embodiment, a case was explained in which addresses are sequentially specified in one direction from high to low.
It is also possible to give instructions sequentially in one direction from a low level to a high level.

Further, in the above embodiment, a case has been described in which the address control of the EEPROM 2 is performed from the external C0U3 and ADP4, but the same function can be achieved when the EEPROM 2 has C0U3 and ADP4.

〔Effect of the invention〕

As explained above, the present invention provides an instruction means for sequentially instructing write or erase addresses of an electrically erasable programmable read-only memory in one direction from high to low or from low to high, and an electrical - to erasable programmable read-only memory
3. Since a counting means for counting the number of times of writing or erasing is provided, addresses to the memory can be managed, and the number of times of writing or erasing to the memory can be equalized.
It has an excellent effect of extending the access life of memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining a memory access control device showing an embodiment of the present invention, and FIG. 2 is a flowchart for explaining a memory access braking operation by an MPU in the present invention. In the figure, 1 is MPU, 1a is ROM, 2 is EEPROM,
3 is COU, 4 is ADP, and 5 is DB. Figure 1 Figure 2

Claims (1)

[Claims] An instruction means for sequentially instructing a write or erase address of an electrically erasable programmable read-only memory in one direction from a high level to a low level or from a low level to a high level; A memory access control device comprising: counting means for counting the number of times of writing or erasing.