JPS6252634A - Buffer memory construction - Google Patents

Abstract

PURPOSE:To secure communications through the use of small-sized memory by making it possible for data to circulate from the final address of a final program in a main memory to the top address of the 1st block and omitting information other than data on an identifying element receiving a signal from being recorded in the main memory. CONSTITUTION:Reception data is converted and stored at an address in the main memory of contents stored in the WP of a block of contents recorded in a register WPQ, while transmission data is read out of an address in the main memory with contents stored in the read address memory RP of a block storing contents recorded in a register RPQ. When the reception data is stored at the final address of the final block, the contents of the WPQ return to the 1st block, and the contents in the WP of the 1st block are checked by a CPU. From the contents the data stored in the 1st block is discriminated whether all of the data is read out or not. If so, the reception data is consecutively converted, and stored in the 1st block. If all the data is not read out, it is judged that the system develops an error, and the reception and transmission are stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the structure of a buffer memory necessary for converting communication protocols and communication speeds.

Prior Art FIG. 2 is a general block diagram of the above-mentioned communication conversion system, in which communication data input as a serial bit signal to the input terminal 11 of the first serial-to-parallel conversion circuit is transmitted to the first serial-to-parallel conversion circuit. The serial/parallel converter circuit sends an interrupt signal to the central processing unit (hereinafter referred to as CPU) 4 from its terminal 12 every time one byte or one word is converted. do. CPU
receives this interrupt signal, takes in 1 byte or 1 word of communication data from the first serial/parallel conversion circuit, performs predetermined protocol conversion, and stores the data in memory 2.

The CPU also receives an interrupt signal from the terminal 32 of the second serial-to-parallel conversion circuit 3 and sends the data stored in the memory 2 to the serial-to-parallel conversion circuit 3 in parallel, one byte or one word at a time. The serial/parallel conversion circuit 3 converts this into a serial bit signal and outputs it.

Problems to be Solved by the Invention In the communication conversion system shown in FIG. 2, one (17" lock or one
The memory size used is large enough to accommodate the expected amount of communication data (pages).

An object of the present invention is to provide a memory structure that ensures reliability of communication with a smaller memory by managing this memory by a CPU.

Means for Solving the Problems FIG. 1 is a block diagram of the memory 2 shown in FIG. 2 according to the present invention. Note that in FIG. 1, system paths between the CPU 4 and each part of the memory 2 are also shown. A block diagram of the entire communication conversion system using the memory of this configuration is the same as that shown in FIG.

In FIG. 1, 21 is the main memory, as shown in the figure.
divided into blocks. 22 is a write address memory WP that records the address of the main memory where received communication data is converted and stored, and 23 is a read address memory RP that records the address of the main memory from which the transmitted data is read. WP and RP
The same number n of main memories are provided. 24 is a memory or register WPQ for recording the block number of WP, and 25 is a memory or register RPQ for recording the block numbers of R and P.

The main memory of the CPU is the above WP, WPQ, RP and RP.
By managing the recorded contents of Q, it is placed under the control of the CPU.

Prior to starting transmission/reception, the CPU reads WP, WPQ, and RP.
and initializes the recorded contents of RPQ. Received data is WPQ
The transmitted data is converted and stored in the main memory address of the WP recorded content of the block of recorded content of , and the transmission data is read from the main memory address of the recorded content of RP of the block of recorded content of RPQ.

When the received data is stored in the final address of the final block in FIG. 1, the contents of WPQ return to the first block (for example, 1).
The contents of the WP of the first block are checked by the CPU, and it is determined from the contents whether all the data stored in the first block has been read out or not. If all the stored data has been read out, remove: convert the received data and store it in the first block. If all the data in the first block has not been read out, the CPU determines that an error has occurred in the system and stops transmission and reception.

As described above, according to the present invention, the main memory divided into n blocks can be recycled to ensure the reliability of transmitted and received data, and the first address of the first block can be used next to the last address of the last block. The overall memory size can be reduced.

Prior to starting transmission/reception of the embodiment, the CPU 4 initializes the recorded contents of WP and -RP to O, and the recorded contents of WPQ and RPQ to 1.

When reception starts, the CPU 4 in FIG.
As shown in the figure, it is checked whether the received data taken in from the first serial/parallel converter circuit connected by the system bus is the head identifier of the packet, and if it is not the head identifier of the packet, the data is converted and Retrieve the next data without storing it in memory.

If it is a packet header identifier, it checks whether the next data is a communication data header identifier, and if it is not a communication data header identifier, it converts the data, takes in the next data without storing it in the main memory, and then checks whether the packet header identifier is the packet header identifier again. Take
Repeat the above operations until the screen is fully loaded.

When the packet header identifier is fetched, and the communication data header identifier is fetched, the next fetched data is converted and stored in the main memory, and the recorded contents of the WP are sequentially incremented by one.

If the captured data is the communication data final identifier, the recorded contents of the WP at that time are rewritten to the block final address and reception is stopped. When the recorded content of the WP is increased by the number of packet constituent data, data conversion and storage is interrupted until the packet head identifier is taken in again as the next data, and storage of error check symbols received during this time is omitted.

When the recorded contents of WP reach the final address of the memory block, the data is stored at that address, the contents of WPQ are incremented by one, the contents of WP in that block are checked, and if it has been initialized, reception continues. do. If the contents of the WP have not been initialized, it is determined as an error and reception is stopped.

On the other hand, the CPU checks the recorded contents of the WP of the block containing the contents of the RPQ by an interrupt signal from the second serial/parallel conversion circuit connected to the CPU 4 of FIG. 1 by the system bus as in FIG. If it is the final address of
Sends the packet header identifier of the predetermined protocol first,
Next, the communication data head identifier is sent, and the converted communication data stored in the memory address of the recorded contents of R and P of one block of the RPQ contents is read out and sent,
Increase the recorded content of RP by one. The above communication data transmission is repeated at a predetermined communication speed, and if the transmission data is the communication final identifier, a predetermined number of error check symbols are transmitted and subsequent data transmission is stopped. C in the middle of sending
When the PU identifies an error, it sends an identifier indicating the error and stops sending data. When data transmission is repeated and the recorded content of the RP increases by the specified number of data in the packet, a predetermined number of error checking codes are transmitted, a packet head identifier is transmitted, and the RP is recorded again. Read and send data from the memory address of the contents.

When the recorded contents of RP reach the final address of the block, the data at that address is read out and sent, and then the recorded contents of WP and RP of the block of RPQ contents at that time are initialized and R
Increase the contents of PQ by one, check the contents of WP of that block, and if it is the last address of the block, continue reading and sending data from the address of the contents of RP of that block, and if WP of that block If the content of is not the final address of the block, reading and sending of data is interrupted until it is updated to the final address.

3, 4, 5, and 6 are flow charts of the above-described embodiment, and for the sake of simplicity, the number of memories in each block of the main memory is made to match the specified number of data in a packet. In addition, write flag WF is used to manage the memory state.
and read flag RF are used.

FIG. 4 is a flowchart showing the flow of reception, FIG. 5 is a flowchart showing the flow of transmission, and FIG. 6 is a flowchart of the block update subroutine in the flow at the time of transmission and reception.

The flags WF and RF are set to 1 when no transmission/reception is being performed, 1 when transmission/reception is being performed to 0.1 block of memory, and a waiting state for data to be transmitted and received after updating the block. It takes a value of 2 when .

Also, if the memory block in which you are trying to store the data is not initialized when receiving data, perform appropriate error handling or initialize all memory, registers, and flags as shown in the dotted routine. That's how it is.

Effects of the Invention As described above, according to the present invention, the memory is completely
Under the control of U, the main memory circulates from the last address of the last block to the first address of the first block. It is possible to distinguish between these and exclude them from being recorded in the main memory, and the reliability of communication is ensured by the small-scale main memory, which has an excellent practical economical effect.

[Brief explanation of drawings]

Figure 1 is a memory configuration diagram of the present invention, Figure 2 is a general configuration diagram of a communication conversion system, Figures 3, 4, 5, and 6.
The figure is a flowchart of an embodiment. 2 is a memory, 21 is a main memo' J-122 is a main memory write address memory, 23 is a main memory read address memory, 24
is write address block number memory or register, 25
is the read address block number memory spanning register, 4 is CPU0

Claims (3)

[Claims] (1) Main memory divided into n blocks, n main memory write address memories, n main memory read address memories, write address block number memories or registers, read address block number memories or means for initializing the contents of the write and read address memory and the write and read address block number memory or register; and upon reception, the contents of the write address block number memory or register contents; If the contents have not been initialized, reception is interrupted, and if the contents have been initialized, the write address block number memory or register contents are stored in the main memory of the block from the first address of the block to the last one. means for sequentially recording the received data up to the address and sequentially rewriting the contents of the write address memory to the data recording address or a numerical value corresponding to the write address; (a means for rewriting the contents of the address memory to the last block address or a numerical value corresponding thereto); If the content does not correspond to the corresponding value, the transmission is interrupted, and if the content is the last address of the block or a value corresponding to it, the data is read from the first address of the main memory of the read address block number memory or the contents of the register to the last address (the corresponding number). After recording the address or the corresponding numerical value in the read address block number memory or the read address memory of the contents of the register, and after reading the data (from the address) and transmitting it sequentially, Means for initializing the contents of the write address memory, and if the received data ends at an intermediate address of the main memory of the block, the contents of the write address memory of the read address block number memory or register contents at that point. and a means for initializing the write address block number memory or the register to complete the writing of the data from the first address to the last address of the main memory of the block containing the contents (or after writing the received data at an intermediate address). means for incrementing the read address block number by one unit (or at an intermediate address); means for incrementing the write and read address block number by one unit (when the received data ends); and means for returning the contents to the initial value when the contents of the write and read address block number memory or register exceed the number of divisions of the main memory or a numerical value corresponding thereto. A buffer memory structure having. (2) In the buffer memory described in item 1, when the received data ends at an address in the middle of a block, the contents of the write address memory are rewritten to the last address of the block or a numerical value corresponding to it. means for incrementing the contents by one unit; means for interrupting transmission if the contents of the read address block number memory or write address memory of the contents of the register at the time of transmission are not the last address of the block or a numerical value corresponding thereto; A buffer memory structure having means for initializing the contents of the write address memory of the read address block number memory or register and incrementing the contents of the read address block number memory or register by one unit when transmission data ends. (3) In the buffer memory described in 1 and 2,
A buffer memory structure in which the number of blocks of memory matches the number of packet data.