JPS6251817A - Variable type delay time equalizer - Google Patents

Abstract

PURPOSE:To obtain an optional characteristic from group delay of a resonance curve to flat group delay by branching a signal into two, providing a variable phase device to both the signals, providing further a variable attenuator and an LC resonance circuit to the one signal and synthesizing both the branched signals. CONSTITUTION:The vector locus of the transfer function of the 1st transfer function of the 1st transmission line through a power branching device 2, a variable phase device 9 and a power synthesizer 10 is shown in dotted lines A and the vector locus of the transfer function of the 2nd transmission line through the power branching device 2, a variable attenuator 3, a high output impedance isolation amplifier 4, a parallel resonance circuit 5, a variable resistor 6, a low input impedance isolation amplifier 7, a variable phase device 8, a power synthesizer 10 is shown in dotted lines B. The vector locus of the synthesized output of both the transmission lines by the power synthesizer 11 is shown in dotted lines C. Thus, a group delay time characteristic with constant amplitude and forming the resonance curve is obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a variable delay time equalizer used in a satellite equalizer, etc., which requires a wide variable range of second group delay time characteristics. It is.

[Conventional technology]

Conventionally, this type of variable delay time equalizer has the configuration shown in FIG. That is, a power splitter 2 that branches the input signal from the input terminal 1 into two, a variable attenuator 3 that receives one output branched by the power splitter 2, and a variable attenuator 3.
and a high output impedance isolation amplifier 4 which inputs the output of.

A low input impedance isolation amplifier 7 receives the output of the high output impedance isolation amplifier 4 through a parallel resonant circuit 5 with one end grounded, consisting of a variable coil 51 and a capacitor 52, and a variable resistor 6; The output of the dance inlation amplifier 7 is input. A variable amplitude equalizer 8' consisting of a capacitor 81', a coil 8Z' and a variable attenuator 83' and the output of the other branched by the power splitter 2 are input. Coil 91'
, an amplitude equalizer 9' consisting of a capacitor 92' and an attenuator 93'.

It has a power combiner 10 that combines the output of the amplitude equalizer 9' and the output of the variable amplitude equalizer 8', and the output of the power combiner IO is outputted as an output signal through an output terminal 11.

In such a configuration, the parallel resonant circuit 5 consisting of the variable coil 51 and the capacitor 52 produces group delay time characteristics. That is, the resonance sharpness Q of the group delay time characteristic forming the resonance curve can be varied by the variable resistor 6, and the center frequency f0 can be adjusted by the inductance of the variable coil 51.

Generally, in a variable delay time equalizer, when a large group delay time characteristic is required, the biggest problem is how to flatten the amplitude frequency characteristic.

In the conventional circuit example shown in FIG.
2' and a variable attenuator 83'.
′ can be adjusted to a flat or positive or negative linear slope.

[Problem that the invention seeks to solve]

However, in the conventional circuit example shown in FIG. 3, in order to obtain a flat amplitude frequency characteristic, an amplitude equalizer is added to the output of the circuit shown in FIG. There are drawbacks that require it.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned conventional drawbacks, and an object of the present invention is to provide a variable delay time equalizer with flat amplitude frequency characteristics and a wide variable range of group delay time. It is in.

[Means for solving problems]

The variable delay time equalizer according to the present invention includes a power splitter that splits an input signal into two, and a variable attenuator that receives the output of one of the split signals from the power splitter.

A first high isolation amplifier inputs the output of this variable attenuator, and the output of this first high isolation amplifier is connected through a parallel resonant circuit with one end grounded, consisting of a variable inductance and a capacitor, and a variable resistor. a second high-isolation amplifier that inputs the output, a first variable phase shifter that inputs the output of the second high-isolation amplifier, and a second variable phase shifter that inputs the output of the other branched by the power splitter. It is characterized by comprising a variable phase shifter and a power combiner that combines the output of the second variable phase shifter and the output of the first variable phase shifter.

〔Example〕

Hereinafter, nine embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a variable delay time equalizer according to the present invention, and parts having the same functions as those in FIG. 3 are given the same reference numerals. The difference from FIG. 3 is that a variable phase shifter 8 is provided in place of the variable amplitude equalizer 8', and a variable phase shifter 9 is provided in place of the amplitude equalizer 9'.

2 is a vector locus of the transfer function of the circuit of FIG. 1, and A is the vector locus of the transfer function of the circuit of FIG. A vector locus of the transfer function of the first transmission line that passes through the variable phase shifter 9 and the power combiner IO to the output terminal 11, B is the vector locus of the transfer function from the input terminal 1 to the power splitter 2, the variable attenuator 3. High output impedance isolation amplifier 4. Parallel resonant circuit 5. Variable resistor6. Low input impedance isolation amplifier7. a vector locus of the transfer function of the second transmission path that passes through the variable phase shifter 8 and the power combiner 10 and reaches the output terminal 11;
and C indicate the vector locus of the transfer function of the entire circuit from the input terminal 1 to the output terminal lit. Here, one frequency is the resonant frequency f of the parallel resonant circuit 5 including the variable coil 51 and the capacitor 52 from 0 (Hz). The case is shown in which the frequency is changed at regular intervals up to 2fo, which is twice the frequency.

In FIG. 2, the second transmission line represented by vector locus B has a variable coil 51. Capacitor 52. Variable phase shifter 8
．． and a variable attenuator 3 are provided. Further, a variable phase shifter 9 is provided on the first transmission line n represented by the vector locus A, and the signal is combined with the signal of the second transmission line by a power combiner 10. In that case, as represented by vector locus C, an output signal having a constant amplitude and a group delay time characteristic forming a resonance curve is obtained.

Center frequency f of the group delay time characteristic obtained at the output terminal 11
c can be adjusted by changing the inductance of the variable coil 51, and the sharpness of the resonance of the group delay time characteristic Q/
I'i can be adjusted using a variable resistor 6 provided between a resonant circuit 5 consisting of a variable coil 51 and a capacitor 52 and a low input impedance isolation amplifier 7. Although the amplitude is no longer constant with respect to frequency due to adjustment of the group delay time characteristic, the amplitude and phase of the signal passing through the second transmission path to be combined by the power combiner 10 can be changed by the variable attenuator 3 and the variable phase shifter 8.
and a variable phase shifter 9 provided on the first transmission path.
By adjusting , it is possible to flatten the amplitude frequency characteristics.

Referring to Figure 2, the adjustment of the 1st group delay time characteristic.

Even if the frequency characteristics of vector locus B change, the variable attenuator 3
By adjusting the variable phase shifters 8 and 9, it is possible to adjust the amplitude frequency characteristic to always be constant as represented by the pedal locus C.

Here, the variable phase shifters 8 and 9 are reactance circuits or delay lines using coils, capacitors, etc.

It is composed of circuits that can change constants such as the right strip 7'&--.

〔Effect of the invention〕

As explained above, the present invention has two transmission paths for high frequency signals.
An LC parallel resonant circuit, a variable attenuator, and a variable phase shifter are installed at one end of the power splitter that branches into two transmission lines, and a variable phase shifter is installed at the other end.

By using a power combiner that combines two transmission lines, it is possible to arbitrarily obtain a group delay time characteristic ranging from a resonance curve with a large resonance sharpness Q to a flat group delay time characteristic. This has the advantage that flat characteristics can be obtained by adjusting the two variable phase shifters.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of an embodiment of a variable delay time equalizer according to the present invention, and Fig. 2 shows a change in the frequency of the transfer function shown in Fig. 1 from O [Hz] to twice the resonance frequency. FIG. 3 is a block diagram showing the configuration of a conventional variable delay time equalizer. l...Input terminal, 2...Power splitter, 3...Variable attenuator, 4...High output impedance isolation amplifier, 5...Parallel resonant circuit, 51...Variable coil . 52... Capacitor, 6... Variable resistor, 7...
Low input impedance isolation amplifier, 8.9
...Variable phase shifter, 10...Power combiner, 11...
Output terminal. Figure 2

Claims (1)

[Claims] 1. A power splitter that splits an input signal into two; a variable attenuator that receives one of the outputs branched by the power splitter; and a first high isolation amplifier that receives the output of the variable attenuator. The output of the first high isolation amplifier is
a second high isolation amplifier that receives input via a parallel resonant circuit with one end grounded consisting of a variable inductance and a capacitor and a variable resistor; and a first variable phase shifter that receives the output of the second high isolation amplifier. a second variable phase shifter that inputs the output of the other branched by the power splitter; and a power combiner that combines the output of the second variable phase shifter and the output of the first variable phase shifter. A variable delay time equalizer comprising: