JPS6251450U - - Google Patents
Info
- Publication number
- JPS6251450U JPS6251450U JP14143485U JP14143485U JPS6251450U JP S6251450 U JPS6251450 U JP S6251450U JP 14143485 U JP14143485 U JP 14143485U JP 14143485 U JP14143485 U JP 14143485U JP S6251450 U JPS6251450 U JP S6251450U
- Authority
- JP
- Japan
- Prior art keywords
- processing
- logic diagram
- display
- functional logic
- coordinates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 claims description 7
- 230000010365 information processing Effects 0.000 claims 1
Description
第1図ならび第2図は、本考案の一実施例の制
御装置回路構成図、第3図は、図形処理装置の構
成図、第4a図は、フエーズ2に於ける画面表示
例の斜視図、第4b図は、フエーズ3に於ける画
面表示例の斜視図、第5図は、フエーズ4に於け
る画面表示例の斜視図である。
1…デイスプレイ、2…ポイントデバイス、3
…スイツチ、4…コマンド、5…カーソル、6…
制御装置、7…演算回路、8…アドレスデコーダ
、9…デイスプレイ制御回路、10…メモリ装置
、11…座標読み取り回路。
1 and 2 are circuit configuration diagrams of a control device according to an embodiment of the present invention, FIG. 3 is a configuration diagram of a graphic processing device, and FIG. 4a is a perspective view of an example of a screen display in phase 2. 4b is a perspective view of a screen display example in phase 3, and FIG. 5 is a perspective view of a screen display example in phase 4. 1...Display, 2...Point device, 3
...Switch, 4...Command, 5...Cursor, 6...
Control device, 7... Arithmetic circuit, 8... Address decoder, 9... Display control circuit, 10... Memory device, 11... Coordinate reading circuit.
Claims (1)
む座標読み取り回路、処理基本コマンド、画面領
域種別、シンボルデータ、図面情報等を格納する
メモリー装置、座標情報、処理コマンドの指定座
標算出、比較処理等を行う演算回路、処理の実行
タイミングを決定するデータデコーダ、デイスプ
レイの表示制御を行うデイスプレイ制御回路、図
形表示の為のデイスプレイ、及び座標指定のポイ
ントデバイスからなる図形処理装置に於いて、同
一表示画面上に、機能論理図とその展開形である
詳細論理図を同時に表示し、機能論理図上にて、
指定された任意のシンボルの展開形を索引し、詳
細論理図上の指定位置に配置を行い、シンボル間
の接続を自動的に行う事により要易に詳細論理を
作成する機能及び、展開結果を即座に機能論理図
へ自動フイードバツクし、展開済の機能論理シン
ボルにマークする機能を有する事を特徴とする図
形処理装置。 A coordinate reading circuit that takes in graphic information processing commands and drawing coordinates, a memory device that stores processing basic commands, screen area types, symbol data, drawing information, etc., coordinate information, calculations for specified coordinates of processing commands, calculations for comparison processing, etc. In a graphics processing device consisting of a circuit, a data decoder that determines the execution timing of processing, a display control circuit that controls display display, a display that displays graphics, and a point device that specifies coordinates, on the same display screen, The functional logic diagram and its expanded form, the detailed logic diagram, are displayed simultaneously, and on the functional logic diagram,
A function to easily create detailed logic by indexing the expanded form of any specified symbol, placing it at the specified position on the detailed logic diagram, and automatically connecting symbols, and displaying the expansion results. A graphic processing device characterized by having a function of immediately automatically feeding back to a functional logic diagram and marking expanded functional logic symbols.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14143485U JPS6251450U (en) | 1985-09-18 | 1985-09-18 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14143485U JPS6251450U (en) | 1985-09-18 | 1985-09-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6251450U true JPS6251450U (en) | 1987-03-31 |
Family
ID=31049212
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14143485U Pending JPS6251450U (en) | 1985-09-18 | 1985-09-18 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6251450U (en) |
-
1985
- 1985-09-18 JP JP14143485U patent/JPS6251450U/ja active Pending
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