JPS6251393A - Color killer for muse system television receiver - Google Patents

Abstract

PURPOSE:To recognize sufficiently information as an easy-to-see black/white picture by detecting whether or not each point at the pre-stage and post-stage of an HD waveform is within a fluctuation width provided in a specified level and outputting a zero output from a succeeding selector to a chrominance processing circuit when even one point is at the outside of the range to make a color signal zero. CONSTITUTION:A digital signal 101 being an output of an A/D converter 1 is led to a synchronizing separation/clock recovery system. A frame pulse detection circuit 3 generates a frame pulse 301 and a HD detection section 4 inputs the digital signal 101 and the frame pulse 301 to generate a HD pulse (horizontal synchronizing pulse) 401 and an error flag signal 402. The HD pulse 401 is inputted to a PLL circuit 5, which recovers a system clock synchronously with the HD pulse 401. The error flag signal 402 changes over the conduction of the position A of selectors 7a, 7b connected to a chrominance processing circuit 6 and the zero output of the position B.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvement of image quality when a signal C/N is defective in a decoder of a MUSE type television receiver or the like.

[Conventional technology]

Research and development of high-definition television is nearing the stage of practical use.

M U S E (Multiple 5ub-Ny
quist Sawpling Encoding
) method was developed by the Japan Broadcasting Corporation, and compresses a high-definition television signal with a baseband bandwidth of about 30 MHz to a bandwidth of about 8 MHz. After A/D converting the MUSE baseband signal input to the decoder, the television receiver performs digital signal processing to separate it into a Y signal and two color signals (Cw, CM signals), converts it to D/A, and outputs it. . As for the digital signal processing, various processes such as frequency band expansion, 9 color signal separation, and 1 time axis expansion are performed, but there is no special process for signal processing in the case of C/N failure.

[Problem that the invention seeks to solve]

If the C/N is poor, the color image becomes particularly difficult to see because the color signal is compressed by 1/4 time and the color sense.

In view of the above circumstances, an object of the present invention is to provide image information that includes:
Considering that the Y signal alone is sufficient for information transmission as long as the color is not a problem, a color killer is used to transmit only the Y signal in the case of a C/N failure to prevent the image from becoming difficult to see. It is about providing.

[Means for solving problems]

The color killer of the present invention detects the pre-stage level of the HD waveform.
Means is provided for outputting a judgment signal to each level detection circuit in the horizontal synchronization detection section consisting of the subsequent stage level detection and slope detection circuits when the sample value of the HD waveform exceeds a specified fluctuation range determined with respect to the reference level. an error flag circuit for generating an error flag signal when the judgment signal is received from at least one of the level detection circuits;
The color signal processing system is followed by a selector which sets the color signal output to zero when the error flag signal is input.

[Effect]

In the present invention, in a horizontal synchronization detection section that detects a horizontal synchronization signal from an HD waveform, fluctuations in the levels of the previous and subsequent stages of the HD waveform with respect to a reference level are grasped as corresponding to C/H, and when a C/N defect occurs, , the color signal display is stopped.

Therefore, in this case, although the image has no color, it is easy to see and the viewer can recognize sufficient information.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic diagram of a decoder for a MUSE baseband signal including a color killer.

The MUSE baseband signal is converted into a digital signal 101 by the A/D converter 1, and the band compression is expanded to the original signal band by the interpolation filter 2. At this time, the interpolation filter 2 has a function of time-compressing and separating the multiplexed color signal (C signal) and luminance signal (Y signal). The Y signal is output as an analog Y signal by the D/A converter 8a. On the other hand, the C signal is processed by the color processing circuit 6 as a wideband color signal (CW
The flaw signal and the narrowband color signal (CN signal) are separated into D/A converters 8b and 8 via selectors 7a and 7b, respectively.
c and output as an analog C8 signal + CN signal.

The selectors 7a and 7b have two input terminals A and B, and an error flag signal 402 from a horizontal synchronization detecting section (HD detecting section) 4, which will be described later, is input to the select terminal (S terminal).

When the error flag signal 402 is low, it is switched to the A input terminal, and when it is high, it is switched to the B input terminal. Therefore, when the error flag signal 402 is high, the output of the color processing circuit 6 is not transmitted, and the inputs of the D/A converters 3b and 3c are zero.
The analog C8 signal+CN signal becomes zero.

The digital signal 101 which is the output of the A/D converter l is
It also leads to synchronization separation and clock recovery systems. The frame pulse detection circuit 3 generates a frame pulse 301, and the HD detection section 4 inputs the digital signal 101 and the frame pulse 301 to generate an HD pulse (horizontal synchronization pulse) 401 and an error flag signal 402. do. The HD pulse 401 is input to the PLL circuit 5, and the PLL
The circuit 5 reproduces a system clock synchronized with this HD pulse 401. As mentioned above, the error flag signal 402 is sent to the selectors 7a and 7 connected to the color processing circuit 6.
Switches conduction on the A side of b and zero output on the B side.

Next, details of the HD detection section 4 will be explained with reference to FIG. Focusing on the sharply changing part of the HD waveform (displayed as a singing analog wave for easy understanding) shown in Figure 3,
Divides into three parts, performs level detection and slope detection,
Front stage level detection! 4 points in the section, subsequent level detection at 5 points in the n section, and slope detection at 3 points in the m section.

As shown in FIG. 2, the HD detection section 4 includes a pre-stage level detection circuit 41. Post-stage level detection circuit 42. Tilt detection circuit 45.
It consists of an error flag circuit 46.

Each level detection circuit 41 and 42 inputs the digital signal 101 and the frame pulse 301, and each level detection circuit 4
HD within the range of fluctuation from the standard level defined in 1.42.
It is detected whether each point in one section and n sections of the waveform is included. In FIG. 3, the permissible fluctuation level width for both the first stage and the second stage is commonly α. This level width is determined by level width setting circuits 43 and 44. Since the HD waveform is inverted line by line as shown in Fig. 3, each level detection circuit 41, 42 can be handled by inverting the numerical value at each point for each line, using the input frame pulse 301 as a reference. .

If each point in the front and rear stages is all within the variation range from the reference level, the slope detection circuit 45 detects the slope, and if it meets the regulations, generates the HD pulse 401. If any one of the four points in the β interval in the first stage or the five points in the n interval in the latter stage exceeds the fluctuation range, the HD pulse 401 will not be generated as described above, but the error flag circuit 46 will generate an error flag signal. 402 stands. As shown in the figure, the error flag circuit 46 performs the OR of 41a and 42a.

This error flag signal 402 is sent to selectors 7a and 7b.

In addition, in the conventional HD detection section, the front stage level detection circuit and the rear stage level detection circuit do not consider the level fluctuation width, but calculate the average value of each point of the front stage and the rear stage, and when the average value meets the regulations, , the inclination is detected.

〔Effect of the invention〕

As explained in detail above, in the present invention, it is detected whether or not each point in the front and rear stages of the HD waveform falls within a fluctuation range set at a specified level, and if even one point does not fall within the fluctuation range set, the color processing circuit follows. The color signal is set to zero by outputting a zero output from the selector. In other words, when there is noise in the MUSE baseband signal, the circuit of the present invention operates as a color killer by checking the data at the front and rear stages of the HD waveform to correspond to the C/N size. do.

In this way, although the color of the image disappears, the information can be sufficiently recognized as a black and white image that is easy to see. It is especially effective when the main content is character/numeric information.

[Brief explanation of the drawing]

1 and 2 are circuit block diagrams of twelfth embodiments of the present invention, and FIG. 3 is a diagram showing HD waveforms. 1-...-A/D converter, 2-...-interpolation filter,
3.--Frame pulse detection circuit, 4-.HD detection section, 5.--PLL circuit, 6.--color processing circuit, ? a, 7b --- selector, 8 a, 8 b
, 8 c-D/A converter, 41.42--HD front/back stage level detection circuit, 43.44-fluctuation level width setting circuit, 45--1 detection circuit, 46--error flag circuit.

Claims (1)

[Claims] In MUSE television receivers, each level detection circuit in the horizontal synchronization detection section, which consists of the HD waveform front-stage level detection, rear-stage level detection, and tilt detection circuits, has a regulation that sets the sample value of the HD waveform relative to the reference level. A means for outputting a judgment signal when the fluctuation range is exceeded is provided, and an error flag circuit for generating an error flag signal when the judgment signal is received from at least one of the level detection circuits is provided, and the color signal processing system is followed by an error flag circuit. , and a selector that sets the color signal output to zero when the error flag signal is input.