JPS6251336A - Communication control system - Google Patents

Abstract

PURPOSE:To attain the efficient transmission on a transmission line by providing the 1st and 2nd consecutive '1's detecting section, the 1st and 2nd counter sections and a means using an output data of a memory section or an output data of a data inverting section as a data outputted actually to a line so as to minimize the reduction in the transmission efficiency. CONSTITUTION:A counter section 15 counting an output (b) of a consecutive '1's detection section 13 obtains number of times for insertion of '0's. On the other hand, '0' level of a data inputted in a data inverting section 14 is inverted to '1' and '1' is inverted into '0', an output pulse (c) of a consecutive '1's detection section 16 is counted by a counter section 17 to obtain the number of times to be subject to '0' insertion with respect to an inverted data. Count outputs (d, e) of the counter sections 15, 17 are inputted to a comparison circuit section 18 and when the count output (d) of the counter section 15 is a smaller than a count output (e) of the counter section 17, a comparison output (f) of '1' level is outputted and when the count output (e) is smaller than the count output (d), the output (f) of '0' level is given. A selection circuit section 19 selects an output (g) of a memory section 11 as it is when the output (f) of the comparison circuit 18 is logical '1' and selects an output (h) of the data inverting section 14 when logical '0'.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is based on ARQ (Automatic Repeat
Request) communication system, especially HDLC (High Lebe) which adds a check bit of 7E in hexadecimal.
Data Link Control) communication method or SDLC (5 ychronous Data Li
This invention relates to a communication control device to which the nkControl) communication method is applied.

[Conventional technology]

In conventional HDLC or SDLC communication systems, this
As can be seen from FIG. 2, which shows the frame format of this communication system, the data to be actually transmitted was transmitted by being embedded as is in the information field. That is, a frame, which is a transmission unit, starts with the frame start flag (01111110 in binary, 7E in hexadecimal) in the flag field F and ends with 7 lags. However, the data that is actually sent on the line consists of the address field, A field, and control field CC.
(I) Regarding the frame check field (Fe2), it is inevitable that the same -A' turn as in the flag field F will occur, so according to the processing convention of O insertion/removal, the flag, etc. I try not to make it the same as the turn. That is, 1. For example, as shown in FIG. 3, when there are five consecutive 1's in the transmitted data,
On the transmitting side, by always adding a 0'', it is possible to distinguish it from a flag/guturn (six consecutive 1''s). The inserted zero data is shown in FIG. 3 with two amplifier lines added to O. On the receiving side, on the other hand, by removing II O# immediately after five consecutive 1's, the same data as the transmitted data is reproduced. This process is called O insertion/removal. .

However, as shown in Fig. 4, for example, all °'1''
When attempting to transmit outgoing data.

A large number of inserted '0's were added, which inevitably reduced the actual transmission efficiency.
Even if it is not ``0'', transmission efficiency inevitably decreases with data in which a large proportion of 1'' occurs. By the way, 96'
When transmitting all °′1” data using a communication channel of OObit/s, the actual amount is 8000 bit/+
It had to be a degree.

[Problems to be solved by the invention] - As mentioned above, in the conventional HDLC or SDLC communication system, in order to maintain data transparency (transbearing range), fields other than flag field F are 0
There was a problem in that the transmission efficiency decreased due to insertion processing.

[Means for solving problems]

The communication control method of the present invention for solving the above problems is as follows:
A communication control device employing an HDLC communication method or an SDLC communication method includes a memory section for storing data to be transmitted, a data inversion section for inverting the data to be transmitted, output data of the memory section and the data. Regarding the output data of the inverting section.

first and second continuous 1 detection sections that respectively emit first and second pulse outputs when five 'l's occur in succession; The first and second counter units that output the first and second count value outputs compare the first count value output and the second count value output, and the first count value output is compared with the second count value output. When the second count value output indicates a smaller value than the first count value output, the output data of the memory section is used, and when the second count value output indicates a smaller value than the first count value output, the data of the output of the data inversion section is actually used. The device is characterized in that it has means for outputting data to a line.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a communication control device showing the configuration of an embodiment of the present invention. Input a sent from another section as data to be transmitted is stored in the memory section 11. Reading of the memory section 11 is started by the control section 12 and inputted to the consecutive 1 detection section 13 and the data inversion section 14 .

The consecutive 1 detecting section 13 checks the data input to the memory section 11, and generates a pulse b once when there are five consecutive 1's.The output of the consecutive 1 detecting section 13 is counted. The counter unit 15 calculates the number of times O should be inserted.On the other hand.

In the data input to the data inversion unit 30, "'0" is 1
", and to 1 n is inverted to tt O"", and the output pulse C of the continuous 1 detection section 16 is counted by the counter section 17, and the number of times that 0 should be inserted with respect to the 1 inverted data is determined. Counter section 15 and 17 count value output du
e is input to the comparator circuit section 18, and when the count value output d of the counter section 15 indicates a smaller value than the count value output e of the counter section 17, to 1 n, the count value output e is a smaller value than the count value output d. When it indicates, a comparison output f which becomes "pa0" is generated.

When the output f of the comparison circuit 18 is l'', the selection circuit section 19 selects the output g of the memory section 11 as is.

When it is OII, select the output of the data inversion section 14.

When the reading from the memory section 11 is completed, the control section 12 fixes the selection direction of the selection circuit 19. this
When the control unit 12 starts reading the memory unit 11 again in the i state, the selection circuit 12 selects the one with fewer 0 insertions among the output g of the memory unit 11 as it is and its inverted data. HDL
The signal is sent to the communication line as an output from the modulation/demodulation section 21 via the C or SDLC frame configuration section 20. Therefore, between the data in the memory unit 11 as it is or the inverted data, the data with fewer '0's to be added for 0 insertion is always sent out as data in the HDLC or SDLC frame.

The above raw data or inverted data selection is shown in Figure 1 + 7)
It may be executed for all fields A, C, I, and Fe2, but it may also be applied to only some of them, for example, F field. Furthermore, it may be applied to only a further portion of the I field.

Methods for notifying the receiving side that the data has been reversed include a method of notifying the receiver using a communication control procedure before transferring the data, a method of notifying the receiver using another communication method,
A field or C if positive/inverted only within the field
There is a method of notifying by indicating this in a field.

〔Effect of the invention〕

As explained above, one aspect of the present invention is that it is possible to minimize the reduction in transmission efficiency caused by O insertion processing in HDLC or SDLC communication systems, and it is possible to realize efficient transmission on a transmission path.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a communication control device showing an embodiment of the present invention, Fig. 2 is a diagram showing a frame format of HDLC or SDLC communication system, and Fig. 3 is a processing method of O insertion processing and transmission/reception data. FIG. 4 is a diagram showing an example of the relationship between the processing method of O insertion processing and transmission/reception data. Explanation of symbols: 11 is a memory section, 12 is a control section. 13 is a continuous 1 detection section, 14 is a data inversion section, 15 is a counter section, 16 is a continuous 1 detection section, 17 is a counter section, 18
19 is a comparison circuit, and 19 is a selection circuit. Reference numeral 20 denotes a frame configuration unit, 21 a modulation/demodulation unit, a, data to be transmitted, b, c, pulse outputs, and d, e, count value outputs, respectively. Agent (7783) Patent attorney Noriyasu Ikeda also 2 Figure F: Flag λ-ru and (01111110 with 2 captives)
A: Atsushi Field C: Satoshi “Strike Field ■: Su I Ran Field FCS: Fushi-Muchieraki Twield ttn
. [〒 −2 −. 1 L; Akira 4 figure ≦2. : 0 year old fist inserted Oteta F near 7 gfould+01llIIIO11111
1111 Jin transmission valve

Claims (1)

[Claims] 1. In a communication control device applying an HDLC communication method or an SDLC communication method, a memory section that stores data to be transmitted, a data inversion section that inverts the data to be transmitted, and output data of the memory section and Regarding the output data of the data inversion unit, first and second continuous 1 detection units that respectively generate first and second pulse outputs when five “1”s are consecutive; and the first and second pulse outputs. first and second counter units that count outputs and output first and second count values, respectively, compare the first count output and the second count output, Numerical output is the second
When the second count value output indicates a smaller value than the first count value output, the output data of the memory section is actually used, and when the second count value output indicates a smaller value than the first count value output, the output data of the data inversion section is actually used. 1. A communication control method comprising: means for outputting data to a line.