JPS6251038B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A beam-indexed color television receiver has a single electron beam as a picture tube, with red, green and blue color phosphor stripes arranged horizontally. An index that has a fluorescent surface and index phosphor stripes arranged horizontally on the inner surface of the phosphor surface is used, and is obtained by scanning the index phosphor stripes with an electron beam. Color switching is performed based on the signal, and when the electron beam scans the red color phosphor stripe, the red primary color signal is used.
When scanning a green phosphor stripe, a green primary color signal is used, and when a blue phosphor stripe is scanned, a blue primary color signal is used for density modulation.

In this case, the method of arranging the index phosphor stripes is to form, for example, three index phosphor stripes for every two sets of red, green, and blue color phosphor stripes. There is a method in which the pitch of the index phosphor stripe is not made an integral multiple of the pitch of a set of color phosphor stripes, and according to this method, the phase of the index signal is shifted depending on the color to be reproduced. The advantage is that there are no problems.

However, according to this method, the index phosphor stripe does not exist in a uniquely defined position relative to each color phosphor stripe, so the index signal is supplied to a PLL circuit, for example, and the frequency is multiplied to determine the color. A signal with a frequency three times the so-called triplet frequency determined by the pitch of a set of phosphor stripes and the scanning speed of the electron beam is obtained, and this signal is fed to a 1/3 frequency divider to gate, for example, the primary color signal of each color. At the beginning of the horizontal scan, each gate signal gates the primary color signal of the corresponding color at the position of the color phosphor stripe of the corresponding color. It is necessary to control so that

The present invention makes it possible to stably and reliably perform phase matching of the color switching signal with respect to the color phosphor stripe, that is, so-called mode setting, using an extremely simple method.

FIG. 1 shows an example of a beam index type color television receiver according to the present invention, and 10 is a beat index type color picture tube, for example, as shown in FIG. Effective screen portion 11 where body stripes R, G and B are formed
An index phosphor stripe I is formed at a pitch of 4/3 of the pitch of a set of color phosphor stripes R, G, and B over the horizontal scanning start part 12 on the left side of the index phosphor stripe. Photodetector 2
0 is set.

Then, the horizontal blanking pulse H _B is supplied to the set input of the RS flip-flop circuit 81,
At the trailing edge of the pulse H _B shown by the arrow, the circuit 81 is set and its output signal SW becomes "1", and this output signal _SW is supplied to the switch circuit 70W, and the circuit is activated during the "1" period. 70 W is turned on, a pre-adjusted value of DC voltage from the variable voltage source 71 is supplied to the first grid 13 of the picture tube 10, and the electron beam is scanned in the above-mentioned horizontal manner with a relatively large constant beam dose. The starting part 12 is scanned, and the light from the index phosphor stripe I of the horizontal scanning starting part 12 is detected by the photodetector 20.

The output signal of this photodetector 20 is passed through a bandpass filter 31 and a phase shifter 32 for phase adjustment, so that the index phosphor stripe I
An index signal S _I with a frequency f _I determined by the pitch of the PLL and the scanning speed of the electron beam is obtained.
It is supplied to circuit 40.

In the PLL circuit 40, the index signal S _I is supplied to the phase comparator 41, and the output signal of the voltage controlled oscillator 42 is supplied to the frequency divider 43 and divided into 1/N or 1/4 in the case of FIG. The frequency-divided signal is supplied to the phase comparator 41, and the output voltage of the phase comparator 41 is supplied to the oscillator 42 through the low-pass filter 44.

On the other hand, the horizontal blanking pulse H _B is applied to the set input of another RS flip-flop circuit 82, and the trailing edge of the pulse H _B sets the circuit 82 so that its output signal P _S becomes "1", and The index signal S _I from the phase shifter 32 is supplied to a Schmitt trigger circuit 83, for example, to obtain an index pulse P _I , which is supplied to the reset input of the flip-flop circuit 82, and the pulse P I is supplied to the reset input of the flip-flop circuit 82.
The first rising edge of _I resets the circuit 82 and its output signal P _S goes to "0".

The output signal P _S of the flip-flop circuit 82 is then supplied to the oscillator 42 of the PLL circuit 40.
The oscillation phase of the oscillator 42 is regulated. That is,
As shown in FIG. 3, the horizontal blanking pulse H
During the period when the signal P _S is "1" from the trailing edge of _B to the first rising edge of the index pulse P _I , the oscillator 42 stops oscillating and its output signal S _O maintains the state of "0". However, when the signal P _S becomes "0" at the first rise of the index pulse P _I ,
The oscillator 42 starts oscillating and its output signal S _O
starts to alternately repeat the state of "0" and "1", and therefore the phase of the output signal S _O with respect to the index pulse P _I is determined as shown in the figure.

Furthermore, the output signal P _S of the flip-flop circuit 82 is also supplied to the frequency divider 43 of the PLL circuit 40, and the state of the frequency divider 43 is regulated at the same time. That is, when the picture tube 10 is configured as shown in FIG. 3 and the frequency divider 43 is a 1/4 frequency divider, the frequency divider 43 is configured with a two-stage flip-flop circuit. , the flip-flop circuit in the previous stage is triggered by the fall of the output signal S _O of the oscillator 42, and the output signal of the flip-flop circuit in the previous stage is
At the falling edge of _F1 , the flip-flop circuit in the subsequent stage is triggered, and during the period when the signal P _S is "1", the flip-flop circuit in the previous stage is preset and its output signal F1 is set to "_1" , and the flip-flop circuit in the subsequent stage is preset to "1". The flip-flop circuit is cleared and its output signal F _R is set to "0".

In this way, the output signal P _S of the flip-flop circuit 82 determines the phase of the output signal S _O of the oscillator 42 with respect to the index signal S _I , and the state of the frequency divider 43 is regulated, so that the index pulse At the time of the first rise of P _I , the reference signal F _R from the frequency divider 43 becomes exactly 90 degrees behind the index signal S _I as shown in the figure, and the PLL circuit 40 immediately locks. I come to do it.

When the PLL circuit 40 locks, its oscillator 42
The output signal S _O is four times the index signal S _I , that is, three times the triplet frequency, as shown in the figure.
At twice the frequency of 3f _T , the falling edge appears in the middle after each color phosphor stripe R, G, and B (assuming that they are formed extending from the effective screen area 11, although they are not in the horizontal scanning start area 12). The phase will be at the position of .

The output signal S _O of this PLL circuit 40 is applied to the 1/3 frequency divider 5
0, resulting in three gate signals P _R , P _G and P _B to gate the red, green and blue primary color signals, and in this case the output signal P _S of the flip-flop circuit 82 described above is Furthermore, it is supplied as a mode set pulse to this 1/3 frequency divider 50, and the phases of the three gate signals P _R , P _G and P _B are adjusted by the signal P _S .

That is, as shown in FIG. 2, for example, the 1/3 frequency divider 50 is composed of a ring counter having three stages of JK flip-flop circuits 50R, 50G, and 50B, and the output signal S _O of the PLL circuit 40 is The Q outputs of the circuits 50R, 50G and 50B are used as gate signals P _R , P _G and P _B to gate the primary color signals of red, green and blue. The output signal P _S of the flip-flop circuit 82 is inputted to the preset circuit 50R, and the circuits 50G and 50B
During the period of “1” of the signal P _S , the circuit 50R is preset and the gate signal P
_R is set to "1" and circuits 50G and 5
When 0B is cleared and the gate signals P _G and P _B are set to "0", and the signal P _S becomes "0" at the first rising edge of the index pulse P _I , each output is changed at each falling edge of the signal S _O. Shifted, the gate signals P _R , P _G and P _B are applied to the red, green and blue color phosphor stripes R, G and B (not in the horizontal scanning start part 12 but extending from the effective screen part 11 ), respectively. assuming that it is formed) becomes position ``1''.

On the other hand, the index pulse P _I from the shot trigger circuit 83 is supplied to the clock input of the counter 84, and the horizontal blanking pulse H _B is supplied to the clear input of the counter 84, so that after the trailing edge of the pulse H _B , the index pulse P I is supplied to the clock input of the counter 84. The falling edge of pulse P _I is counted. When, for example, the second falling edge of the index pulse P _I at the end position of the horizontal scanning start section 12 is counted, a pulse is obtained from the counter 84, and this pulse is input to the reset input of the flip-flop circuit 81. The circuit 81 is reset, its output signal _SW becomes "0", and the switch circuit 70
W turns off.

The three gate signals P _R , P _G and P _B from the 1/3 frequency divider 50 are supplied to the gate circuit 60, and the output signal _SW of the flip-flop circuit 81 is supplied to the gate circuit 60 as a gate signal. ,
During the "0" period of the signal _SW , that is, in the effective screen section 11, the gate signals P _R , _PG and _PB are taken out as gate signals G _R , _GG and _GB , and these are sent to the switch circuits 70R, 70G and 70B to switch circuits 70R, 70G and 7 at the locations of red, green and blue color phosphor stripes R, G and B.
0B turns on and the red, green and blue primary color signals E
_R , E _G and E _B are extracted and the switched primary color signals are supplied to the first grid 13 of the picture tube 10.

FIG. 4 shows the effective screen area 11 in the picture tube 10.
This is a case where the index phosphor stripe I is formed at 2/3 of the pitch of a set of color phosphor stripes R, G, and B over the horizontal scanning start portion 12.

In this case as well, as shown correspondingly in FIG. 3, during the "1" period of the signal P _S from the trailing edge of the horizontal blanking pulse H _B to the first rise of the index signal P _I , the oscillator 42 is activated. Stops oscillation and maintains the output signal S _O at “0”,
When the signal P _S becomes "0" at the first rising edge of the index pulse P _I , the oscillator 42 starts oscillating, and the output signal S _O alternately repeats "0" and "1" states. The phase of the output signal S _O with respect to the index pulse P _I is determined as shown in the figure.

Furthermore, in this case, the frequency divider 43 is a 1/2 frequency divider and is composed of one flip-flop circuit, but this flip-flop circuit is triggered by the rise of the output signal S _O of the oscillator 42, and the signal During the period when P _S is "1", this flip-flop circuit is cleared and its output signal F _R is set to "0".

As a result, as in the case of FIG. 3, the reference signal F _R from the frequency divider 43 has a phase of just 90° with respect to the index signal S _I at the time of the first rise of the index pulse P _I. This causes the PLL circuit 40 to lock immediately.

When the PLL circuit 40 locks, its oscillator 42
The output signal S _O is twice the index signal S _I , that is, three times the triplet frequency, as shown in the figure.
At twice the frequency _3fT , the rising edge of each color phosphor stripe R, G, and B (assuming that they are formed extending from the effective screen area 11, although not in the horizontal scanning start area 12), is then reflected in the intermediate area. It becomes the phase that comes to the position.

Then, the output signal S _O of this PLL circuit 40 is 1/3
The gate signals P _R , P _G and P _B are obtained by being supplied to the frequency divider 50, and the gate signal P _R is set to "1" during the period when the output signal P _S of the flip-flop circuit 82 is "1". , gate signals P _G and P _B
is set to ``0'', but in this case, each output is shifted every time the signal S _O rises, and the gate signals P _R , P _G and P _B are also set to red, green and blue color phosphors respectively. It becomes "1" at the positions of stripes R, G, and B (assuming that they are formed extending from the effective screen area 11, although they are not in the horizontal scanning start area 12).

As in the example of FIG.
PLL instead of index pulse P _I from 3
The reference signal F _R from frequency divider 43 of circuit 40 is applied to the clock input of counter 84, and the output signal P _S of flip-flop circuit 82 is applied to the clear input of counter 84 instead of the horizontal blanking pulse H _B . Therefore, the rising or falling edge of the reference signal F _R may be counted after the falling edge of the output signal P _S .

Note that the output signal P of the flip-flop circuit 82
_S is further a low pass filter 44 of the PLL circuit 40
Alternatively, by being supplied to the phase comparator 41, the electric charge of the low-pass filter 44 becomes zero during the "1" period of the signal P _S , and thus at the time of the first rise of the index pulse P _I. If this is done, the PLL circuit 40 will lock more quickly.

According to this invention, the first index signal at the horizontal scanning start end of the picture tube is detected, the detected signal is used to match the phase of the signal that is compared with the index signal in the PLL circuit, and the PLL circuit is immediately locked. In addition, since the same detection signal is used to align the phase of the color switching signal with respect to the color phosphor stripe, there is an advantage that stable and reliable mode setting can be performed without the need to adjust the timing as in the conventional method. .

[Brief explanation of the drawing]

FIG. 1 is a system diagram of an example of the receiver of the present invention, FIG. 2 is a connection diagram of a specific example of a part thereof, and FIGS. 3 and 4 are waveform diagrams for explaining its operation, respectively.
FIG. 5 is a system diagram of the main parts of another example of the receiver of the present invention. 10 is a picture tube, 20 is a photodetector, 31 is a bandpass filter, 40 is a PLL circuit, 41 is its phase comparator, 42 is its voltage controlled oscillator, 43 is its frequency divider, 50 is 1/3 frequency division 81 and 82 are RS flip-flop circuits, 83 is a Schmitt trigger circuit, and 84 is a counter.

Claims (1)

[Claims] 1 In a picture tube, the index phosphor stripe is formed at a pitch that is not an integral multiple of the pitch of a set of color phosphor stripes, and the index signal is
In a device in which the output signal of this PLL circuit is supplied to a frequency divider to obtain a color switching signal, the first index signal at the start end of horizontal operation of the picture tube is provided separately from the PLL circuit. The signal is detected by the detection circuit, and the detection signal is supplied to the PLL circuit, and the phase of the signal is matched with the index signal, and the color switching signal is detected by the frequency divider. A beam index type color television receiver in which phase alignment is performed for stripes.