JPS6224971B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PLL circuit used in a beam index type color television receiver or the like.

A beam-indexed color television receiver has a single electron beam as a picture tube and a phosphor surface with red, green and blue colored phosphor stripes arranged horizontally; The index phosphor stripes arranged horizontally on the inner surface of the phosphor surface are used, and the colors can be switched based on the index signal obtained by scanning the index phosphor stripes with an electron beam. when the electron beam scans the red color phosphor stripe with a red primary color signal;
When scanning a green phosphor stripe, a green primary color signal is used, and when a blue phosphor stripe is scanned, a blue primary color signal is used for density modulation.

As for signal processing for this purpose, for example, the output signal of the photodetector is supplied to a bandpass filter, and an index signal with a frequency f _I determined by the pitch of the index phosphor stripe and the scanning speed of the electron beam is extracted. The index signal is supplied to a PLL circuit, which is synchronized in phase with the index signal and at a frequency 3f _T which is three times the so-called triplet frequency f _T determined by a set of pitches of the color phosphor stripes and the scanning speed of the electron beam. A signal is obtained and this signal is divided by a ring counter to obtain a three-phase gating signal for gating the red, green, and blue primary color signals, respectively, regulated by the mode set pulse; A method is used in which the primary color signals are sequentially gated and the switched primary color signals are applied to the picture tube.

In the PLL circuit, as shown in FIG. 1, an input index signal S _I is supplied to a phase comparator 101, an output signal S _O of a voltage controlled oscillator 102 is supplied to a frequency divider 103, and is divided into 1/N. For example, in a type in which three index phosphor stripes are formed for every two sets of color phosphor stripes, so that f _I =3/2f _T , the frequency is divided into 1/2; The signal is supplied to a phase comparator 101, and the output voltage of the phase comparator 101 is supplied to an oscillator 102 through a low pass filter 104.

In this case, the PLL circuit is designed to lock to the frequency f I of the input index signal S _I even when the scanning speed of the electron beam changes during the horizontal scanning period and the frequency f _I of the input index signal S I fluctuates, and when the beam current is small. It is necessary to increase the hold range in consideration of the fact that the index signal becomes smaller and the loop gain becomes smaller.

Incidentally, the free-running frequency of the voltage controlled oscillator 102 drifts due to temperature changes and changes over time, and the output voltage of the phase comparator 101 similarly drifts due to temperature changes and changes over time. Therefore, it is necessary to take these drifts into consideration when designing the hold range.

To achieve this, the loop gain of the PLL circuit can be increased to allow for these drifts and to provide sufficient margin for the hold range. However, when the loop gain is increased, the influence of noise included in the input increases, and the phase of the index signal S _I changes depending on the color to be reproduced, causing the beam scanning position to shift, resulting in poor image reception. There is a disadvantage that parasitic oscillation occurs in the entire loop including the tube, and vertical stripes appear on the screen.

In view of this point, the present invention firstly provides a PLL
The hold range can be increased without increasing the loop gain of the circuit, regardless of the free-running frequency of the voltage controlled oscillator or the drift of the output voltage of the phase comparator.

In order to suppress the influence of the free-running frequency drift of the voltage controlled oscillator, a method as shown in FIG. 2 can be considered. That is, the output voltage of the low-pass filter 104 is further supplied to the level comparator 106 through another low-pass filter 105, and the level is compared with the reference voltage V _O , and the output voltage of the level comparator 106 is voltage-controlled together with the output voltage of the low-pass filter 104. oscillator 102. Here, the low- _pass filter 104 has a sufficiently small time constant, that is, a sufficiently high cutoff frequency, as shown in FIG. On the other hand, the low-pass filter 105 has a time constant as large as one field to several fields, that is, a cutoff frequency that is sufficiently low, as shown in FIG.

According to this method, the loop gain in the low frequency range of the PLL circuit is increased, the oscillation center frequency of the voltage controlled oscillator 102 is matched to the average frequency of the input index signal S _I , and the free-running frequency of the oscillator 102 drifts. The hold range will be expanded regardless of the situation.

However, this method
This is effective when there is no or little drift in the output voltage, but it becomes inconvenient when the drift exceeds a certain level.

In order to eliminate the influence of the drift of the output voltage of the phase comparator 101, the value of the reference voltage V _O shown in the figure may be changed in accordance with the drift. The drift of the output voltage of the phase comparator 101 is mainly due to temperature changes, and therefore the drift of the output voltage of the phase comparator 101
If the source of the reference voltage V O and the reference voltage V _O are configured on the same integrated circuit, the value of the reference voltage V _O will change in accordance with the drift of the output voltage of the phase comparator 101, and the drift can be considered to be compensated for. however,
Considering variations in integrated circuits, this is only compensated for in the design, and in order to absorb these variations, an adjustment circuit is required outside the integrated circuit.

In view of this point, the second object of the present invention is to eliminate the influence of the drift of the free-running frequency of the voltage controlled oscillator and the output voltage of the phase comparator without adjustment.

Even if the frequencies of the two inputs of the phase comparator are the same and the phase difference between them is 90 degrees, the output voltage will drift due to temperature changes, as described above. By the way, the output voltage when one of the two inputs of the phase comparator has no signal is the same as the output voltage when the phase difference between the two inputs of the phase comparator is 90° at any temperature. be equal. In a beam index type color television receiver, the picture tube is cut off during the horizontal and vertical retrace periods, so the index signal S _I , which is the input to the PLL circuit, cannot be obtained.

This invention focuses on this point, and the phase comparator 1
The drift of the output voltage of the phase comparator 101 is detected from the output voltage during the horizontal and vertical retrace periods when the index signal S _I of 01 is not obtained, and the output voltage during these horizontal and vertical retrace periods is sampled and held. is used as the reference voltage V _O mentioned above.

FIG. 4 shows an example of a beam index type color television receiver using the PLL circuit of the present invention, in which numeral 10 is a picture tube, and the effective screen area on which color phosphor stripes are formed and the horizontal scanning area on the left side thereof. An index phosphor stripe is formed at a constant pitch across the starting section, and a photodetector 20 is provided on the outside of the funnel section.

Then, the horizontal and vertical blanking pulses P _B (FIG. 5A) are supplied to the switch circuit 80, and the switch circuit 80 is turned off during the "1" period, that is, the horizontal and vertical retrace periods. The picture tube 10 is cut off, and the switch circuit 80 is turned on during the "0" period, that is, during the horizontal scanning period within the vertical scanning period.

The blanking pulse P _B is supplied to the reset input of the counter 120, and at the falling edge of the pulse P _B , that is, at the beginning of the vertical scanning period, the counter 12
The output signal _SW of 0 (Fig. 5B) becomes "1",
This output signal _SW is supplied to the switch circuit 60, and during the "1" period, the switch circuit 60 is switched to the input W side, and a DC voltage of a pre-adjusted value from the variable voltage source 70 is received. The first of the tubes 10
The electron beam is supplied to the grid 11 and scans the above-mentioned horizontal scanning start section with a relatively large constant beam amount, and the light from the index phosphor stripe at the horizontal scanning start section is detected by the photodetector 20. Ru.

The output signal of this photodetector 20 is supplied to a bandpass filter 30 to obtain an index signal S _I , which is supplied to these PLL circuits 100.

The PLL circuit 100 is configured as described below, and when it is locked, a signal with a frequency of 3f _T whose phase is synchronized with the index signal S _I is obtained as the output signal S _O of the voltage controlled oscillator 102 as described above. It will be done. The output signal S _O of this PLL circuit 100 is then supplied to a gate signal generator 40 consisting of a ring counter.

On the other hand, the index signal S _I from the bandpass filter 30 is transmitted to the Schmitt trigger circuit 9, for example.
0 to obtain the index pulse P _I (FIG. 5C), which is fed to the clock input of counter 120 and counted. And PLL
When the pulse corresponding to the last index phosphor stripe at the start of the horizontal scan described above is counted after the circuit 100 is locked, the output signal S _W of the counter 120 falls to "0" and the switch circuit is activated. 60 is switched to the input C side.

The output signal S _W of this counter 120 is supplied to _the gate signal generator 40 as a mode set pulse. When the output signals S _R , S _G and S _B are set to predetermined states, and the output signal S _W becomes "0", that is, when the valid screen area is reached, the output signal S
_R , S _G and S _B become "1" at the red, green and blue color phosphor stripes, respectively, which are obtained by dividing the output signal S _O of the PLL circuit 100 by 1/3.

The output signals S _R , S _G and S _B of the gate signal generator 40 are used as gate signals to gate the primary color signals of red, green and blue to the switch circuit 50 .
R, 50G, and 50B, switch circuits 50R, 50G, and 50B are turned on at the red, green, and blue color phosphor stripes;
Green and blue primary color signals E _R , E _G and E _B are taken out sequentially, and the switched primary color signals are sent to the picture tube 1.
0 to the first grid 11.

In the PLL circuit 100, the bandpass filter 30
is supplied to the phase comparator 101, and the output signal S _O of the voltage controlled oscillator 102 is supplied to the frequency divider 103.
The divided signal is supplied to the phase comparator 101, and the output voltage of the phase comparator 101 is supplied to the oscillator 102 through a low-pass filter 104 with a small time constant as shown in FIG. 3A. .

Further, the output voltage of the phase comparator 101 through the low-pass filter 104 is supplied to the switch circuit 111, and the horizontal and vertical blanking pulses P
_B is supplied to the switch circuit 111, and the switch circuit 111 is turned on during the "1" period of the blanking pulse P _B , that is, the horizontal and vertical retrace periods, and the horizontal and vertical retrace lines of the phase comparator 101 are turned on. The output voltage during the period is taken out and this is applied to the resistor 1
The capacitor 113 is charged through the capacitor 12. That is, the index signal S of the phase comparator 101
The output voltage during the horizontal and vertical retrace periods where _I cannot be obtained is sampled and held. The sampled and held voltage is then supplied to the level comparator 106 as a reference voltage.

Further, the output voltage of the phase comparator 101 through the low-pass filter 104 is connected to another switch circuit 114.
The horizontal and vertical blanking pulses P _B and the output signal S _W of the counter 120 are supplied to the NOR gate 130 to control the horizontal and vertical retrace periods and the horizontal scan start portion of the horizontal scan period within the vertical scan period. A signal S _C (FIG. 5D) is obtained, which is "0" during the period and "1" during the other periods, that is, the period excluding the horizontal scanning start part of the horizontal scanning period within the vertical scanning period, and this signal S _C is supplied to the switch circuit 114, and the switch circuit 114 is turned on during the "1" period of the signal S _C , that is, the period excluding the horizontal scanning start part of the horizontal scanning period within the vertical scanning period.
The output voltage of the phase comparator 101 during the period excluding the horizontal scanning start part of the horizontal scanning period within the vertical scanning period is extracted, and as shown in FIG. supplied to

The output voltage of the level comparator 106 is then supplied to the oscillator 102.

Therefore, as mentioned above, the phase comparator 101
The output voltage during the horizontal and vertical retrace periods when the index signal S _I is not obtained is different from that when the index signal S _I is obtained and the frequency of the index signal S _I and the frequency division signal of the frequency divider 103 are the same and there is a phase difference. 90
It is always equal to the output voltage when the phase comparator 1
01, the sampled and held output voltage during the horizontal and vertical retrace periods when the index signal S _I of the phase comparator 101 is not obtained is the output voltage of the level comparator 106. By using it as a reference voltage, the influence of the drift of the output voltage of the phase comparator 101 is eliminated. And like this, phase comparator 1
Without the influence of the output voltage drift of 01,
PLL in the horizontal scanning period within the vertical scanning period in which the index signal S _I of the phase comparator 101 is obtained.
The output voltage in the period after the circuit 100 is locked, that is, in the period excluding the horizontal scanning start part, is supplied to the voltage controlled oscillator 102 through the low-pass filter 105 with a low cutoff frequency, and the low-frequency loop gain of the PLL circuit 100 is increased. Therefore, the oscillation center frequency of the voltage controlled oscillator 102 is matched to the average frequency of the index signal S _I ,
The hold range becomes wider regardless of the drift of the free-running frequency of the oscillator 102.

Note that if the output signal _SW of the counter 120 is "1"
The reason why the switch circuit 114 is turned off and the output voltage of the phase comparator 101 is not taken out during the horizontal scanning start period of the horizontal scanning period within the vertical scanning period is that the PLL circuit 100 is locked during this period. This is because a transient appears in the output voltage of the phase comparator 101.

As described above, according to the present invention, the hold range can be widened without adjustment regardless of the drift of the free-running frequency of the voltage controlled oscillator or the output voltage of the phase comparator. Moreover, since only the loop gain in the low range is increased, there is no risk that the influence of noise will increase or that parasitic oscillations will occur in the entire loop including the picture tube as described above, causing vertical stripes to appear on the screen.

Note that the output voltage of the phase comparator 101 may be directly supplied to the switch circuits 111 and 114 without passing through the low-pass filter 104.

Furthermore, the present invention is not limited to use in beam index type color television receivers, but can be widely applied to cases where signal presence periods and signal loss periods periodically exist in the input.

[Brief explanation of the drawing]

Fig. 1 is a system diagram of a conventional PLL circuit, Fig. 2 is a system diagram of a PLL circuit for explaining the present invention, Fig. 3 is a diagram showing the characteristics of its low-pass filter, and Fig. 4 is a PLL circuit of the present invention. A system diagram of an example of a beam index type color television receiver using a circuit,
FIG. 5 is a waveform diagram for explaining the operation. 101 is a phase comparator, 102 is a voltage controlled oscillator, 104 is a low-pass filter with a small time constant,
105 is a low-pass filter with a large time constant; 10
6 is a level comparator.

Claims (1)

[Claims] 1 comprises a voltage controlled oscillator and a phase comparator that compares the phase of the output of the voltage controlled oscillator with an input in which signal presence periods and signal missing periods periodically exist, and the output voltage of this phase comparator has a time constant. The voltage controlled oscillator is supplied to the voltage controlled oscillator through a small low-pass filter, and the output voltage of the phase comparator during the signal presence period is taken out through the low-pass filter with a large time constant, and the output voltage of the phase comparator during the signal missing period is The level is compared with that sampled and held, and the comparison output voltage is given to the voltage controlled oscillator.
PLL circuit.