JPS6250992B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor photoelectric conversion device.

2. Description of the Related Art Photoconductive photodetectors, photodiodes, phototransistors, and the like are conventionally known as semiconductor photoelectric conversion devices. A phototransistor has a structure similar to that of a conventional transistor, and controls emitter current by accumulating carriers generated by light in the base region of the transistor.

On the other hand, the present inventor proposed a static induction transistor that can exhibit unsaturated current-voltage characteristics in contrast to conventional bipolar transistors and field effect transistors that exhibit saturated characteristics (Patent No.
968336 (Special Publication No. 52-6076) "Field-effect transistor", Patent No. 968337 (Special Publication No. 17720-1972)
``Field-effect transistor'') has achieved various developments.

Static induction transistors have extremely low series resistance from the source to the intrinsic gate (where the drain current is essentially controlled).
Has high conversion conductance.

Also, if a potential barrier is created at the intrinsic gate,
The height of the potential barrier can be controlled by both the gate potential and the drain potential, which is the reason why it can exhibit unsaturated characteristics. Furthermore, the gate capacitance can be made extremely small, making it suitable for high-speed, low-power operation.

An object of the present invention is to provide a highly sensitive semiconductor photoelectric conversion device using the principle of a static induction transistor.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a circuit diagram for explaining a basic embodiment of the present invention, in which the source of an n-channel junction type static induction phototransistor Q is grounded, and the drain is connected to a positive voltage source V _B through a load resistor R. It is connected to the. An output terminal V _put is connected to the midpoint between the drain and the load resistor R. When light h _v irradiates the electrostatic induction phototransistor and electron-hole pairs are generated in the channel, at least some of the generated holes are accumulated in the p-type gate region and the gate potential V
Increase _G. The electromotive force caused by this light irradiation is shown as a variable voltage source V _G in the form of a transparent circuit. Since the output (drain) voltage V _put changes depending on the gate potential V _G generated by light irradiation, the amount of irradiated light can be known.

FIG. 2 shows the characteristics of a static induction phototransistor in which the channel is sufficiently pinched off with zero gate bias. In FIG. 2, g ₁ to _{g 4} are curves due to changes in the amount of light, and l ₁ and l ₂ are load curves when the power supply voltage is changed. There is no light irradiation, and the diffusion potential due to the pn junction remains as it is at the gate.
The characteristic when the channel is sufficiently pinched off between channels is _g4 , and a certain drain voltage _Vth is required to lower the potential barrier of the inherent gate and start flowing current.

Upon irradiation with light, the holes generated are accumulated in the gate region and bias the gate in the forward direction. That is, the sum of the diffusion potential and the electromotive force generated by light irradiation is generated between the gate and the channel. The generated electromotive force is determined by the amount of light, that is, the amount of charge accumulated in the gate region and the gate capacitance. As the amount of irradiation light increases, the characteristic curve changes from g ₃ to g ₂ to g ₁ . g ₂ corresponds to a state where a neutral region begins to appear in the channel, and at g ₁ the channel has a resistive characteristic.

FIG. 3 shows an embodiment of a phototransistor used in the configuration of FIG. n ^- on n ⁺ type Si substrate 1
A type epitaxial layer is grown, and a p ⁺ type gate mesh region 3 is formed thereon. Furthermore, an n ^-type epitaxial layer 4 is grown on top of that, and a thin layer is formed on the surface.
An n ⁺ type layer 5 is formed. Metal electrodes 11 and 15 are formed on the entire back surface of the substrate 1 and around the upper surface of the n ⁺ type layer 5. A portion 6 surrounded by the electrode 15 becomes a light receiving portion.

The substrate 1 is used as a source, and the n ⁺ type layer 5 is used as a drain. The thickness of the n ⁺ type layer 5 is small enough to reduce the attenuation of the incident light (e.g.
0.3 to 0.5 μm). The n ^- type layer 4 is a region between the gate and drain, and is a region that determines applied voltage, photosensitivity, and the like. The thickness is preferably selected so that most of the region where incident light is absorbed becomes a depletion layer and most of the holes ionized by the incident light can reach the gate region. In order to increase the breakdown voltage, it is preferable to reduce the impurity density. For example, when targeting visible light,
The impurity density is about 10 ¹⁴ cm ^-3 and the thickness is about 10 to 20 μm. The spacing of the p ⁺ type gate mesh region is
It is selected so that the depletion layers due to the diffusion potential of the pn junction overlap each other and form a sufficient potential barrier in the channel. For example, if the impurity density of the n ^- type layer forming the channel is 1 × 10 ¹⁴ cm ^-3, the impurity density of the gate region is 10 ¹⁸ cm ^-3 or more, and the mesh spacing is approximately 5μ.
Choose m or less. The n ^- type layer 2 is a region between the source and the gate, and together with the n ^- type layer 4, determines the photosensitivity. For example, impurity density 1×10 ¹⁴ cm
^-3 , choose a thickness of about 2 to 3 μm. There are not many restrictions on n ⁺ type substrates, but for example, the impurity density is 10 ¹⁸ ~
10 ²⁰ cm ^-3 is used. In order to widen the dynamic range of the output voltage, it is also good to lower the impurity density of the n ^- type layer 4 and increase the applied voltage.
When the wavelength of the light to be detected becomes longer and the absorption coefficient becomes lower, the gate-drain distance (thickness of the n ^- type layer 4) can be made thicker.

In the embodiments described above, the potential of the gate region can vary from at most zero to the diffusion potential. In order to change the gate potential over a wider range, a configuration as shown in FIG. 4 may be used.

In the configuration shown in FIG. 4, a gate region lead-out portion 3' and a gate electrode 7 insulated by an insulating layer 6 are added to the configuration shown in FIG. 3, resulting in a structure in which a bias can be applied to the gate from the outside. ing. Such a gate structure is hereinafter referred to as a capacitively coupled junction gate.

In this case, the depletion layer extending from the gate region 3 to the channel regions 4 and 2 can be expanded by applying a reverse bias to the gate electrode 7, so that restrictions on gate spacing etc. are weakened. Of the voltage applied to the gate electrode 7, the proportion of the voltage applied between the gate region 3 and the channel regions 2, 4 is mainly determined by the capacitance _C1 between the gate electrode 7 and the gate regions 3', 3 and the gate region. 3, 3' and the capacitance C ₂ between the source region 1 and the source region 1. In order to apply more voltage components to the gate region 3, it is sufficient to increase C ₁ and decrease C ₂ .

FIG. 5 shows a circuit diagram using the electrostatic induction phototransistor having the capacitively coupled junction gate shown in FIG. 4. Compared to the circuit shown in FIG. 2, the major differences are that it is an insulated gate transistor and that a reverse bias power source is added to the gate. The electrostatic induction phototransistor shown in FIG. 4 is similar to the one shown in FIG. 3 except for the external lead electrode portion of the gate. The gate region lead-out portion 3', the insulating layer 6, and the gate electrode 7 form a capacitor, and the photovoltaic gate bias power source V _G and the external reverse bias power source V _GO are connected via the capacitor. The gate part becomes an equivalent circuit as shown by the dotted line.
The characteristic curve is also similar in principle to the previous embodiment, but in this embodiment, a reverse bias can be applied externally, so there is no need for the channel to be pinched off in the zero bias state. Therefore, the degree of freedom in element design increases.

In the characteristic curves shown in FIG. 6, g ₁ to _{g 8} are curves obtained when the effective gate bias, which is the sum of the external reverse bias and the forward bias due to the photovoltaic force, is changed.

The operating range can be widened by increasing the external reverse bias. As in the previous embodiment, by changing the drain voltage source V _B , the load curve can be changed as l ₁ , l ₂ , l ₃ . For example, the drain voltage sources are V _B1 , V _B2 , V
By changing it like _B3 , it is possible to measure the drain current in a limited range from very strong light to weak light. The ability to increase sensitivity by increasing the drain voltage is a feature not found in phototransistors exhibiting saturation type characteristics.

In the embodiments described above, the minority carriers generated in the channel by light irradiation are accumulated in the gate region of the opposite conductivity type. If the gate region is made to have a floating structure, the accumulated charge is simply erased through the leakage resistor, resulting in a slow response speed.

In order to actively release the accumulated charges, a conductive path may be connected between the gate region and the source region.
When a resistor is connected, the response speed is determined by the values of the capacitance and resistance of the gate region. This resistor can be formed within the same semiconductor chip by diffusion or the like.

When a switching means is connected as a conductive path, the response speed is determined by the switching frequency. In this case, charge continues to accumulate while the switch means is off, so if it is desired to increase the sensitivity even if the response speed is slow, it is sufficient to lengthen the off period of the switch means. The switch means may be formed of a transistor or the like and integrated on the same semiconductor chip, or may be formed of a mechanical chopper or the like and attached externally.

The structure of the light receiving section is not limited to the structure of the above embodiment. For example, when forming the light-receiving surface, it may be formed on the drain side, the source side, or any other location. It is sufficient that sufficient light can be introduced into the active region in the operating state.

The electrode structure when the electrode is arranged on the light-receiving surface side as in the above embodiment is not limited to that shown in the drawings. The electrodes may have a stripe or mesh shape, or a transparent electrode may be provided over the entire light receiving surface.

In particular, the impurity density and dimensions of the channel region are selected to be, for example, about 10 ¹⁴ /cm ³ and the width of the channel region sandwiched by the gate region is 5 μm or less. The width of this channel region is the width of the n ^- region in the finished state between the p ⁺ gate and the p ⁺ gate when the SIT has a buried gate structure as shown in Figures 3 and 4. It is. Alternatively, when the SIT is a planar gate or other gate structure such as a notched gate structure, it is the width of the n ^- channel region in the finished state sandwiched by the gate.

Semiconductor materials are not limited to Si, but also include semiconductors that have a narrow bandgap (for example,
Ge, P _b1-x Sn _x Te (S, Se), Hg _1-x Cd _x Te, etc.) can be used, or for shorter wavelength optical measurements, a semiconductor with a wide bandgap (e.g. GaAs, etc.) can be used. It can also be used. It goes without saying that all conductivity types may be reversed.

The gist of the present invention is to use a static induction transistor as a photodetector, accumulate carriers ionized by incident light in the gate region, and extract the intensity of the incident light as an electrical signal by changing the effective gate voltage. . In particular, if the gate is a capacitively coupled junction gate, the operating range will be expanded, making it suitable for light detection over a wide intensity range. The term "semiconductor photoelectric conversion device" in the claims refers to an element as shown in FIGS. 3 and 4,
This refers to both the devices shown in FIGS. 1 and 5 incorporating these elements.

The basic operating principle of a conventionally known photoelectric conversion device having a junction type FET structure, as typified by Japanese Patent Laid-Open No. 49-88492, is as follows. One of the electron-hole pairs (holes in the case of an n-channel) generated by light incident on the light receiving section accumulates in the gate region, and the potential level of the gate region changes. This change in gate potential controls the width of the neutral channel,
The output signal changes. Furthermore, since the drain current saturates as the drain voltage increases, it is almost impossible to control the output using the drain voltage. Of course, the height of the gate point is not controlled by the drain voltage. In addition, when the channel region is pinched off only by the depletion layer from the gate region, the channel resistance is extremely high.
Only a very small output signal is obtained.

The semiconductor photoelectric conversion device of the present invention uses the operating principle of SIT, and the impurity density (for example, 10 ¹⁴ /cm
³ ), channel dimensions (e.g. channel spacing 5
(μm or less), etc., and therefore its operating principle is fundamentally different from that of the known junction FET structure photoelectric conversion device typified by the above-mentioned Japanese Patent Application Laid-Open No. 49-88492. The height of the potential at the gate point is controlled by the amount of light incident on the light receiving section, and in this respect it is the same as a conventionally known photoelectric conversion device having a junction type FET structure. However, the fundamental difference in operation between the semiconductor photoelectric conversion device using SIT of the present invention and the conventionally known photoelectric conversion device having a junction type FET structure lies in another point. That is, in the SIT photodetector of the present invention, as the potential at the gate point changes depending on the amount of incident light, the height of the potential barrier at the unique gate point, which is the saddle point of the potential generated in the depleted channel region, changes, and the output signal changes. can get. The SIT optical detection of the present invention controls the potential of the gate region, which has a higher potential and tends to accumulate carriers (holes in the case of an n-channel), and the specific gate point, which has a lower potential and is more likely to cause carrier injection from the source. In this case, a very high optical gain can be obtained. actually
An optical gain exceeding ¹⁰⁸ was obtained. In addition, in the semiconductor photoelectric conversion device using SIT of the present invention, the height of the potential barrier at the intrinsic gate point (not the gate point) is controlled by the electrostatic induction effect due to the drain voltage, and the output signal is exponentially changed depending on the drain voltage. It has the characteristic of increasing.

As described above, the operating principles and characteristics of the conventionally known photoelectric conversion device having a junction FET structure and the semiconductor photoelectric conversion device using the SIT of the present invention are significantly different.

Next, an example of experimental results of a semiconductor photoelectric conversion device using SIT of the present invention will be shown. used for this experiment
The SIT photodetector is a normally-off type device with an element area of 50 × 60 μm ² . The gate terminal of the SIT photodetector was left open, and the light source used to measure the dependence of the optical gain on the incident light intensity had a wavelength λ = 880 nm.
A GaAs LED was used. In addition, measurements were performed while converting the drain bias V _D from 50 mV to 3V. At drain bias V _D = 3V, the incident light intensity Pi is
An optical gain exceeding 10 ⁸ was obtained below 10 ⁻³ μW/cm ² . Another feature of the SIT photodetector is that the smaller the incident light intensity Pi, the greater the optical gain. Further, when the drain bias V _D =50 mV and 100 mV, a constant optical gain is obtained when the incident light intensity Pi is in the range of 10 ^-4 to 10 ² μW/cm ² .

Furthermore, the measurement results of the dependence of the optical gain G on the drain bias V _D will be described. The optical gain G using the incident light intensity Pi as a parameter is the drain bias V _D
It shows a tendency to increase almost exponentially as the value increases. This characteristic is unique to SIT photodetection. This is because a photoelectric conversion device having a junction FET structure exhibits a characteristic in which the optical gain G is saturated as the drain bias V _D increases.

In addition to the above experimental results, the semiconductor photoelectric conversion device using SIT of the present invention also has a low noise characteristic.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a semiconductor photoelectric conversion device according to a basic embodiment of the present invention, Fig. 2 is a characteristic diagram of the photodetecting element shown in Fig. 1, and Fig. 3 is a cross-sectional view of the structure of the photodetecting element shown in Fig. 1. , FIG. 4 is a sectional view of another structure of the photodetecting element, FIG. 5 is a circuit diagram of a semiconductor photoelectric conversion device according to another embodiment of the present invention using the photodetecting element of FIG. 4, and FIG. 5 is a characteristic diagram of the photodetecting element shown in FIG. 4. FIG.

Claims (1)

[Claims] 1. A channel region of low impurity density of one conductivity type, and a source and drain provided on both sides of the channel region for flowing a main current of the same conductivity type and high impurity density as the channel region. area and
a gate region of the other conductivity type provided in contact with the channel region and for accumulating carriers mainly generated within the channel region due to incident light and controlling the main current between the source and drain regions; a light receiving section for introducing light into a predetermined portion of the channel region, and the height of the potential at the unique gate point, which is a saddle point of the potential generated in the channel region, is determined by the amount of light incident on the light receiving section. The drain region is controlled in a capacitive manner by the voltage applied to the drain region, and the channel region is pinched off only by the depletion layer from the gate region, which is generated by the diffusion potential between the gate region and the channel region, and the channel region becomes an unsaturated type. Each region has impurity density, dimensions, and arrangement such that it can exhibit current-voltage characteristics, and in particular, the impurity density in the channel region is
10 ¹⁴ /cm ³ or so, and the width of the channel region sandwiched by the gate region is 5 μm or less. 2. Claim 1, wherein the gate region is electrically floating.
The semiconductor photoelectric conversion device described in . 3. The semiconductor photoelectric conversion device according to claim 1, comprising an insulating layer provided on the gate region and a conductive gate electrode provided on the insulating layer. 4. The semiconductor photoelectric conversion device according to claim 3, further comprising a reverse bias voltage source connected to the conductive gate electrode.