JPS6250906B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time code writing method, and more particularly to an improvement in an assemble mode editing method in an editing device for a video tape recorder (VTR).

When editing a VTR, it is necessary to control the tracking control signal (CTL signal) so that it is uniformly continuous so that the tracking is not disturbed at the joints. VCRs for editing have two types of recording functions for this purpose: insert mode and assemble mode. The former covers the entire surface of the magnetic tape in advance.
This method records the CTL signal, runs a magnetic tape in synchronization with the CTL signal, and rewrites the video or audio signal at the required location.
This is a method in which the CTL signal is also recorded in a connected manner while being newly written. For editing purposes such as connecting video and audio signals after each cut on a recording VTR, the latter method has the advantage of eliminating the need to record CTL signals on tape in advance.

SMPTE (American National Standard Time)
and Control Code for video and audio tape
For editing equipment that uses 525 line/60 field television systems), in the case of assemble editing, it is necessary to record the time code on the cue track or audio track in the same way as the CTL signal. However, the current SMPTE time code uses the biphase system, and the level transition direction of the recording pattern on the tape at a certain point always depends on the phase of the previous bit. The bit pattern on the tape cannot be determined. Even if you try to connect time codes using assemble editing, even if it is a continuous code string, it will not work on the recording VTR.
Unless you determine the phase of the connection point of the time code that has already been recorded and match it, the pattern on the tape will be discontinuous at that connection point, and even when played back, the waveform of that part will be distorted and the time code will not be correct. cannot be read. Therefore, in this case, editing is carried out by reading time codes other than the joints between cuts, and interpolating the joints from the values of the preceding and following time codes. However, with this method, when editing is performed in units of one frame, each frame becomes a joint, and in the worst case, it becomes impossible to read the time code at all. The present invention is one way to improve this.

The SMPTE time code consists of a word of 80 serial bits per frame, and FIG. 1 shows the pulse waveform of a portion of it, for example, 01101000101011. As is clear from the figure, in the SMPTE time code system, each bit is divided by a level transition, and only bit "1" has a level transition in the middle. Therefore, if the number of "0" bits in one word is an odd number, the first bit of the next word will be in opposite phase to the first bit of the previous word. Therefore, in the SMPTE time code generation circuit, 1
By assigning ``1'' or ``0'' bits to appropriate empty bits in the time code of a word, the total number of ``0'' bits in one word can always be kept even. This makes it possible to equalize the phase of the bits at the end and start points of each word, and uniquely determine the phase of the recording pattern on the tape from only the time code data, without referring to the phase of the previous word. .

In the preferred embodiment of the present invention, the empty bit position at the 63rd bit position immediately before the bit position for the sync word consisting of the last 16 bits of the SMPTE time code is filled with 1's depending on the number of previous "0" bits. ``1'' so that the total number of ``0'' bits in the word is an even number.
Or insert a "0" bit. Of course, the insertion bit position of the ``0'' or ``1'' bit may be at any vacant bit position as long as the number of ``0'' bits in the entire word can be maintained at an even number.

FIG. 2 shows an embodiment of the present invention, and FIG. 3 shows its operating waveform diagram. In the waveform diagram of FIG. 2, an even parity bit of "0" or "1" is inserted at the 63rd bit position in a word of the SMPTE time code. In the figure, 10 is
In the SMPTE time code generator, terminal 12 receives the time code data, terminal 14 receives the strobe signal for the 63rd bit position, and terminal 16 receives the first falling strobe signal at the bit break and center, respectively. A clock pulse is generated at terminal 18, and a second clock signal is generated that falls only at the boundary between bits. Figure 3 shows 80 numbers from 0 to 79.
The first clock signal (Figure 3a), the second clock signal (Figure 3b) from the 60th bit of the 60th bit to the 0th bit of the next word.
The strobe signal (Fig. 3c), the time code data (Fig. 3 d and e) and the output at the time code output terminal 20 (Fig. 3 d' and e') are shown. Third
In the figure, d and d' are examples where a "0" bit is inserted at the 63rd bit position, and e and e' are examples where a "1" bit is inserted at the same position.

The time code data generated from the SMPTE time code generator 10 at the terminal 12 is in the form of a pulse train in which each bit is high level if it is "1" and low level if it is "0".
It is applied to one input of AND gate 22.
The other input of AND gate 22 receives the strobe signal at terminal 14 inverted by inverter 24 . The strobe signal is also connected to another AND gate 26
is given to one input of Both AND gate 2
The outputs of 2 and 26 are provided to an OR gate 28 along with a second clock signal at terminal 18. OR gate 2
The output of 8 is applied to the J and K inputs of a JK flip-flop 30. The inverted clock input of flip-flop 30 receives the first clock signal at terminal 16. The Q output of this flip-flop is connected to output terminal 20 and the other input of AND gate 26.

With such a logic circuit configuration, the 63rd
When the preceding bit ends at a high level at the th bit position (Fig. 3d), the bit position shown in Fig. 3
When a "0" bit is given as shown in d', and the preceding bit ends at a low level (Fig. 3e),
A bit of "1" is applied as shown in Figure 3 e', so that a transition in the same direction always occurs at the succeeding bit position as shown in Figure 3 d' and e'. becomes possible. That is, no matter what data is before the inserted bit position (63rd bit position), the signal at the next bit position (64th bit position) always has the same phase.
In the SMPTE time code, the 64th to 79th bits are always the same data as the synchronization word bits, so as shown in Figure 3 d' and e', the word breaks are in the same direction (as shown by the arrow). (high → low) transition.

The time code generated in the manner described above can be preferably used in assemble editing. As described above, in the assemble editing mode, when a program is inserted from the master tape to the editing position of the editing tape, a new CTL signal and time address code are written in the recording side recorder. According to the feature of the present invention, it is advantageous that the state of the SMPTE time code data before the cut-in point does not necessarily need to be known at this time. However, the time code produced by the present invention must be synchronized with the readout of the timecode before the cut-in point, and this can be easily accomplished by synchronizing the generator 10 of FIG. 2 with the readout data. .
Furthermore, in implementing the present invention, the previous cut is recorded for an appropriate length (several ms to several tens of ms),
Connect the two cuts by overwriting that part in the next cut. Due to this aspect, the time code is continuous without any gaps,
The SMPTE timecode method is used in editing equipment.
More complete assembly editing is possible without sacrificing the high precision advantage of using absolute addresses.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the SMPTE time code used in the embodiment of the present invention, FIG. 2 is a configuration diagram of the embodiment of the present invention, and FIG. 3 is an operational waveform diagram of FIG. 2. In the figure, 10 is the SMPTE time code generator, 2
2 and 26 are AND gates, 24 is an inverter, 2
8 is an OR circuit, and 30 is a JK flip-flop.

Claims (1)

[Claims] 1. A phase correction bit is provided in a time code consisting of a plurality of serial bit words representing address information of the corresponding video signal, and the phase correction is performed according to the number of "0" or "1" bits in the serial bits. In a time code writing method that controls the contents of the first bit so that the last bit of a word is always in the same phase direction, the first time code corresponding to the first program to be recorded is moved from the cutout point to a predetermined point. An extra length is recorded, and a second time code corresponding to a second program that is edited and recorded following the first program from the cut-out point is superimposed on the extra recorded first time code. A time code writing method characterized in that the time code is recorded from the cut-out point.