JPS62502156A - Floating gate non-volatile field effect memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] floating dart non-volatile field effect memory device The present invention includes a first conductive layer capable of providing charge, and a region above the first conductive layer. a 70-charting layer and separated from said first conductive layer by a dielectric layer; A conductive floating dirt layer configured to conduct electricity and discharge. related to programming dart non-volatile memory devices.

Background technology Floating dart non-volatile memories are known in the prior art. They are For electrically isolated dart electrodes, or “floating darts” It works by transferring a charge of a given polarity, and the dart is then charged for a long time. The polarity of the charge present on the floating dart that acts to hold the load and control the operation of the field effect sense transistor in response to the magnitude of the field effect sense transistor. by traditional data to insert or write data into specified nonvolatile memory cells. A floating dart memory cell first undergoes an erase cycle and then It only writes to a new binary state. Unfortunately, the board and the 70-ting Repeated write/erase cycles with silicon dioxide (oxide) as dielectric between It deteriorates as it ages. Having such a floating date Degradation of durability is due to narrowing of the memory window or programming into non-volatile devices. This appears as a deterioration in the retention characteristics of the binary state. Moreover, such a device As evident by reading the prior art of (e.g., U.S. Pat. No. 4.203 ．． No. 158), the program voltage may be as high as, for example, 20V, e.g. The pulse width is quite long, such as 100 milliseconds. Such voltage and time magnitudes are It can be reduced by using a thin oxide layer, but experience shows that Such a reduction results in a corresponding reduction in the holding power and endurance of the device.

Therefore, while maintaining the holding power of the oxide separated 70-ting dart electrode device, Write/erase voltages and/or voltages required to program a rolling dart device A number of design techniques have been proposed to reduce the path width. Besides, floating Focusing on the typical endurance limits that appear on dart equipment, the holding force can be adjusted to an acceptable range. Significant efforts have been made to develop structures that increase endurance while maintaining strength. jen “Floating dirt tunnel dielectric” by Jenq et al. Properties of thin oxynitride films used” (IEDM 1982. P, 811. The method described in the paper 30.9) is based on the substrate and 70. - Thin thermally formed silicon oxide to remove oxide between the ting and dart electrodes. We propose to replace the nitride (hereinafter referred to as oxynitride) dielectric layer. ing. This paper lists oxynitride as a preferred dielectric material and Fowler as a single transfer mechanism for charge transfer to charging darts. It is proposed to maintain the Nordheim Tunnel.

Other attempts include IEDM 1982. P, 810. The cha listed in Paper 30.8'' by Chang et al. There is "oxidation-nitride oxide (ONO)" for OM. According to the paper, the preference A desirable structure is a thermal oxidation layer, thermal oxynitride from the oxide layer, and oxynitride from the oxide layer. Ultra-thin composite dielectric layer with thermal oxide from toride layer. This is also due to its charge transfer. The transport mechanism is a Famler-Nordheim tunnel through a very thin composite dielectric. .

Various composite dielectrics used in floating dart structures to improve performance The changes are IEDM1980, P, 590-593. It is described in Paper 23.4''' gradient energy, band- An EAROM cell with a gap insulator tends to have a floating structure. Gradient silicon oxynitride (oxynitride) and acid graded silicon nitrite with thermally formed oxides or nitrides dielectric consisting of either oxide (nitride) or oxynitride separated from the substrate by a body complex. The structure is a fairly thick composite dielectric. The 7cZ −Charge transfer to the ting dart is performed by avalanche injection. It is done.

Also - IEEE Transactions on Electron Devi ces.

Vot, Ed, 26. A 6. P, 906-913, June’ 1979. “Nightride-Bali” described by Ito et al. Low voltage rewriting with avalanche injection MIS (NAMIS) There is a paper called "A Possible EAROM Cell". According to this method, the dielectric material is very It consists of a thin (approximately 10 nm) thermally formed nitride layer. it is thermoformed This results in a fairly thin nitride layer. The transfer of charge to the 70-ting dart The transmission is performed by avalanche injection.

(nm), and a pool (PooLe)-7 lens ( Frenkel) Nitride with charge trapping sites through charge transfer mechanism A dielectric layer including a silicon (siticonnitride)-based dielectric layer. A 70-ting dart nonvolatile memory device is provided.

The 70-ting dart non-volatile device according to the present invention has excellent retention properties and durability. Despite having long-lasting characteristics, it is difficult to use voltages with fairly low amplitudes and narrow voltage pulses. It has been found that writing and erasing can be performed using the following methods.

Briefly explaining one embodiment of the present invention, a portion thereof is located on a conductive region of a substrate. , thin thermoformed oxide layer and thin low pressure chemical vapor deposition (LPCVD) nitride base conductively doped polycrystalline silicon (poly) separated from the substrate by a layer poly) floating dart non-volatile including floating dart electrode provides a digital memory device. As seen from this structure, through the nitride base layer The charge transfer is based on the Pour-Silankel conduction mechanism. Flow through the nitride base layer Long-term charge leakage from the tinging dirt is inhibited by the presence of the oxide dielectric layer. will be stopped. Charge transfer during write/erase occurs through Fowler-Nordheim oxide ・Performed by tunneling and pour-silankel conduction through the nitride base layer. Ru.

Additionally, another embodiment may be briefly described in which a portion thereof is located over a conductive region of the substrate. , very thin thermoformed silicon dioxide (5iLicon dioxide) ) layer and a fairly thick low pressure chemical vapor deposited (LPCVD) silicon nitride layer formed on it. with a relatively thin LPGVD oxide or oxynitride base layer. conductively doped polycrystalline silicon (pony) separated from the substrate Floating dart non-volatile memory device containing 70-ting dart electrodes Provide location. Due to such a structure, oxidants and oxynitrite The charge layer follows 7 Auler-Nordheim charge tunneling and charges pass through the fairly thick nitride. The transfer is performed using a Pouleux-Sillanquer conduction mechanism. Thereby, nitriding Charge transfer to the material layer is inhibited by the oxide or oxynitride layer; Fowler Nordheim tunnels through oxides or oxynitrides The conduction of charges is controlled by the Pour-silankel conduction properties of the inserted nitride layer. and restricted.

Brief description of the drawing Next, one embodiment of the present invention will be described by way of example with reference to the accompanying drawings.

FIG. 1 shows an expanded view of a memory cell layout constructed in accordance with the principles of the present invention. It is a large plan view.

FIG. 2 is a cross-sectional view of FIG. 1 taken along line 2--2.

FIG. 3 is a cross-sectional view of FIG. 1 taken along line 3--3.

FIG. 3A is a cross-sectional view of an alternative embodiment for the charge transfer region.

FIG. 4 is an electronic circuit equivalent diagram of the memory cell of FIG.

FIG. 5 is a diagram representing the write/erase characteristics of a memory cell of the form shown in FIG.

FIG. 6 is a diagram representing the retention/endurance characteristics of the memory cell of FIG. 1.

FIG. 7 shows a photoringraph mask/mother pattern of an alternative embodiment of a cell according to the invention. FIG.

FIG. 8 is a diagram representing the electronic circuit of the memory cell pattern of FIG. 7.

FIG. 9 is a cross-sectional view of the cell of FIG. 7 taken along line 9--9.

Figure 10 shows the sense field effect representing the inherent characteristics and operation during write and erase states. FIG. 3 is a diagram showing linear transfer characteristics of a transistor.

Figure 10A shows the test circuit used to obtain the results depicted in Figure 10. It is a road map.

FIG. 11 is a write/erase characteristic diagram of the memory cell of FIG. 7.

Figure 12 shows the memory window at high temperature after multiple write/erase cycles. It is a figure showing the deterioration of c.

BEST MODE FOR CARRYING OUT THE INVENTION 70-ting dart type non-volatile memo using features of this invention One embodiment of the Lee cell is designated by the number 1 in FIG. This memory cell 1 is Addressable individually or in groups for writing, erasing, and reading data typically used in integrated circuit memory plays consisting of multiple cells connected together You should understand that. Moreover, the memory cell structure described here is merely illustrative of a structure for implementing the principles of the invention.

Memory cell 1 in FIGS. 1, 2 and 3 is a lightly doped p-type single crystal silicon cell. formed in the silicon substrate 2, using an n-type diffusion region, and a conductive layer and a dielectric isolation dome. a polycrystalline silicon electrode and an interconnect layer. In Figure 1 , bit line 3 in the diffusion region is connected to channel 4 of field effect transistor (FET) Q1. connected to the next diffusion 6 by and diffused through channel 7 of sense FET Q2. 5. Diffusion area under poly layer 18 and connected to ground diffusion 8 by diffusion 10 .

This can be clearly seen from the electronic equivalent circuit diagram in FIG. Memory cell 10 write line 9 also Diffusion within the semiconductor substrate 2 and further diffusion by the channel 11 of FETQ3 Separated from 12.13. Diffusion 13 is located below the poly layer 18 and is located below the poly layer 17. extends downward. Diffusion 13 extends from diffusion 12 below charge transfer region 14 and from the field Note that it extends to the edge of oxide 15 (FIG. 3). As specified in Figure 1 Comparing the regions with the cross-sectional views of FIGS. 2 and 3 reveals that diffusion regions 3, 6, 89 . 10.12 is heavily doped and regions 5 and 13 are lightly doped with n-type impurities. shall be provided. The heavily doped layer regions are phosphorous diffused from the pact3 source. or using furnace diffused ions from arsenic or phosphorous or other impurity sources. It can be formed by ion implantation. The lightly doped region is the first poly Preferably, it is formed by phosphorus or arsenic ion implantation prior to the deposition of the silicon layer.

As well as the existence of a potential conductive path between the bit line 3 and the ground diffusion 8, the write line 9 and the charge The conductive path with the transfer region 14 is cut off by FETs Q1, Q2, and Q3. No. 1 level doped polycrystalline silicon (poly) is a floating dirt electrode 1 7, it forms a diffusion region 13 to form a sense FET Q2, a charge transfer region It overlaps with region 14 and channel 7. Floating dart, as it is known The presence of charge on the electrode 17 influences the conductive properties of the channel 7.

Poly level (albeit dielectrically isolated) on top of floating dart 17 The control line electrodes 18 of the control lines are overlapped. Floating data for control line electrode 18 The size and proximity of the gate electrodes 17 provide sufficient capacitive coupling therebetween.

The poly level also forms leads 16 and connects the channel region 4 in Ql and Q A channel region 4 in Q3 and a channel region 11 in Q3 are defined.

The long length of channel 11 means high punch through of FET Q3. This is for voltage requirements.

Although lightly doped, regions 5 and 13 are such that the potential of the control line 18 becomes conductive in the diffusion region. Contains enough damage to ensure that it has little effect. Ru.

A feature of the invention is the structure and composition of the dielectric of the charge transfer region 14 of cell l. Special In addition, the present invention provides a connection between the diffusion channel 13 and the polygon gate 17. An intervening charge transfer dielectric layer 19 (FIG. 3) connects the diffusion region 13 and the floating da... A bidirectional Pour-Silanque transfer mechanism between the ground electrode 17 and the frozen charge transfer mechanism. consists of a silicon nitride dielectric layer formed and treated to promote electrical conduction. It is intended to say.

Transfer of charge by pool-7 Lenkel conduction is a granche injection or Fowler-Nord-im-tunneling charge transfer This requires attention. The difference is mainly due to the characteristics of the charge transfer dielectric 19. It is. In that regard, the previously proposed silicon dioxide or thermoformed nitride Silicon dielectrics limit charge transfer only by tunneling or anodizing. This means that This invention can be applied to relatively thin low pressure chemical vapor deposition (LPCD) or Atmospheric pressure chemistry The existence of charge trap sites in such nitride-based layers is rare. To facilitate the desired Sol-7 Lenkel conduction, the nitride base layer 19 and one of the Between the recon floating dirt 17 and the other single crystal diffused silicon region Is the band, gear lug, energy barrier between 13 a floating dart? limit the leakage of charge between them.

The concept of nitride-based dielectric layers can be either nitride only, oxynitride or graded oxide. Contains a sinitride layer.

Using a nitride-based dielectric 19 to facilitate Pour-Silankel conduction in both directions. In particular, it has improved endurance compared to memory cells using oxide-based dielectrics. can provide improved 70-ting dart memory cells . Due to dielectric breakdown mechanism and hot electron charge trap, LP Charge drag sites in CVD or APCVD nitride-based dielectrics are large. oxide-based dielectrics easily facilitate charge transfer without permanent degradation. The charge transfer deteriorates visibly after only multiple write/erase cycles.

An alternative embodiment of the dielectric 19 of the charge transfer region 14 of FIG. 3 is shown in FIG. 3A. this The dielectric is a thick nitride-based dielectric at the extreme end that contacts the 70-ting dart 17. A very thin layer immediately adjacent to and below the diffusion layer region 13 covered by the body layer 22 It is a double gold layer including a certain oxide layer 21. Layer 21 is thermally grown silicon dioxide. is preferred. The Fowler-Nordheim tunnel passing through layer 21 has the lowest electrical current. The nitride layer 22 is made thin enough to be achieved in the field, while the nitride layer 22 is in contact with layer 21. It acts to limit the current density of the charge tunnel.

As in the embodiment shown in FIG. 3, the poly level control a18 is It's pretty close to Bell's Floating Dart 17, which means it's big enough. This means that capacitive coupling can be obtained. The two electrodes preferably have a density of 50 to 100 A dielectric layer 23 consisting of a nm-thick oxide or a 30 to 60 nm-thick nitride separated.

Experience has shown that the thickness of the nitride layer 19 in FIG. 3 is in the range of 5 to 30 nm. propose. For the composite dielectric of FIG. 3A, current experience indicates that oxide 21 is The nitride base layer 22 has a thickness of about 5 to 30 nm. Suggest something.

Next, regarding FIGS. 5 and 6, for bidirectional charge transfer, the pool-7 Renkel Discover the benefits of floating dart non-volatile memory cells using conducting dielectrics explain. The write/erase characteristic curve in Figure 5 is simply a nitride-based dielectric memory cell. This is representative of a device with a dielectric that can accommodate a fairly narrow range of low voltages and pulses. If it is possible to create a floating dart type memory cell that This is what I am saying.

For example, a memory cell with a nitride layer 19 (FIG. 3) with a thickness of about 10 nm. The voltage is approximately 8 µm using a 1 ms wide write/erase voltage not higher than 15 V. Provides a 2 sense FET write/erase window.

The excellent endurance properties of such memory cells are illustrated in FIG. Therefore, 19 v and 20 microseconds of a non-volatile nitride dielectric memory cell written in Hals. Storage time refers to time for both new cells and cells after 104 write/erase cycles. It is. A song depicting a window of a memory cell after a 10' write/erase cycle Line 26 is the opening representing the new memory cell window, and the curve in Figure 6 is Provides bidirectional pool silankel conduction for floating dart charges. What can be gained from memory cells using nitride-based dielectric layers formed to It simply represents the improved retention and endurance properties that can be achieved.

has a trap site for Gloof-Frenkel conduction through which the charge transfer Understanding of the physical factors that make LPCVD type nitrides suitable over oxides as media For this purpose, the dielectric properties in Table 1 below can be referred to.

table 1 Silicon nitride 10.8 6.0 4.0. 2.7 Thin oxide particles Silicon nitride 17.3 7.6 4.3 4.0 Oxynitride 13. 3 18.04.52.9 Thin regrowth HLC Oxide 13.7 7.5 9.0 1.5 Thin HLC oxide 11.7 0. 028 8.9 1.3z+)shi+)-y@4hichunazu 3.2 0.002 3 ．． 2 1.0 Table 1 shows electric field strength data and breakdown voltage for each level of current density. It is provided along with a summary in the form of merit numbers for comparison with industry data.

On the basis of merit numbers, 70-techniques using only oxides as charge transfer dielectrics The ding dart device produces the electric field strength and dielectric breakdown required for conduction. The margin between electric field strength and potential irreversible damage to the dielectric is quite small. I can see that it is. In that respect, the first three materials offered as dielectrics, all That is, silicon nitride alone, a combination of thin silicon dioxide and silicon nitride, and It turns out that silicon oxynitride is consistently good for both oxide and silicon. Karu.

Table 1 supports the selection of nitride as the charge transfer dielectric. given The electric field required to create a high current density is lower in nitride-based materials. The use of nitride dielectrics provides lower programming voltages and Allows for much faster programming times or the use of thicker nitrides Hold programming voltage.

Regarding dielectric integrity, the defect density of CvD silicon nitride films is It is believed that silicon oxide layers can be more easily controlled.

The advantages of nitrides as charge transfer dielectrics can therefore also be easily understood. Wear.

Merit: In addition to the margin characteristics given by the P parameter number, the charge Floating r-t memory using silicon dioxide as the transfer medium The cell has endurance problems due to the permanent charge trap of silicon dioxide. So The charges trapped here are useful for charging and discharging the floating darts. effectively reducing the effective electric field. For memory cells using nitride dielectrics: , since such nitride dielectrics feature charge trap sites, M In experiments with NOS type nonvolatile memory devices, its charge traps are recoverable. He showed that he is capable. Therefore, the nitride dielectric conducts the specified current value. Increasing the margin between the electric field required to break down and the electric field destroyed by breakdown In addition to being able to Therefore, it is strengthened.

Floating dart devices using silicon dioxide dielectrics typically have excellent retention It is known that it exhibits certain characteristics. It is silicon dioxide and silicon nitride. This is due to two differences between the base dielectric and the base dielectric.

First, silicon dioxide exhibits sol-7 Lenkel conduction that causes charge loss. The second reason is that silicon dioxide has a band gap of about 9 eV. The band gap of silicon nitride is about 5.2 eV, which is lower than that of silicon nitride. death However, memory cells that use silicon nitride-based dielectrics for charge transfer The holding power is sufficient for most applications, even at temperatures as high as 100°C. It has the advantage of staying within a reasonable range. In Figure 3A, very thin dioxide Alternative embodiments using a silicon layer 21 may further improve the retention mark if this is desired. Jin can be improved.

The operation of the memory cells shown in FIGS. 1 to 3 is explained by the circuit shown in FIG. This can be better understood by considering the signals shown in Table 2.

table 2 Semery cell operation Write ground vpp ground vpp Erase vpp vpp ground ground 5 read ground 5 V 2 V ground (Sense amplifier V Erase prohibited vpp vpp ground vpp Memory cell 1 writing is via control line 18 and bit line 3 to ground potential, and program voltage is applied to word line 16 and write line 9. This can be achieved by providing. In these conditions, the control line 18 and the floaty The capacitive coupling between floating r-gate 17 and floating r-gate 17 essentially connects floating gate 17. The combination of the voltages of the heel write line 9 and the word line 16 to the ground potential conducts FET Q3. This ensures the supply of a voltage of approximately V-VT□ to the diffusion 12°13.

p ■ is the threshold voltage of the transistor Q3. That H , the nitride-based dielectric 14 corresponds to a relative voltage of about vpp to vTH. receive an electric field. By following these process steps, you can create a floating gate Electrons are removed from 17. The opposite state (erased) of memory cell 1 is on control line 1 8 and write line 9 by applying opposite voltage states. Therefore , the electrons move to the floating gate 17. This state is shown in Table 2. .

The binary state of the floating dart 17 is read using the control line 18 and the write line 9. to ground potential and use the nominal enable potential of Q1 (e.g. 5V) to bit line 16 and sense amplifier voltage, e.g. This is accomplished by supplying a charge. FET Q1 is conductive via Since the sense amplifier connected to bit line 3 is It is possible to detect whether the negative voltage potential makes the sense FET Q2 conductive. .

The erase-inhibit mode shown in f-fle2 provides more flexibility in the implementation of memory cells. It gives It allows bank or word selection while operating in erase mode It is something to do. Memory cells 1 are arranged in a matrix within an integrated circuit structure. Let's remember that it is composed of one of several. One example is matrices. In some cases, it may be desired to erase/write only selected cells in the memory array. Erase prohibited mode The code gives features that can accomplish that. Memory according to that mode - To erase the cell, apply voltage V to the write line 9 during the erase mode. This is prohibited for cells that do. As can be seen from the analysis of these structures, erasure is prohibited. The signal prevents the formation of a relative potential between the nitride dielectrics 14. This example of erasure protection The benefit is that a common control line 18 can be used for the memory array, Use a write line 9 already used by another group of cells or by a puncture. It is something that can be done.

The structure of the memory cell disclosed herein has control line 18 and write line 9 at ground potential. The cell state can be read when the cell is opened. Thereby, each read cycle This minimizes disturbance of the charge on the floating darts 17 in the module.

Manufacturing of memory cell 1 can be performed using a wide range of techniques known in the industry. Wear. In all cases, it is conductive to the Pour-Silankel conduction, such that By forming a nitride-based dielectric layer, the tunneling through the oxide layer is considerably lower. This can be achieved by using fairly low field strengths corresponding to the write/erase voltages. It is important to ensure that the auxiliary oxide layer is thin enough to . A typical charge transfer dielectric layer is formed using typical manufacturing conditions such as: Ru. At atmospheric pressure and 750° C., the silicon dioxide dielectric layer 21 (FIG. 3A) Single crystal silicon is grown by exposing the wafer to a 1=1 mixed gas of N2 and 02. grown from the main substrate 2. The formation of nitride-based dielectric 22 is based on the fact that it is made of silicon nitride. or silicon oxynitride or graded silicon oxynitride However, it is preferable to undergo furnace operation immediately thereafter.

For the silicon nitride layer, it is a 3.5:1 mixture of dichlorosilane to ammonia. LPCVD deposition process at approximately 5 Q mtorr and 750 °C using I do. If the nitride base layer is silicon oxynitride, it is approximately 600 using a 3.5:1:2 mixture of Rosilane to ammonia to nitrous oxide. Preferably, the LPCVD process is carried out at a temperature of mTorr and 750°C. If the slope When depositing a xynitride layer, the deposition cycle should be adjusted in proportion to the desired shape. The mixing ratio may be varied to adjust the gas mixture throughout.

The patterns in FIG. 1, FIG. 2, FIG. 3, or FIG. 3A are known photolin graph masses. It can be fabricated by applying kinging, etching and dopant implantation techniques.

The non-volatile floating dirt type memory cell has been described above.

The cell uses a deposited silicon nitride-based dielectric as the charge transfer medium. , which involves the use of Pouleux silankel conduction as a charge transfer mechanism. . Nitride-based dielectric memory cells have excellent durability and acceptable retention properties It responds to write/erase voltages with fairly low amplitude and short pulse width while exhibiting can be done. The nitride base dielectric itself was formed during the nitride deposition. Characterized by its ability to conduct charge bidirectionally using nitride trap sites I get kicked.

Next, additional embodiments will be described. The composite dielectric layer there is 70-ting dart. is electrically isolated from the charge source for the same dart, but at a considerably lower write/erase voltage1 5 table Showa 62-502156 (7) and short pulse widths to floating darts. The dielectric is then a thin diacid layer formed directly on top of the conductive doped region of the silicon substrate. The layer is itself formed from a fairly thick LPCVD silicon nitride layer. The F layer is covered with a thin layer between the nitride and the 70-ting dart electrode above it. Contains oxynitride layer. According to this structure, the charge is the Fowler Nord ha Bidirectional tunneling through the oxynitride layer and the oxide layer by the im-mechanism However, the bidirectional transfer of charge through a fairly thick nitride is due to Leuf-Renkel conduction. achieved. This prevents the oxidation load from returning and removes the oxide and oxygen on both sides of the nitride. The complex of sinitride is a complex in which the charge held by the nitrides remains. It acts to electrically shield the 70-ting dart that is being flashed from the board. I guarantee that.

The next embodiment will be described with reference to Figure 7.8.9.

A given floating dart memory cell such as 101 is not publicly available in the industry. The following description will modify the memory cell performance as confirmed by the test results. I will concentrate on the good points of this invention. Figure 7.

As seen in FIG. 8, the memory cell 101 according to this embodiment is a field effect sensor. transistor 102, which has a source/drain connection. 104.106 and memory cells that form part of the 70-tag dart. and a rolling dart electrode 107. The charge is a diffused region within the substrate 111. from a control gnito 108 used as a charge source injector 109 Floating due to capacitive coupling? -) forwarded to (and from) 107 .

As in the embodiment, floating gate 107 is made of a first doped polysilicon The polycrystalline silicon layer 108 is a second doped polycrystalline silicon layer (poly, control layer). ff IJ II). As is common sense, various areas are separated by field oxide 112.

The focus of this invention is on region 113. Composite dielectric structure improved by this invention Structure 115 not only improves durability and retention properties, but also provides significantly lower pressure and shorter width Use Noculus to transfer charge to or from 70-ting・ff-) 107 Can move in both directions.

As seen in FIG. 9, floating ff-) 107 and control goo) 108 The capacitive coupling between the will be supplied.

Reference is now made to the cross-sectional view of the embodiment in FIG. Floating gate 107 is thin A thin silicon dioxide layer 116, a relatively thick silicon nitride layer 117 and a fairly thin silicon layer 116. Note that the composite dielectric structure with the oxynitride layer 118 is Should. Lateral oxide 119 is configured for charge transfer in region 113 Similarly, the sense FE is notched to form a composite dielectric 115. It corresponds to the oxide formed for T102.

According to one form of this structure, the dart oxide 119 of FIG. 9 is approximately 30-50 nm thick. The tunnel oxide 116 is a thermally grown diacid with a total thickness of about 2 nm. The layer 117 is made of LPCVD silicon nitride approximately 10-20 nm thick. The layer 118 may be an LPCVD oxynitride approximately 4-6 nm thick. nitrogen The oxide layer 117 and the oxynitride layer 118 are locally formed in the region 113 with a /4' As shown in FIG. 9, 70-Tinder Gate 107 Holds nitrides and oxynitrides in an extension/gutter with the same extent as is equally viable. However, standard FE like sense FET I O2 The presence of nitride in the dirt structure of T increases the threshold voltage of the FET. Previous experience has shown that this can lead to period instability.

According to the embodiments of FIGS. 7 and 9, the nitride layer 117 and the oxynitride layer It can be seen that 118 extends over the remaining portion of dirt oxide 119. So Nevertheless, during write/erase operations, the diffusion region 109 and the floating dart Due to the electric field gradient between 107 and 107, tunnel and nitride conduction charge transfer is through the central region within the cut of oxide 119.

The alternative embodiment structure of FIG. or even more so by replacing it with a thin silicon dioxide layer of slightly greater thickness.

The operation of the non-volatile cells in FIGS. 6-9 is floating.

The dart 107 also acts as a dart electrode for the sense FET 102. Understanding can be made easier by recognizing that Therefore, the drain Conduction between diffusion 106 and source diffusion 106 is provided by floating dirt 107. Indicated by the charge held. Following this structure, the floating game Transfer of charge from diffusion 109 on gate 107 occurs at the threshold voltage of sense FET 102. to bias. 70-ting gate 107 itself is shown in FIGS. A 70-ting gate 107 formed as a polyelectrode layer as shown in FIG. Due to the adjacency between the control dart 108 formed as a polyelectrode layer Recall that it is capacitively coupled to control gate 108.

An example of a set of typical conduction characteristics is shown in FIG. Therefore, the drain current is the 10th Curve 12 for a unique sense FET when tested according to the circuit in Figure A If there is a response like 1, the shifter will not be able to supply the write/erase pulse. is shifted between curves 122 and 123 according to the polarity of the charge transferred to port 107. It will be done. According to this exemplary embodiment, the pulse is 16V amplitude and lms wide. there were.

Floating dart 1o7 becomes negatively charged by transferring electrons to the electrode the effective control dart voltage required to bring the sense FET 102 into conduction if is shifted in the positive direction of curve 123 to remove the negative charge from the 70-ting dart. , the threshold voltage of the sense FE 7102 is shifted toward the characteristic curve 122. It will be done.

The range in between is defined as the memory cell window. The characteristics in Figure 10 are The compound layer 117 and the oxynitride layer 118 are made of polysilicon 7er-tin. The memory set has 74 turns to have the same width as the Gu Dart 7. This is for the example of the file.

You should be careful what you say.

Transfer of charge to and from the floating dart is carried out by the injector 109 and the control 108 (FIGS. 7 and 8) by supplying an appropriate voltage.

For example, change the threshold value of the sense FET 102 in the positive direction toward the curve 123 in FIG. If you want to shift to %7” wing r-t 107, move injector diffusion ground and set the control gate 108 to the appropriate amplitude and width using the information shown in FIG. The positive voltage of J? Negatively charged by supplying Luz. Poly! level The capacity between the floating gate 107 and the poly level control gate 108 is The quantity coupling makes the positive potential of the control dart. Regarding the cross-sectional view in Figure 9, 70-ting ・Coupling of the write voltage to 107 and grounding of the diffusion 109 is done using the dirt oxide 11 A high-strength electric current is placed at both ends of the composite dielectric layers 116, 117, and 118 in the notch region passing through 9. give rise to a world. As mentioned above, the strong electric field is caused by the thin oxide layer 116 and the thin oxide layer 116. Fowler-Nordheim tunnel of electrons passing through the xynitride layer 118 and generates an electronic state according to the Pour-Silang mechanism through the thick nitride layer 117. live. Ground the control dart electrode 108 and connect it to the injector diffuser 109 as appropriate. By supplying positive voltages of amplitude and width to floating memory cells. write state. In that case, the electrons from 70-Ting Gu) 107 are It diffuses through the combined dielectrics 116, 117 and 118.

Due to such operation, as shown in the M2O diagram, the sense FE'I' characteristic changes from the previous song. from line 123 to a new negative threshold voltage curve like curve 122. That will happen.

The read operation of the nonvolatile cell by the sense FET 102 is controlled by the control f-) 108. ground and appropriately bias the source diffusion 104 and drain diffusion 106. Therefore, this can be achieved by sensing the conduction state through the sense FET 102. Preferably. The embodiment of FIG. 7 has the source diffusion 104 connected to ground and the drain In-diffusion 106 is connected to vDD, but sense FET 102 It is well known that there are many means for sensing conduction. for example , the voltage vDD connected to the diffusion 106 is connected to the drain due to the inherent distributed capacitance of the line. It may also be a precharge potential held in the connection line. Also, FET Another transistor is connected in series with the sense FET 102 as a means to detect the conduction state. and other similar devices can be connected.

Figure 11 shows the change in the threshold voltage of the sense FET l02 and the write/erase pulse. The diagram depicts changes in the amplitude and width of the signal. Obviously, the pulse width and the wide range of vibration The higher the width, the more the window formed between the opposite binary states of the memory cell. becomes wider. Non-volatile memory made with composite dielectric material according to this invention - The cell's performance is excellent, and it is clearly a fairly large 10 microampere This is evidenced by a curve of the threshold voltage measured at the conductive level. . These results indicate that the composite dielectric layers 116, 117, and 118 are flat at the point IJ level. Rotting Goo) Same as 107 - This fruit is patterned to have a spreading pattern. It should be noted that it was drawn from the example test.

Oxide patterned to have a coextensive surface with floating gate 107 It is composed of a composite dielectric material consisting of a substance 116, a nitride 117, and an oxynitride 118. The endurance of the produced memory cells was shown to be excellent. Especially 100,000 times Even for cells that have undergone several write/erase cycles, the width is often reduced due to window degradation. No shortening was observed. Moreover, as seen in FIG. 12, the nominal 14V amplitude 1 Write/erase cycles are performed 100,000 times in milliseconds and stored at 100°C. The memory cell tested showed a window degradation of about 0.16V per 100,000 cycles. child performance, whether made solely of oxides or containing other materials as dielectrics. , it is considerably superior to the floating dart structure of the previous characteristics. Figure 12 gender Memory cell 1 in which the composite dielectric material has the same width as the floating dart Structural arrangement for 01 and sense FET 102 Flows a current of 5 microamperes This is the result of doing so. As shown in Figure 12, 100,000 write/erase cycles The retention characteristics after cycling are approximately 100,000 times from what the memory cell 101 originally exhibited. 90. There is no possibility of deterioration due to a new write/erase cycle with a reduced IV range. Recognize.

Memory cells according to the invention can be used in a number of different ways 107 (FIGS. 7 and 9). As far as it is concerned, it involves the arrangement of layers between the source of charge and the 70-ting dart. /Provides an area to direct the electric field during erasure. As explained earlier, the species described above Examples with different performance characteristics are composite dielectrics identical to floating darts. It includes structures with an expanse of . Preferably, the structure takes the form of FIG. The composite dielectric is then placed in a cut through the dirt oxide layer 119.

To create the structure shown in Figure 9, place the silicon substrate 111 at the position of Fi sense FET 2. , and at location 113? Approximately 30-50 nm above the insoecta diffusion 109 undergo normal processing until a dirt oxide is formed. After that, photoresist pattern using a mask to expose the notch in region 124-124; . Next, add the acid until the top surface of n+ doped injector diffusion region 109 is exposed. Apply chemical etching. A thin silicon dioxide layer is then grown from region 109. It will be done.

It grows from region 109 by thermal oxidation, one of the known methods. Next, pressure For example, a 1:3.5 ratio at 400-600 mtorr and a temperature of about 750°C. Silicon nitride layer 11 is deposited by low pressure chemical vapor deposition using silane and ammonia. form 7. According to this embodiment, silicon nitride layer 117 is 10-20 nanometers thick. It is formed to be thick. As previously explained, the next layer 118 is silicon oxide. Either nitride or silicon dioxide may be used. Oxynitride is preferred If the oxynitride is Chemically vapor deposited using a mixture of ammonia and nitrous oxide in the proportions of It will be done. In the case of silicon dioxide, it is the material of choice for dielectric layer 118.

The layer may be grown by conventional chemical vapor deposition or by thermal oxidation of the underlying nitride layer 117. stomach. Preferably, oxide layer 118 is slightly thicker than oxide 116.

oxide layer 116, nitride layer 117 and oxide or oxynitride layer 118. Formation starts from the formation of oxide 116 to oxynitride without exposing the device to the outside air. Hot wall reactor allowing direct continuity of the manufacturing process through the formation of 118 Preferably made of tubes.

As considered in one embodiment, the 113 composite dielectric is 70-tin with a poly I level. Should be made to have the same width as 107, floating - The doped polysilicon for gate 107 is deposited using selected photomasks. After cleaning, the exposed polysilicon, oxide, or oxynium Remove torides and nitrides. According to the alternative embodiment of FIG. ・Prior to the deposition of the polysilicon of the gate 107, photolithography is performed on the region 113. A lithographic mask is applied and the wafer is oxinitride or oxide and nitride. Subject to etching to remove objects. Afterwards, the PoIJ level is deposited and 70 - patterned to form a tinging gate 107. Separated oxide 114 The deposition and patterning of the poly II level control gate 108 is well known in the industry. done in a knowledgeable manner. Covered by a relatively thick nitride layer and a thinner oxide layer or a complex consisting of a very thin oxide layer covered by an oxynitride layer. A mixed dielectric (the last layer is thicker than the first oxide layer and directly adjacent to the floating dirt) (2009) offer a semiconductor dielectric structure that appears to have unique properties. This compound The structure exhibits exceptional staying power and can be programmed at fairly low voltages and with narrow widths. No-cycle retention feature compared to other 70-ting dart devices Show your gender.

The characteristics of this structure are the combination of a nitride layer sandwiched by two thin oxide base layers. This is due to the At zero or low controlled dart bias, the oxide film Preventing charge flow to or from floating darts. dielectric During writing or programming when the electric field is N, the energy barrier of the oxide is lowered. charge or discharge the 70-ting dart through the nitride In order to Start Lenkl conduction. Nitride conduction is limited by nitride trap density Ru. This nitride trap limits the charge transfer or flow rate because only the oxide film Minimizes the breakdown that would occur if used as a single dielectric for load transfer. Make it less.

The high energy barrier for holes with respect to electrons tunneling through the oxide is promotes electron conduction while reducing and restricting the transfer of electrons. This advantageous feature The problem is that silicon dioxide dielectrics are susceptible to destruction by repeated hole transfers. It is beneficial because of this. Moreover, electron conduction increases charge efficiency. those reasons.

are floating darts containing only nitrides or oxides as charge transfer media. The memory cell according to the present invention has higher retention characteristics and durability compared to memory cells. I believe that the fact that it has this characteristic is enough to explain it.

Oxynitride or oxide dielectric layer 118 is similar to thermally grown oxide layer 116. fabricated by a thick, vapor-deposited polysilicon layer 107. This will offset the effect of the mismatch.

The presence of such polysilicon mismatch creates and induces high electric field regions during write operations. The effective potential required to activate a tunnel through the electrical layer 118 is lowered. On top of that, The tunnel from floating gate 107 to substrate diffusion 109 is made of single crystal silicon. compared to the interface state density for the thermally grown oxide interface of Present for the oxide or oxynitride interface of silicon This is advantageous because the interface state density is high.

FIG. 1 Bi, 1,1 yarn made -311, Goshu made -9vth e only A (V) FIG.7 FIG, 10° FET pulse characteristic Vpp = 100rnV 16V, 1tns to W/E'I less FIG, 1 0A.

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Claims (1)

[Claims] 1. a first conductive layer (13, 109) capable of supplying charge; 3,109) and the dielectric layer (19; 21, 22; 116, 117) , 118) for charge and discharge. a conductive floating gate layer (17, 107) configured to a non-volatile memory device, the dielectric layer (19; 21, 22;116,117,118) have a thickness range of about 5 to about 30 nm; has a charge trapping site that provides a Poole-Frenkel charge transfer mechanism through a silicon nitride-based dielectric layer (19, 22, 117) floating gate non-volatile memory device. 2. The first conductive layer (13) and the silicon nitride layer have a thickness ranging from about 1 to about 4 nm. The silicon base dielectric layer (22) is placed between a silicon dioxide layer (21, 116) adapted for charge transfer by the channel; Floating gate nonvolatile memory according to claim 1, characterized in that Device. 3. The silicon dioxide layer has a thickness ranging from about 1 to 4 nm. 3. The floating gate non-volatile memory device according to claim 2. 4. The first conductive layer (13) is made of doped single crystal silicon and is The ting gate layer (17) is characterized in that it is made of doped polycrystalline silicon. 4. The floating gate non-volatile memory device according to claim 3. 5. The silicon dioxide layer (21, 116) is a thermally formed layer. Floating gate non-volatile memory device according to claim 4 characterized in . 6. The silicon nitride-based dielectric layer (19, 22) is made of dichlorosilane and aluminum. Claims characterized in that they are formed by chemical vapor deposition using ammonia. The alloting gate nonvolatile memory device according to item 1 or 2. 7. The silicon nitride based dielectric layer (19, 22) is made of dichlorosilane, anhydride. characterized by being formed by chemical vapor deposition using monia and nitrous oxide Floating gate nonvolatile memory device according to claim 1 or 2 . 8. The silicon nitride-based dielectric is silicon nitride, and the floating silicon dielectric is silicon nitride. A non-volatile memory device is aligned with the silicon dioxide layer (116). in contact with the floating gate layer (107), Silicon dioxide layer or silicon oxide layer compatible with charge transfer by tunneling The floatie according to claim 2, characterized in that it comprises a toride layer (118). non-volatile memory device. 9. The silicon dioxide layer (116) is approximately 2 nm thick and the silicon nitride layer (116) is approximately 2 nm thick. (117) is in the thickness range of about 10 to 20 nm, and the second silicon dioxide or the silicon oxynitride layer has a thickness range of about 4 to about 6 nm. Floating gate non-volatile memory device according to claim 8, characterized in that Place. 10. placed close to the floating gate layer (17, 107); Having a control gate electrode that is capacitively coupled to the floating gate layer. Floating gate non-volatile memory device according to claim 1 characterized in .