JPS6249736A - Reproducing circuit for clock of bi-phase modulated signal - Google Patents

Abstract

PURPOSE:To prevent picture quality deterioration of a TV picture, by constituting the titled clock reproducing circuit of an edge detecting circuit which detects the edge of a bi-phase modulated signal, tuning circuit which turns to frequencies that are even times higher than the highest frequency of the bi-phase modulated signal, and comparator. CONSTITUTION:An edge detecting pulse (b) is supplied to a tuning circuit 13 through a coupling condenser 12. The tuning circuit 13 is composed of a coil and capacitor and its turning frequency is set at, for example, 5.0MHz which is double of the highest frequency of a bi-phase modulated signal (a). Signals which are fetched from the tuning circuit 13 and phase-synchronous to both rising and falling edges of the input bi-phase signals (a) are supplied to the base of an NPN transistor 15 through a coupling condenser 14. A NOR circuit 18 and resistance 19 constitute a comparator and such a pulse train (d) that becomes high in level when the level is higher than the center level of an input sine wave (c) and low in level when the level is lower than the center level, is fetched to an output terminal 21 from the NOR circuit 18.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a clock recovery circuit for a biphase modulated signal, and more particularly to a clock recovery circuit that recovers a clock for a biphase modulation signal without using an oscillator.

Conventional technologyAs one of the conventional self-clockable modulation methods,
A biphase modulation method is known.

A digital signal modulated by this bi-phase modulation method, that is, a bi-phase modulated signal, for example, changes from high level to low level at half the bit period T when the bit information (data) is 1'', and when the bit information (data) is 1'', it goes from high level to low level. It goes from low level to high level at half the bit period JIQT, and then 1 i l!.

In either case of "°0", it is a binary signal that has different logical values in the first half and the second half of each bit period. To demodulate the above bi-phase modulation signal, its clock component is regenerated (extracted).
Conventionally, the clock has been regenerated using a configuration as shown in FIG.

In Fig. 3, the biphase modulated signal that enters the input terminal 1 is band-limited by the bandpass filter 2, and then the phase comparison @
3, where the voltage controlled crystal oscillator (VCXO)
The phase is compared with the output signal of No. 5 and converted into an error voltage according to their phase difference. This phase error voltage is applied to the VCXO 5 through a low-pass filter 4 as a control I lightning voltage,
Its output oscillation frequency is variably controlled. This allows the VC
The clock component of the biphasic modulation signal is taken out from x05 to the output terminal 6.

Problems to be Solved by the Invention However, the above-mentioned conventional circuit can be used even when a biphase modulation signal is intermittently received.

5 is constantly oscillating, causing interference. for example,
When the above-mentioned bi-phase modulated signal is transmitted superimposed on a specific position in the vertical blanking period of a television signal, most of the non-superimposed period has the highest frequency of the bi-phase modulated signal (for example, 2. The high frequency of 5MH2) enters the television receiver, and since it falls within the video signal band, it degrades the image quality. In addition, VCXO5 was used because it did not require adjustment, but VCXO5
O5 has a problem in that the variable frequency range is narrow and may cause problems in clock recovery of biphase modulated signals.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a clock recovery circuit for a biphase modulated signal that solves the above problems by supplying an edge detection signal of the biphase modulated signal to a tuning circuit.

Means for Solving the Problems A clock recovery circuit for a biphase modulation signal according to the present invention includes an edge detection circuit for detecting edges of the biphase modulation signal, and a clock regeneration circuit tuned to a frequency that is an even multiple of the highest frequency of the biphase modulation signal. It consists of a tuning circuit and a comparator.

Both rising and falling edges of the active bi-phase modulated signal are detected by an edge detection circuit and then fed to a tuning circuit where they are tuned. The output signal of this tuning circuit is converted into a pulse train by a comparator and output as a reproduced clock signal.

The above tuning circuit is configured to tune to a frequency that is an even number multiple of the highest frequency of the biphase modulation signal, and does not produce an output unless the edge detection signal of the biphase modulation signal is supplied. Therefore, if the biphase modulation signal is intermittently input, the regenerated clock signal can be output only when the biphase modulation signal is input. It is a resonant circuit using C and has no oscillation circuit.

EXAMPLE An example of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows a circuit diagram of an embodiment of the circuit of the present invention.

In the same figure, a biphase modulated signal a as shown in FIG. . That is, the biphase modulated signal a
After the polarity is inverted by the inverter 8, the capacitor 9
The pulse train is integrated by , and is further supplied to the inverter 10, where it is converted into a low level pulse train when the level is above a predetermined threshold value, and a high level pulse train when the level is below the threshold value. Therefore, a pulse train having the same waveform as the biphase modulation signal a and delayed by integration using the capacitor 9 is extracted from the inverter 10.

The antagonistic OR circuit 11 is supplied with the output pulse train of the inverter 10 and the input biphase modulation signal, has a pulse width corresponding to the delay time due to the integration, and has a pulse width corresponding to the rise and fall of the biphase modulation signal a. The edge detection pulse b shown in FIG. 2 is outputted in phase synchronization with both edges.

This edge detection pulse b is supplied to a tuning circuit 13 via a coupling capacitor 12. This tuning circuit 13 is composed of a coil and a capacitor, and its tuning frequency is, for example, 5 times twice the highest frequency of the biphase modulation signal a.
．． It is selected as 0MHz HZ. Note that the tuning frequency may be another even number multiple, such as four times the highest frequency of the input biphase modulation signal a. A signal extracted from this tuning circuit 13, which has a repetition frequency of 5.0 MHz and is phase-locked to both the rising and falling edges of the input biphase signal a, is supplied to the base of the NPN transistor 15 through the coupling capacitor 14. Here, the signal is inverted and amplified and taken out from the connection point between the collector of the transistor 15 and the load resistor 16.

The collector output signal of transistor 15 is a sine wave as shown by C in FIG.
It is supplied to one input terminal of the R circuit 18. One of the input terminals of the NOR circuit 18 is connected to the output terminal 21 via one resistor, and the input terminal for its use is connected to a low level signal as shown in FIG. 2 via the input terminal 20. A signal is provided. The NOR circuit 18 and the resistor 19 constitute a comparator, and the output terminal 2 from the NOR circuit 18
1, as shown in FIG. 2, a pulse train d is taken out which has a high level that is higher than the center level of the input stop string wave C and a low level when the level is small. This pulse train d is a clock signal reproduced from the input biphase modulation signal a, and is at a low level at the beginning position and the intermediate position of the bit period T of the input biphase modulation signal a.

Note that when the biphase modulation signal does not enter the input terminal 7, the exclusive OR circuit 1 constituting the edge detection circuit
There is no output of 1, so no signal is output to the output terminal 21.

Effects of the Invention As described above, according to the present invention, since the edge detection signal of the biphase modulation signal is supplied to the tuning circuit, it is possible to output the clock signal only when the biphase modulation signal is supplied. Since it does not use an oscillator, it does not cause any interference to other equipment during the period when the biphase modulation signal is not supplied. It has features such as being able to have a wide variable frequency range.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the circuit of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation of the circuit shown in FIG. 1, and FIG. 3 is a block system diagram showing an example of a conventional circuit. 7... Biphase modulation signal input terminal, 8.10...
・Inverter, 9... Capacitor, 11... Exclusive OR circuit, 12, 14.17... Coupling capacitor,
13... Tuned circuit, 15... NPN transistor,
18...NOR circuit, 20... Output terminal. Patent applicant: Victor Japan Co., Ltd. Figure 3 -″m

Claims (1)

[Claims] an edge detection circuit that detects both rising and falling edges of the biphase modulation signal; and a tuning circuit that is supplied with the output detection signal of the edge detection circuit and that tunes to a frequency that is an even multiple of the highest frequency of the biphase modulation signal. 1. A clock regeneration circuit for a biphase modulated signal, comprising: a comparator to which an output signal of the tuning circuit is supplied and converts it into a pulse train.