JPS6249669A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain an EPROM having low voltage necessary for the write in of data by a method wherein the charge injection into a floating gate is performed using an MIS-type FET of submicron type having the channel length of 1mum or less. CONSTITUTION:A p-channel MOSFET 4, consisting of an outer gate 1 and a floating gate 2, and a submicron depression type p-channel MOSFET of the channel length of 0.8mum, consisting of the floating gate 2 and another outer gate 3, are formed on an n-type substrate 6 by performing an n-type double-layer polysilicon process. The floating gates 2 of the two p-channel MOSFET's 4 and 5 are connected on the same pattern. Through these procedures, the EPROM using the write-in by the enhancement type channel MISFET with which a data write-in operation can be performed in a short period with low voltage, can be accomplished.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an erasable and writable read-only semiconductor memory device that enables high-speed data writing at low voltage.

Prior Art Conventionally, floating goo11 between the external control gate and the channel
- Applying a high voltage between the external (control) gate and the substrate to inject charge into the so-called floating gate erasable and programmable read-only semiconductor memory device (KFROM) with Charge injection methods have been used that utilize an F-N channel current injected into the gate insulating film or a drain avalanche generated by applying a high voltage between the drain and the substrate.

However, writing using these methods requires high voltage (
10V to 40V) and required a relatively long data writing time (several tens of microseconds to several milliseconds) compared to DRAM and SRAM.

Problems to be Solved by the Invention As mentioned above, the conventional method of writing data to a floating gate type RPRQM requires a high voltage during writing, or it takes a relatively long time to write data. There were other problems.

The present invention was developed to solve this problem, and aims to realize EPRQM that can write data at high speed with low voltage.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention aims to reduce the normal operating voltage (
sV) or relatively low voltage (<10V)
By applying voltage to the drain electrode, impact ionization occurs near the drain, and a submicron depletion type P-type with a channel length of less than 1 μmid causes avalanche hot electron current to be injected into the gate insulating film. MIS field effect transistor (IKT)
) by injecting charge into the floating gate, it is possible to create an ICPROM in which the voltage required for writing data is low.

Operation The present invention uses the above-described configuration to write data by injecting hot Φ electrons generated by impact ionization in/near the channel current into the gate insulating film. Data can be written at a lower voltage than N tunnel injection or drain avalanche injection. Further, by using a depletion type P-type MISFET, the injection efficiency is improved more than that of an enhancement type MISFET.An example of the present invention will be described with reference to FIG.

For example, a P-channel MOSFXT 4 consisting of an external gate 1 and a floating gate 2 and a submicron channel length of 0.8 μm consisting of a floating gate 2 and another external gate 3 are formed using an n-type double-layer polysilicon process on an n-type substrate 6. Forming a depletion type P-channel MO8FET This is because the dependence of hot electron generation on the channel length is extremely large, and with a channel length of 1.0 μm or more, sufficient hot electron injection required for writing cannot be expected. be. 2 P channels M
It is assumed that the floating gates 2 of the O8FET 4.5 are connected on the same ζ turn. Submicron depression type P-channel MO8FET6 formed in this way
FIG. 2 shows the relationship between the external gate voltage and the gate injection current when -9V is applied to each drain of an enforcement type MO8FET having the same shape as this. 7 shows the characteristics of depression type FIcT, and 8 shows the characteristics of enhancement type FKT. The threshold voltage vth of two MO8FB:T is 00T for each depletion type.
V, Enhancement l-W is -1, OV,! +ru.

Both gate currents and gate voltages have threshold voltages vth
It can be seen that the peak is approximately 0.7V higher. Furthermore, since this gate current is positive, it can be seen that it is a hot electron current from the substrate side. When comparing the depletion type and the enhancement type, the depletion type has a larger injection current peak.

This is thought to be due to the fact that in the depletion type, electron injection begins at a lower external gate voltage, resulting in lower external gate voltage and higher injection efficiency. Although the above embodiment has been described using an MO5 type FET, the insulating film is not limited to an oxide film, and may be a so-called MIS type FET. In this way, depression type P-channel MIS
The FET is an enhancement type P-channel MISFE.
'l: Electrons can be injected more efficiently than in this case.

Effects of the Invention As described above, according to the present invention, it is possible to realize an EFROM using writing using an enhancement type P-channel MISFET, which allows data to be written at low voltage and in a short time.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the structure of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 shows the relationship between the gate voltage and gate injection current of a depletion type FET that constitutes the device of this embodiment, compared to that of an enhancement type FKT. It is a characteristic diagram shown in comparison with. 1...External (control) gate, 2...Floating gate, 3...External (control) gate, 4...
...P-channel MO3FET, 5...Submicron depression type P-channel MO8FE
T, 6... Board. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 1 Tatone p gate Figure 2 Gate house, E (V)

Claims (1)

[Claims] An erasable and writable read-only nonvolatile semiconductor having an external gate and a floating gate between the external gate and the substrate and to which no voltage can be applied directly from the outside, as a gate electrode of a MIS field effect transistor. 1. A semiconductor memory device comprising a depletion type P-type MIS field effect transistor with a channel length of 1.0 μm or less as means for injecting charge into the floating gate.