JPS6249422A - Constant-voltage generating circuit - Google Patents

Abstract

PURPOSE:To obtain the titled circuit which is strong against a temperature variation and whose power consumption is small, and also to use it in a circuit in which a supply power source voltage is low, by boosting the supplying power source voltage by a switched capacitor circuit and generating a reference voltage which is higher than the supply power source voltage,and using a constant-voltage diode having a Zener voltage which is higher than the supply power source voltage. CONSTITUTION:When the potential of an output terminal 8 and the potential of a connecting point 7 of a switched capacitor circuit 1 become higher than a threshold voltage of a MOSFET 15, the MOSFET 15 exerts no influence on the potential of the output terminal 8. On the other hand, when the sum of a Zener potential Vz of a constant-voltage diode 2 and a threshold voltage Vtn of a MOSFET 3 coincides with the potential of the output terminal 8,the potential of the output terminal 8 is maintained in (Vz+Vtn) and goes to a reference voltage, and the reference voltage of (Vz+Vtn) is divided into object voltages by MOSFETs 41-43 of a load circuit 4. A MOSFET 44 becomes an off-state, when no current is flowing to the constant- voltage diode 2, and when the switched capacitor circuit 1 is not executing a switching operation, it is prevented that an unnecessary current flows.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a constant voltage generation circuit, and particularly to a constant voltage generation circuit having a switched capacitor circuit.

[Conventional technology]

Conventionally, this type of constant voltage generating circuit has been used to increase the forward voltage of the diode by M, as shown in the circuit diagram of the first conventional example in FIG.
OS) Generates the required constant voltage by distributing it using a load circuit made up of transistors. In this case, the temperature dependence of the forward voltage is significant, and in order to obtain a stable constant voltage against fluctuations in the power supply voltage, it is necessary to flow a sufficient current.6M08
The constant voltage generating circuit shown in FIG. 5 distributes the Zener voltage of a constant voltage diode through a load circuit constituted by a MOS transistor to generate a required constant voltage.

In this case, it is generally difficult to obtain a low Zener voltage of 5V or less with the IC chip, and it cannot be used in a circuit with a power supply voltage of 5V or less.

[Problem that the invention seeks to solve]

The above-described conventional constant voltage generation circuit has the disadvantage that it is sensitive to temperature changes and consumes a large amount of power, or cannot be used in circuits with a low supply voltage.

An object of the present invention is to provide a constant voltage generation circuit that is resistant to temperature changes, consumes little power, and can be used in circuits with a low power supply voltage.

[Means for solving problems]

The constant voltage generation circuit of the present invention includes a switched capacitor circuit that is on/off controlled by an externally supplied clock and outputs an output voltage higher than the externally supplied power supply voltage, and a zener voltage that is higher than the supplied power supply voltage. a constant voltage diode having an anode electrode connected to an output terminal of the switched capacitor circuit; and a constant current circuit having one terminal connected to a cathode electrode of the constant voltage diode and the other terminal connected to a ground point. and a load circuit whose one terminal is connected to the anode electrode of the voltage regulator diode and the other terminal is connected to a ground point and which distributes the output voltage.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

In FIG. 1, 1 is a switched capacitor circuit, 2 is a constant voltage diode having a Zener voltage higher than the supply voltage VDD, 3 is a MOSFET as a constant current circuit,
4 is a load circuit formed by MOSFETs 41-44.

In FIG. 1, the switched capacitor circuit 1 is
When the N-channel MOSFET 14 is turned on by CLK, the potential at the connection point 6 of the continuum y-12°13 becomes VS8. The forward potential of the diode 11 is V
F, the capacitor 12 is charged through the diode 11 by a potential difference of (VDD - Vss - VF). Here, the caps of capacitors 12 and 13 are set to be equal. When the ktO8FBT14 is turned off by the clock CLK, the connection point 6 becomes a floating state, the same charge as the capacitor 12 is induced in the capacitor 13, and the potential of the connection point 7 between the diode 11 and the capacitor 12 becomes (VD
D - Vss - VF). Note that the reverse withstand voltage of the diode 11 is set to prevent discharge from occurring on the power supply terminal side.
The P-well diffusion layer and the N-type high concentration diffusion layer are set to have a sufficiently high breakdown voltage.

In MOS F'ET l 5, the potential at the connection point 7 is 1M08 from the potential at the output terminal 8 of the switched capacitor circuit l.
When the voltage becomes higher than the threshold voltage of FET 15, it turns on, but the voltage at the connection point 7 at position t (VD
D-Vss-VF) (at D time, the voltage turns off and the potential of the output terminal 8 is no longer affected.

On the other hand, the Zener voltage vz of the constant voltage diode 2 and the MOS
When the sum of the threshold voltage Vtn of the FET 3 and the potential of the output terminal 8 match, the MOSFET 3 is turned on, and a current flows until the potential of the output terminal 8 drops slightly below (Vz + vtn). Therefore, only the voltage boosted by the clock CLK is applied to the constant voltage diode 2, and the potential of the output terminal 8 is maintained at (vz+Vtn) by the parasitic capacitor 21 of the constant voltage diode 2, which becomes the reference voltage.

The reference voltage of (Vz+Vtn) is the MOSF of the load circuit 4.
ET 41.42.43 to the desired voltage. The MOSFET 44 is in an off state when no current flows through the constant voltage diode 2, and prevents unnecessary current from flowing when the switched capacitor circuit 1 is not performing a switching operation. Here, the MOSFET 4 is set so that the current limited by the load MOSFETs 41 to 43 is sufficiently smaller than the current limited by the MOSFET 44.
4 and the channel widths of MOSFETs 41 to 43 are set.

FIG. 2 shows the switched capacitor circuit 1 shown in FIG.
FIG. 3 is a cross-sectional view of an IC chip constructed of MO8.

As shown in Figure 2, the reverse breakdown voltage is equal to the supply power supply voltage vDD
A sufficiently taller diode 11. MOSF for preventing discharge
ET15, capacitors 12 and 13 whose electrodes are an N-type cavity intensity diffusion layer 17 and two aluminum electrodes, and a clock C.
MOSFETs 14 that are turned on and off by LK are arranged on an N-type silicon substrate 18, respectively.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

As shown in FIG. 3, a switched capacitor circuit 1. The reference voltage generated by the constant voltage diode 2 and the MOSFET 3 of the constant current circuit is connected to the load circuit 5 connected in series.
The target voltage is divided by capacitors 51 and 52, and a constant voltage output Vref is obtained by a comparator 53 formed by five MOSFETs.

〔Effect of the invention〕

As explained above, the constant voltage generating circuit of the present invention is as follows.

By boosting the supply voltage using a switched capacitor circuit to generate a reference voltage higher than the supply voltage, and by using a constant voltage diode with a Zener voltage higher than the supply voltage, temperature dependence can be reduced even at the supply voltage below the Zener voltage. This has the effect that any constant voltage output that is less dependent on the power supply voltage can be obtained with low power consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
A cross-sectional view of an IC chip when the switched capacitor circuit shown in the figure is configured with 0MO8, FIG. 3 is a circuit diagram of a second embodiment of the present invention, and FIG. 4 is a circuit diagram of a conventional constant voltage generation circuit.
FIG. 5 is a circuit diagram of a second conventional example of a conventional constant voltage generating circuit. 1°゛...°switched capacitor circuit, 2...°゛...constant voltage diode, 4,5...load circuit,
16...P well diffusion layer, 17...N
Type high concentration diffusion layer, 18...Nfi silicon substrate. 3-mu

Claims (1)

[Claims] A switched capacitor circuit that is controlled on and off by an externally supplied clock and outputs an output voltage higher than the externally supplied power supply voltage, and an anode connected to the output terminal of the switched capacitor circuit that has a Zener voltage higher than the supplied power supply voltage. a constant current circuit having one terminal connected to the cathode electrode of the constant voltage diode and the other terminal connected to a ground point; and a constant current circuit having one terminal connected to the anode electrode of the constant voltage diode, and a load circuit having a terminal connected to a ground point and distributing the output voltage.