JPS6248946B2 - - Google Patents

Info

Publication number
JPS6248946B2
JPS6248946B2 JP54123171A JP12317179A JPS6248946B2 JP S6248946 B2 JPS6248946 B2 JP S6248946B2 JP 54123171 A JP54123171 A JP 54123171A JP 12317179 A JP12317179 A JP 12317179A JP S6248946 B2 JPS6248946 B2 JP S6248946B2
Authority
JP
Japan
Prior art keywords
circuit
signal
delay
image quality
waveform
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54123171A
Other languages
Japanese (ja)
Other versions
JPS5647174A (en
Inventor
Akira Usui
Toshimitsu Fujimori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP12317179A priority Critical patent/JPS5647174A/en
Publication of JPS5647174A publication Critical patent/JPS5647174A/en
Publication of JPS6248946B2 publication Critical patent/JPS6248946B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/14Picture signal circuitry for video frequency region
    • H04N5/21Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
    • H04N5/211Ghost signal cancellation

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)

Description

【発明の詳細な説明】 本発明は、テレビジヨン受像機の画質調整装置
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image quality adjustment device for a television receiver.

従来、テレビジヨン受像機の画質調整装置は、
標準的な送信信号を受信した場合に再生波形が最
適となるように設定される。第1図のAは、標準
的な受信信号を映像検波したもので、VIFフイル
タによる帯域制限のため、プリ・オーバーシユー
ト、オーバーシユートが少しつく状態を示してい
る。この信号をCRT上で最適に再生するために
は、Bのように、プリ・オーバーシユート、オー
バーシユート量を等量つけるように画質回路の定
数が決定される。ところが、実際の受信状態で
は、アンテナ系のミスマツチングや近接ゴースト
等の影響で、C,Dのような波形が映像検波波形
として再生される場合が多くある。この波形を前
設定の画質定数の回路を通してCRT上に再生す
ると、それぞれC,Dの状態がきわめて強調さ
れ、プリ・オーバーシユート、オーバーシユート
が非常に目立つ画になり見苦しくなる欠点があつ
た。
Conventionally, the image quality adjustment device for television receivers is
The reproduction waveform is set to be optimal when a standard transmission signal is received. A in FIG. 1 is a video detection result of a standard received signal, and shows a state in which there is a slight pre-overshoot and overshoot due to the band limitation by the VIF filter. In order to optimally reproduce this signal on a CRT, the constants of the image quality circuit are determined so that the pre-overshoot and overshoot amounts are equal, as shown in B. However, in actual reception conditions, waveforms such as C and D are often reproduced as video detection waveforms due to antenna system mismatching, proximity ghosts, and the like. When this waveform is reproduced on a CRT through a circuit with preset image quality constants, the C and D states are extremely emphasized, and the pre-overshoot and overshoot become very noticeable, resulting in an unsightly image. .

本発明は、かかる欠点を補正できる手段を提供
するものである。
The present invention provides means for correcting such drawbacks.

第2図に本発明の第1の実施例を示す。第3図
に標準的な検波信号を第4図に前述のような原因
で歪んだ検波信号を示す。第2図のAから入力ビ
デオ信号を供給してこれを2つに分ける。第3図
のa,e、第4図のa,eがこれに相当する信号
波形である。この一方を2次微分回路1を通す
と、第3図、第4図のb,fに相当する波形とな
る。また、小時間遅延回路2を通すと第3図、第
4図のc,gの波形となる。この遅延時間は、外
部より可変になつており、入力信号の歪みに応じ
て最適に変化させる。回路1と2の出力信号を加
算回路3で合成すれば、第3図、第4図のd,h
のように、入力信号の歪みにかかわらず、最適な
状態の画質補正が可能となる。4は再生画像の周
波数対振幅特性を変化させる回路であり、この出
力をBから後段の回路に供給するものである。
FIG. 2 shows a first embodiment of the present invention. FIG. 3 shows a standard detection signal, and FIG. 4 shows a detection signal distorted due to the causes mentioned above. An input video signal is supplied from A in FIG. 2 and split into two. Corresponding signal waveforms are a and e in FIG. 3 and a and e in FIG. 4. When one of these is passed through the second-order differentiator circuit 1, it becomes a waveform corresponding to b and f in FIGS. 3 and 4. Furthermore, when the signal is passed through the small time delay circuit 2, it becomes the waveforms c and g in FIGS. 3 and 4. This delay time is externally variable, and is optimally changed according to the distortion of the input signal. If the output signals of circuits 1 and 2 are combined in addition circuit 3, d and h in Figs. 3 and 4 are obtained.
As shown in the figure, it is possible to perform image quality correction in an optimal state regardless of the distortion of the input signal. 4 is a circuit for changing the frequency versus amplitude characteristic of the reproduced image, and its output is supplied from B to the subsequent circuit.

第5図に具体的な回路例を示す。破線で囲んで
符号を付した部分が第2図の各ブロツクと対応す
るようになつている。1は、入力信号をインダク
タL2、キヤパシタC3の各インピーダンスL2,C3
により遅延させるもので、遅延量は√23
比例し、本発明ではL2,C3のそれぞれ両方とも
可変になつている。2では、インダクタL1、キ
ヤパシタC1の各インピーダンスL1,C1による直
列共振回路を通すことにより、2次微分を行なつ
ている。3は一方の信号をトランジスタQ6のベ
ース、他方の信号をエミツタから供給してコレク
タにより合成する回路である。トランジスタQ6
のベースから入力した信号はトランジスタQ6
エミツタを通してトランジスタQ7のベースに供
給される。トランジスタQ6,Q7のコレクタはト
ランジスタQ2ないしQ5の(Q2,Q3)、(Q4,Q5
の共通エミツタで接続されたダブルトランス回路
で外部電圧により(Q3,Q5)、(Q2,Q4)の共通
コレクタでの混合比が変化させられる。トランジ
スタQ6のエミツタにはキヤパシタC1,C2、イン
ダクタL1のインピーダンスC2、(C1,L1)が低イ
ンピーダンス間に接続されているため、高域周波
数成分の利得が高くなつている。抵抗器R11の出
力信号は、可変抵抗器VR1により外部から与えら
れる電圧により、周波数振幅特性が変化する信号
となつている。なお、V1,V2はバイアス電位で
ある。
FIG. 5 shows a specific circuit example. The portions surrounded by broken lines and labeled with symbols correspond to the blocks in FIG. 1 connects the input signal to the impedances L 2 and C 3 of the inductor L 2 and capacitor C 3
The amount of delay is proportional to √2 · 3 , and in the present invention, both L 2 and C 3 are variable. In No. 2, second-order differentiation is performed by passing the signal through a series resonant circuit formed by impedances L 1 and C 1 of an inductor L 1 and a capacitor C 1 . 3 is a circuit that supplies one signal from the base of the transistor Q 6 and the other signal from the emitter and synthesizes them at the collector. transistor Q 6
The signal input from the base of is supplied to the base of transistor Q7 through the emitter of transistor Q6 . The collectors of transistors Q 6 and Q 7 are the ( Q 2 , Q 3 ) , (Q 4 , Q 5 ) of transistors Q 2 to Q 5.
The mixing ratio at the common collector of (Q 3 , Q 5 ) and (Q 2 , Q 4 ) can be changed by an external voltage using a double transformer circuit connected by a common emitter. Capacitors C 1 and C 2 and impedance C 2 of inductor L 1 (C 1 , L 1 ) are connected to the emitter of transistor Q 6 between low impedances, so the gain of high frequency components is high. There is. The output signal of the resistor R11 is a signal whose frequency and amplitude characteristics change depending on the voltage applied from the outside by the variable resistor VR1 . Note that V 1 and V 2 are bias potentials.

第6図に、群遅延特性と、波形変化とを示す。
横軸は周波数、縦軸は遅延時間tとする。a′の
特性の回路を通した波形はaのように、プリ・オ
ーバーシユート、オーバーシユートのバランスは
くずれない。b′のように高域での遅延が大きくな
るとbのように、オーバーシユートがつき、その
後にはリンキングが発生する波形となる。c′のよ
うに高域の遅延量が少ないものは、cのようにプ
リ・オーバーシユートがつき、立下がり部分に肩
ができる波形となる。b′とc′の,,のそれ
ぞれの特性の和をとると、d′の,,のよう
に、高域の遅延量が、大きい、平坦、少ないの3
特性を作ることができる。故に波形は、それぞれ
dの,,のようにオーバーシユートが大、
等量、プリ・オーバーシユートが大の波形ができ
る。前述の第1図の波形のA,C,Dのどの入力
波形を受信しても、これを逆補正するようなdの
,,の特性を通してやれば、入力信号波形
の歪みにかかわらず、最適な波形を供給すること
ができる。
FIG. 6 shows group delay characteristics and waveform changes.
The horizontal axis is the frequency, and the vertical axis is the delay time t. As shown in a, the waveform passed through a circuit with characteristics a' does not lose the balance between pre-overshoot and overshoot. When the delay in the high range becomes large, as shown in b', the waveform becomes overshooting, followed by linking, as shown in b. A waveform with a small amount of delay in the high range, such as c', has a pre-overshoot and a shoulder at the falling edge, as shown in c. If we take the sum of the respective characteristics of b' and c', , we can see that the amount of high-frequency delay is large, flat, or small, as in d'.
Characteristics can be created. Therefore, the waveforms have large overshoots as shown in d and , respectively.
Creates a waveform with equal amount and large pre-overshoot. No matter which input waveform A, C, or D of the waveform shown in Figure 1 is received, if it is reversely corrected through the characteristics of d and , it will be optimal regardless of the distortion of the input signal waveform. can provide a wide range of waveforms.

第7図は、これを実現する第1の手段を示すも
のである。1aは第6図のc′の特性をもつ群遅延
特性補正回路で、振巾特性は変えずに、群遅延回
路のみを変化させうるものである。回路1aの出
力は信号遅延回路2aを経て画質調整回路3aを
通して、周波数対振幅特性を可変させる回路に供
給され、その出力信号はBから後段に供給され
る。第6図の特性の回路例を第9図に示す。破線
で囲んで符号を付したブロツクが第6図に対応す
るようになつている。回路1aはラチス回路で構
成されており、インダクタL1,L2は結合係数が
1で巻かれている。この回路でインダクタL3
るいはキヤパシタC3のインピーダンスを変化さ
せると、第6図のc′の,,に示すような変
化を得ることができる。回路2aは信号遅延線で
あり、回路3aは、エミツタピーキング法による
画質補正回路であり、可変抵抗器VR1を変化させ
ると周波数対振幅特性も可変にしうる。ただしエ
ミツタピーキング回路は第6図のb′のような遅延
特性になる。従つて、この総合特性は第6図の
d′の,,のいずれの特性をも得ることがで
きる。なお、回路3aとしては、第5図の回路を
使用することも可能である。この場合には回路1
aは総合係数m<1のものを構成すればよい。
FIG. 7 shows a first means for realizing this. 1a is a group delay characteristic correction circuit having the characteristic c' in FIG. 6, which is capable of changing only the group delay circuit without changing the amplitude characteristic. The output of the circuit 1a is supplied via a signal delay circuit 2a and an image quality adjustment circuit 3a to a circuit for varying frequency versus amplitude characteristics, and the output signal is supplied from B to a subsequent stage. An example of a circuit with the characteristics shown in FIG. 6 is shown in FIG. Blocks surrounded by broken lines and labeled with symbols correspond to those in FIG. The circuit 1a is constituted by a lattice circuit, and the inductors L 1 and L 2 are wound with a coupling coefficient of 1. By changing the impedance of inductor L 3 or capacitor C 3 in this circuit, it is possible to obtain changes as shown in c' and , in FIG. 6. The circuit 2a is a signal delay line, and the circuit 3a is an image quality correction circuit using the emitter peaking method, and by changing the variable resistor VR1 , the frequency versus amplitude characteristic can also be made variable. However, the emitter peaking circuit has a delay characteristic like b' in FIG. Therefore, this comprehensive characteristic is shown in Figure 6.
It is possible to obtain both properties of d′. Note that it is also possible to use the circuit shown in FIG. 5 as the circuit 3a. In this case, circuit 1
It is sufficient that a has a total coefficient m<1.

なお、色復調信号は回路1aの出力から供給す
れば、色信号と輝度信号との厳密な調整が可能で
ある。
Note that if the color demodulation signal is supplied from the output of the circuit 1a, precise adjustment of the color signal and the luminance signal is possible.

第8図に第2の手段を示す。1bは、信号遅延
線を切替える回路で、それぞれ群遅延特性が異な
るものを用い、その遅延特性は第6図のc′のよう
に特性の変化したもので、振幅特性が等しいもの
を用いる。2bは、周波数対振幅特性を可変させ
る回路である。第10図に第8図の回路例を示
す。破線の部分が第8図のブロツクと対応するよ
うになつている。1bは、外部により遅延線DL
を切り替えられるような構成になつている。両ス
イツチSW1,SW1は連動になつている。なおこの
スイツチは、機械的なものでも、電子的なもので
もよい。2bは第9図の3aと同じエミツタピー
キング回路であるので説明を省略する。なお、第
9図の場合と同様に、2bは第5図の回路も使用
可能であるが、この場合は、遅延線DLのそれぞ
れの群遅延特性を変える必要があるのはいうまで
もない。要するに、入力信号が第1図のA,C,
Dのものを受信したとき、補正特性が第6図のd
の,,のようになるようにするものであ
る。
FIG. 8 shows a second means. Reference numeral 1b designates a circuit for switching signal delay lines, each having a different group delay characteristic, whose delay characteristic changes as shown in c' in FIG. 6, and having the same amplitude characteristic. 2b is a circuit for varying frequency versus amplitude characteristics. FIG. 10 shows an example of the circuit shown in FIG. 8. The broken line portion corresponds to the block in FIG. 1b is externally connected to the delay line DL.
The configuration is such that it can be switched. Both switches SW1 and SW1 are interlocked. Note that this switch may be mechanical or electronic. Since 2b is the same emitter peaking circuit as 3a in FIG. 9, its explanation will be omitted. As in the case of FIG. 9, the circuit of FIG. 5 can also be used for 2b, but it goes without saying that in this case, it is necessary to change the group delay characteristics of each delay line DL. In short, if the input signals are A, C,
When D is received, the correction characteristic is d in Figure 6.
This is to make it look like this.

以上の通りであるから、本発明を使用すれば、
アンテナのミスマツチングや、近接ゴースト等の
歪みによる入力波形の歪みを補正することができ
るので、最適な再生画質を得ることができる。
As described above, if the present invention is used,
Since input waveform distortion caused by antenna mismatching, proximity ghost, etc. can be corrected, optimal reproduced image quality can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は入力信号の歪みを示す波形図、第2図
は本発明の第1の実施例のブロツク回路図、第3
図および第4図は第2図の各部の信号の波形図、
第5図は第2図の回路例を示す図、第6図は群遅
延特性と波形との関係図、第7図は本発明の第2
の実施例のブロツク回路図、第8図は本発明の第
3の実施例のブロツク回路図、第9図は第7図の
具体例を示す図、第10図は第8図の具体例を示
す図である。 1…2次微分回路、2…遅延回路、3…加算回
路、4…周波数対振巾特性を変えうる回路、1a
…群遅延特性補正回路、2a…信号遅延回路、3
a…画質調整回路、1b…遅延線切替回路、2b
…周波数対振巾特性を変えうる回路。
FIG. 1 is a waveform diagram showing distortion of an input signal, FIG. 2 is a block circuit diagram of the first embodiment of the present invention, and FIG.
The figure and Figure 4 are waveform diagrams of the signals at each part in Figure 2,
5 is a diagram showing an example of the circuit shown in FIG. 2, FIG. 6 is a diagram showing the relationship between group delay characteristics and waveforms, and FIG.
8 is a block circuit diagram of the third embodiment of the present invention, FIG. 9 is a diagram showing a specific example of FIG. 7, and FIG. 10 is a diagram showing a specific example of FIG. 8. FIG. 1...Second-order differentiator circuit, 2...Delay circuit, 3...Addition circuit, 4...Circuit that can change frequency versus amplitude characteristics, 1a
...Group delay characteristic correction circuit, 2a...Signal delay circuit, 3
a... Image quality adjustment circuit, 1b... Delay line switching circuit, 2b
...A circuit that can change the frequency versus amplitude characteristics.

Claims (1)

【特許請求の範囲】 1 入力信号を第1と第2の2信号に分け、第1
の信号を遅延時間を変えうる遅延回路に加え、第
2の信号を2次微分回路に加え、上記遅延回路に
よつて遅延をうけた第1の信号と2次微分処理さ
れた第2の信号とを合成回路にて合成し、この合
成した信号を周波数対振幅特性を変えうる回路に
供給することを特徴とする画質調整装置。 2 入力信号を群遅延特性を変えうる群遅延特性
補正回路に加え、この群遅延特性補正回路の出力
を信号遅延回路に加え、前記信号遅延回路の出力
を周波数対振幅特性を変えうる回路に供給するこ
とを特徴とする画質調整装置。
[Claims] 1. An input signal is divided into two signals, a first signal and a second signal.
A signal is added to a delay circuit that can change the delay time, and a second signal is added to a second-order differentiator circuit, and the first signal delayed by the delay circuit and the second signal subjected to second-order differentiation processing are obtained. An image quality adjustment device characterized in that a synthesis circuit synthesizes the signals and supplies the synthesized signal to a circuit that can change frequency versus amplitude characteristics. 2. Adding the input signal to a group delay characteristic correction circuit that can change group delay characteristics, adding the output of this group delay characteristic correction circuit to a signal delay circuit, and supplying the output of the signal delay circuit to a circuit that can change frequency versus amplitude characteristics. An image quality adjustment device characterized by:
JP12317179A 1979-09-27 1979-09-27 Picture quality regulator Granted JPS5647174A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12317179A JPS5647174A (en) 1979-09-27 1979-09-27 Picture quality regulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12317179A JPS5647174A (en) 1979-09-27 1979-09-27 Picture quality regulator

Publications (2)

Publication Number Publication Date
JPS5647174A JPS5647174A (en) 1981-04-28
JPS6248946B2 true JPS6248946B2 (en) 1987-10-16

Family

ID=14853934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12317179A Granted JPS5647174A (en) 1979-09-27 1979-09-27 Picture quality regulator

Country Status (1)

Country Link
JP (1) JPS5647174A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6442252U (en) * 1987-09-09 1989-03-14

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6312616Y2 (en) * 1979-09-28 1988-04-11
JPH0736746B2 (en) * 1986-09-01 1995-04-26 日清製粉株式会社 Germ drink

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5396928U (en) * 1977-01-10 1978-08-07

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6442252U (en) * 1987-09-09 1989-03-14

Also Published As

Publication number Publication date
JPS5647174A (en) 1981-04-28

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