JPS6312616Y2 - - Google Patents

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Publication number
JPS6312616Y2
JPS6312616Y2 JP1979134162U JP13416279U JPS6312616Y2 JP S6312616 Y2 JPS6312616 Y2 JP S6312616Y2 JP 1979134162 U JP1979134162 U JP 1979134162U JP 13416279 U JP13416279 U JP 13416279U JP S6312616 Y2 JPS6312616 Y2 JP S6312616Y2
Authority
JP
Japan
Prior art keywords
circuit
delay
delay circuit
video signal
phase lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1979134162U
Other languages
Japanese (ja)
Other versions
JPS5652367U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1979134162U priority Critical patent/JPS6312616Y2/ja
Publication of JPS5652367U publication Critical patent/JPS5652367U/ja
Application granted granted Critical
Publication of JPS6312616Y2 publication Critical patent/JPS6312616Y2/ja
Expired legal-status Critical Current

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Description

【考案の詳細な説明】 本考案はテレビジヨン受像機における画質補正
回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image quality correction circuit in a television receiver.

一般に画像の鮮鋭度を上げるために、映像信号
のレベル急変部分にプリシユートあるいはオーバ
ーシユートをつけ、輪郭部分を強調する。この場
合オーバーシユートのみを与える方法とプリシユ
ートとオーバーシユートの両方を与える方法があ
るが、視覚特性上後者の方が鮮鋭度がよいと感じ
る。オーバーシユートは映像増幅回路で、エミツ
タピーキング等により容易につけることができる
が、プリシユートを付加するについては次のよう
な方式がある。第1は二次微分方式であつて、映
像信号を通過させる低域通過回路と、映像信号を
二次微分する輪郭強調高域通過回路とを設け、両
回路出力を合成し、映像信号にプリシユートとオ
ーバーシユートをつける。第2に映像中間周波増
幅回路で群遅延時間の補正を行いプリシユートを
つけ、映像増幅回路でオーバーシユートをつける
方式がある。第1の方式は低域通過回路、輪郭強
調高域通過回路そして合成回路を必要とし、回路
が複雑で部品点数も多い。又第2の方式では、映
像中間周波増幅回路で群遅延時間を変えるため、
クロマ(CHROMA)回路の位相に影響を与えぬ
よう配慮する必要がある。又ピークAGC回路を
使用しているときはAGC電圧への影響を、さら
に同期信号にもプリシユートがつくのでそのため
の影響も考慮せねばならず設計が複雑になる。
Generally, in order to increase the sharpness of an image, a preshoot or an overshoot is applied to parts where the level of the video signal suddenly changes to emphasize the outline parts. In this case, there are two methods: one that provides only overshoot, and one that provides both preshoot and overshoot, but I feel that the latter provides better sharpness in terms of visual characteristics. Overshoot can be easily added using emitter peaking in a video amplification circuit, but the following methods are available for adding preshoot. The first method is a second-order differential method, which includes a low-pass circuit that passes the video signal and a high-pass circuit that emphasizes contours that performs second-order differentiation of the video signal, and combines the outputs of both circuits and converts the output into a video signal. and overshoot. The second method is to use a video intermediate frequency amplification circuit to correct the group delay time and add a preshoot, and a video amplification circuit to add an overshoot. The first method requires a low-pass circuit, an edge-enhancing high-pass circuit, and a synthesis circuit, and the circuit is complex and has a large number of parts. In the second method, the group delay time is changed using the video intermediate frequency amplification circuit, so
Care must be taken not to affect the phase of the CHROMA circuit. Furthermore, when a peak AGC circuit is used, the design becomes complicated as the influence on the AGC voltage and the synchronization signal also have pre-cuts, which must be taken into consideration.

第3に遅延回路の利用がある。第1図は3種の
遅延回路A,B,Cの周波数特性を、第2図は矩
形波特性を、そして第3図は群遅延特性をそれぞ
れ示している。遅延回路Aは第1図aに示すよう
に搬送色信号成分(3.58MHz)に対し十分な減衰
を与えるが第3図aに示すごとく群遅延時間特性
が波状になるため、第2図aのごとくリンキング
を生ずる。遅延回路B,Cは第2図b,cに示す
ようにリンキングがないか、又わずかであるが、
第1図b,cのごとく3.58MHzを減衰させないの
で、別にトラツプ回路を設ける必要がある。第4
図は遅延回路Aと同じく特定周波数を減衰させ得
る遅延回路で、D1は遅延素子、R0は整合抵抗で
ある。cは抵抗R1,R2、コイルL1、コンデンサ
C1からなるトラツプ回路が並列に、dは抵抗R3
R4、コイルL2、コンデンサC2からなるトラツプ
回路が直列に接続されている。しかしながら、前
述のごとく、このような構成でプリシユートとオ
ーバーシユートの両特性を満足することは困難
で、別に二次微分回路を設けている。従つて回路
構成が複雑になる欠点がある。
Thirdly, there is the use of delay circuits. FIG. 1 shows the frequency characteristics of three types of delay circuits A, B, and C, FIG. 2 shows the rectangular wave characteristics, and FIG. 3 shows the group delay characteristics. Delay circuit A provides sufficient attenuation to the carrier color signal component (3.58MHz) as shown in Figure 1a, but the group delay time characteristic becomes wavy as shown in Figure 3a. This results in linking. Delay circuits B and C have no or only slight linking, as shown in Figure 2b and c.
Since 3.58MHz is not attenuated as shown in Fig. 1b and c, it is necessary to provide a separate trap circuit. Fourth
The figure shows a delay circuit that can attenuate a specific frequency like delay circuit A, where D 1 is a delay element and R 0 is a matching resistor. c is resistance R 1 , R 2 , coil L 1 , capacitor
A trap circuit consisting of C 1 is connected in parallel, d is a resistor R 3 ,
A trap circuit consisting of R 4 , coil L 2 and capacitor C 2 is connected in series. However, as described above, it is difficult to satisfy both the preshoot and overshoot characteristics with such a configuration, so a second-order differentiator circuit is provided separately. Therefore, there is a drawback that the circuit configuration becomes complicated.

本考案は上述の点に鑑み、特定周波数を減衰さ
せるトラツプ付の遅延回路でプリシユートをつ
け、該遅延回路に連なる映像増幅回路でエミツタ
ピーキング等によりオーバーシユートをつける画
像補正回路を提供するものである。
In view of the above-mentioned points, the present invention provides an image correction circuit that applies a preshoot using a delay circuit with a trap that attenuates a specific frequency, and applies an overshoot using emitter peaking or the like using a video amplification circuit connected to the delay circuit. It is.

第5図は本考案の一実施例を示す接続図であ
る。1は映像信号の入力端子、R5,R6は整合用
の抵抗、2は搬送色信号成分(3.58MHz)のトラ
ツプ付遅延回路、3は映像増幅回路、4はエミツ
タピーキング回路、5は出力端子である。入力端
子1に入力する映像信号はトラツプ付遅延回路2
でプリシコートがつけられ、さらにエミツタピー
キング回路4でオーバーシユートがつけられ出力
端子5に出力される。第6図はトラツプ付遅延回
路2の一実施例であり、コイルL3、コンデンサ
C3がトラツプ回路を構成し、コイルL4〜L7、コ
ンデンサC4〜L7が遅延回路を構成する。又第7
図はエミツタピーキング回路の一例で、TRはト
ランジスタ、VRは可変抵抗器で、抵抗R8、コイ
ルL8、コンデンサC8がピーキング回路を構成す
る。
FIG. 5 is a connection diagram showing an embodiment of the present invention. 1 is a video signal input terminal, R 5 and R 6 are matching resistors, 2 is a delay circuit with a trap for the carrier color signal component (3.58MHz), 3 is a video amplification circuit, 4 is an emitter peaking circuit, and 5 is an emitter peaking circuit. It is an output terminal. The video signal input to input terminal 1 is sent to delay circuit 2 with trap.
A precipitate is added at the emitter peaking circuit 4, and an overshoot is added at the emitter peaking circuit 4, and the signal is output to the output terminal 5. FIG. 6 shows an embodiment of the delay circuit 2 with a trap, which includes a coil L 3 and a capacitor.
C3 constitutes a trap circuit, and coils L4 to L7 and capacitors C4 to L7 constitute a delay circuit. Also the 7th
The figure shows an example of an emitter peaking circuit, where TR is a transistor, VR is a variable resistor, and resistor R 8 , coil L 8 , and capacitor C 8 constitute the peaking circuit.

第8図、第9図、第10図はトラツプ付遅延回
路2の周波数特性、矩形波特性及び群遅延特性を
それぞれ示す特性図である。第8図e,fはトラ
ツプの特性を違えた場合を、又第10図g,h,
iは最大群遅延を生じる周波数を違えた場合を示
している。群遅延時間の進む周波数成分の割合で
プリシユートの幅を変化でき、進み時間の大小で
プリシユートの大きさを変えることができる。又
群遅延時間が進み始める周波数は、クロマ信号と
の関係で遅延時間が適正となるよう、0.5MHzよ
り高い周波数とする。かつ群遅延特性は全体の周
波数特性及び第7図に示すエミツタピーキング回
路の特性に応じて第10図g,h,iに示すよう
に、最大群遅延時間及びそれを与える周波数を適
宜選択する。
FIGS. 8, 9, and 10 are characteristic diagrams showing the frequency characteristics, rectangular wave characteristics, and group delay characteristics of the trap-equipped delay circuit 2, respectively. Figures 8e and f show cases with different trap characteristics, and Figures 10g and h,
i indicates the case where the frequency at which the maximum group delay occurs is different. The width of the pre-cut can be changed by changing the ratio of frequency components in which the group delay time advances, and the size of the pre-cut can be changed by changing the advance time. Also, the frequency at which the group delay time begins to advance is set to be higher than 0.5MHz so that the delay time is appropriate in relation to the chroma signal. As for the group delay characteristics, the maximum group delay time and the frequency that provides it are appropriately selected as shown in Fig. 10g, h, and i according to the overall frequency characteristics and the characteristics of the emitter peaking circuit shown in Fig. 7. .

以上述べたように本考案によれば特定の周波数
を減衰させる遅延回路によりプリシユートをつ
け、該遅延回路に縦続接続する映像増幅回路でオ
ーバーシユートをつける。従つて各回路の構成が
簡単であると同時に、他の回路に影響を及ぼさな
いので設計が容易になる。すなわちプリシユート
の幅と大きさは、トラツプ付遅延回路の群遅延時
間の進み位相の周波数の選定と、その進み時間の
設定とにより行う。オーバーシユートはエミツタ
ピーキング回路でその幅と大きさを調整する。又
このような機能を有する素子をICで構成するこ
とができ、トラツプ回路、遅延回路及び画像補正
回路を一つにまとめられるので、ICのピン数の
減少等集積化に役立つ。また、本考案によれば遅
延回路で搬送色信号成分を減衰するようにしてい
るので、映像増幅回路には搬送色信号成分を含ま
ない信号が入力され、補正された映像信号は鮮鋭
で色妨害が除去されたものとなる。
As described above, according to the present invention, a preshoot is provided by a delay circuit that attenuates a specific frequency, and an overshoot is provided by a video amplification circuit cascaded to the delay circuit. Therefore, the configuration of each circuit is simple, and at the same time, design is facilitated because other circuits are not affected. That is, the width and magnitude of the precut are determined by selecting the frequency of the lead phase of the group delay time of the trapped delay circuit and setting the lead time. The width and size of the overshoot is adjusted using an emitter peaking circuit. Furthermore, since an element having such a function can be constituted by an IC, and a trap circuit, a delay circuit, and an image correction circuit can be integrated into one, it is useful for integration such as reducing the number of pins of the IC. In addition, according to the present invention, the carrier color signal component is attenuated by the delay circuit, so a signal that does not include the carrier color signal component is input to the video amplification circuit, and the corrected video signal is sharp and has no color interference. will be removed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は遅延回路の周波数特性図、第2図は同
矩形波特性図、第3図は同群遅延特性図である。
第4図は従来のトラツプ回路と遅延回路とを直、
並列接続した接続図、第5図は本考案の一実施に
係る接続図、第6図はトラツプ付遅延回路の一構
成例を示す接続図、第7図はエミツタピーキング
回路の接続図、第8図、第9図、第10図はそれ
ぞれ本考案に係るトラツプ付遅延回路の周波数特
性、矩形波応答及び群遅延特性を示す特性図であ
る。 2……トラツプ付遅延回路、3……映像増幅回
路、4……エミツタピーキング回路。
FIG. 1 is a frequency characteristic diagram of the delay circuit, FIG. 2 is a rectangular wave characteristic diagram thereof, and FIG. 3 is a group delay characteristic diagram thereof.
Figure 4 shows the conventional trap circuit and delay circuit.
5 is a connection diagram of one embodiment of the present invention; FIG. 6 is a connection diagram showing an example of the configuration of a delay circuit with a trap; FIG. 7 is a connection diagram of an emitter peaking circuit; 8, 9, and 10 are characteristic diagrams showing the frequency characteristics, rectangular wave response, and group delay characteristics of the trap-equipped delay circuit according to the present invention, respectively. 2...delay circuit with trap, 3...video amplification circuit, 4...emitter peaking circuit.

Claims (1)

【実用新案登録請求の範囲】 搬送色信号成分である3.58MHzの周波数成分を
特に減衰させると共に、その群遅延時間が約
0.5MHzより進み位相となり、位相進みが周波数
の増加と共に単調に増大し1.5〜3MHzで最大位相
進みとなり、続いて位相進みが単調に減少する特
性を有し、入力として映像信号が供給され、出力
としてプリシユートがつけられた映像信号を得る
遅延回路と、 この遅延回路に縦続接続され、前記遅延回路の
出力映像信号にオーバーシユートをつける映像増
幅回路とを具備したことを特徴とする画質補正回
路。
[Claims for Utility Model Registration] The frequency component of 3.58MHz, which is the carrier color signal component, is particularly attenuated, and its group delay time is approximately
The phase lead starts from 0.5MHz, the phase lead increases monotonically as the frequency increases, reaches the maximum phase lead at 1.5 to 3MHz, and then the phase lead decreases monotonically.A video signal is supplied as input, and the output is An image quality correction circuit comprising: a delay circuit that obtains a pre-shot video signal; and a video amplification circuit that is cascade-connected to the delay circuit and applies an overshoot to the output video signal of the delay circuit. .
JP1979134162U 1979-09-28 1979-09-28 Expired JPS6312616Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1979134162U JPS6312616Y2 (en) 1979-09-28 1979-09-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1979134162U JPS6312616Y2 (en) 1979-09-28 1979-09-28

Publications (2)

Publication Number Publication Date
JPS5652367U JPS5652367U (en) 1981-05-08
JPS6312616Y2 true JPS6312616Y2 (en) 1988-04-11

Family

ID=29365732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1979134162U Expired JPS6312616Y2 (en) 1979-09-28 1979-09-28

Country Status (1)

Country Link
JP (1) JPS6312616Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59126059U (en) * 1983-02-12 1984-08-24 寺田 富美雄 tombstone cover

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5647174A (en) * 1979-09-27 1981-04-28 Matsushita Electric Ind Co Ltd Picture quality regulator

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4938133U (en) * 1972-07-05 1974-04-04
JPS5396928U (en) * 1977-01-10 1978-08-07

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5647174A (en) * 1979-09-27 1981-04-28 Matsushita Electric Ind Co Ltd Picture quality regulator

Also Published As

Publication number Publication date
JPS5652367U (en) 1981-05-08

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