JPS6248006U - - Google Patents

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Publication number
JPS6248006U
JPS6248006U JP14023585U JP14023585U JPS6248006U JP S6248006 U JPS6248006 U JP S6248006U JP 14023585 U JP14023585 U JP 14023585U JP 14023585 U JP14023585 U JP 14023585U JP S6248006 U JPS6248006 U JP S6248006U
Authority
JP
Japan
Prior art keywords
demodulation circuit
heads
data
pll
speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14023585U
Other languages
Japanese (ja)
Other versions
JPH0725902Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14023585U priority Critical patent/JPH0725902Y2/en
Publication of JPS6248006U publication Critical patent/JPS6248006U/ja
Application granted granted Critical
Publication of JPH0725902Y2 publication Critical patent/JPH0725902Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の高速再生復調回路の一実施
例のブロツク図であり、第2図は、高速再生時の
トラツクに対するヘツドの摺接を説明する図であ
り、第3図は、記録されたアジマス角度の違いに
より再生信号が変化することを説明する図である
。 1:PLL回路、7:アナログスイツチ、8:
データ復調回路、V1,V2:基準信号、TA:
Aのアジマス角度で記録されたトラツク、TB:
Bのアジマス角度で記録されたトラツク、HA:
Aヘツドの摺接軌跡、HB:Bヘツドの摺接軌跡
、a:Aヘツドで信号を横切る間隔、b:Bヘツ
ドで信号を横切る間隔。
FIG. 1 is a block diagram of one embodiment of the high-speed reproduction demodulation circuit of the present invention, FIG. 2 is a diagram illustrating the sliding contact of the head with respect to the track during high-speed reproduction, and FIG. FIG. 4 is a diagram illustrating how a reproduced signal changes depending on a difference in azimuth angle. 1: PLL circuit, 7: Analog switch, 8:
Data demodulation circuit, V1, V2: reference signal, TA:
Track recorded at azimuth angle of A, TB:
Track recorded at azimuth angle B, HA:
A sliding contact trajectory of head A, HB: sliding contact trajectory of B head, a: interval at which the A head crosses the signal, b: interval at which the B head crosses the signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 約常再生より高速でテープを走行させ、アジマ
ス角度を相違させてドラムに配設された2個のヘ
ツドを前記テープに記録されたトラツクに対して
斜めに摺接させ、前記ヘツドで再生される再生信
号をデータ復調回路とPLL回路に入力させ、こ
のPLL回路の出力により前記データ復調回路で
前記再生信号からデータを読み取り復調データと
して出力する高速再生復調回路において、前記2
個のヘツドを切り換えるヘツド切換信号によつて
前記PLL解路に与えられる基準信号を切り換え
るようにしたことを特徴とする高速再生復調回路
The tape is run at a higher speed than normal playback, and two heads disposed on the drum are brought into sliding contact diagonally with respect to the track recorded on the tape at different azimuth angles, and the track is played back by the heads. In the high-speed reproduction demodulation circuit, the reproduction signal is input to a data demodulation circuit and a PLL circuit, and the data demodulation circuit reads data from the reproduction signal according to the output of the PLL circuit and outputs it as demodulated data.
1. A high-speed regeneration demodulation circuit characterized in that a reference signal applied to said PLL solution path is switched by a head switching signal for switching between two heads.
JP14023585U 1985-09-13 1985-09-13 High-speed reproduction demodulation circuit Expired - Lifetime JPH0725902Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14023585U JPH0725902Y2 (en) 1985-09-13 1985-09-13 High-speed reproduction demodulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14023585U JPH0725902Y2 (en) 1985-09-13 1985-09-13 High-speed reproduction demodulation circuit

Publications (2)

Publication Number Publication Date
JPS6248006U true JPS6248006U (en) 1987-03-25
JPH0725902Y2 JPH0725902Y2 (en) 1995-06-07

Family

ID=31046892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14023585U Expired - Lifetime JPH0725902Y2 (en) 1985-09-13 1985-09-13 High-speed reproduction demodulation circuit

Country Status (1)

Country Link
JP (1) JPH0725902Y2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63188867A (en) * 1987-01-31 1988-08-04 Kenwood Corp Clock signal reproducing device
JPS63317965A (en) * 1987-06-20 1988-12-26 Sanyo Electric Co Ltd Rotary head type digital magnetic reproducing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63188867A (en) * 1987-01-31 1988-08-04 Kenwood Corp Clock signal reproducing device
JPS63317965A (en) * 1987-06-20 1988-12-26 Sanyo Electric Co Ltd Rotary head type digital magnetic reproducing device

Also Published As

Publication number Publication date
JPH0725902Y2 (en) 1995-06-07

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