JPS6324705U - - Google Patents

Info

Publication number
JPS6324705U
JPS6324705U JP11688186U JP11688186U JPS6324705U JP S6324705 U JPS6324705 U JP S6324705U JP 11688186 U JP11688186 U JP 11688186U JP 11688186 U JP11688186 U JP 11688186U JP S6324705 U JPS6324705 U JP S6324705U
Authority
JP
Japan
Prior art keywords
circuit
hold pulse
hold
noise removal
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11688186U
Other languages
Japanese (ja)
Other versions
JPH075522Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11688186U priority Critical patent/JPH075522Y2/en
Publication of JPS6324705U publication Critical patent/JPS6324705U/ja
Application granted granted Critical
Publication of JPH075522Y2 publication Critical patent/JPH075522Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

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  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は実施例のブロツク図、第2図、第3図
は実施例の回路図、第4図は従来例のブロツク図
、第5図、第6図は説明のための波形図である。 10……モノマルチ、13……時定数回路、1
4……スイツチ手段。
Fig. 1 is a block diagram of the embodiment, Figs. 2 and 3 are circuit diagrams of the embodiment, Fig. 4 is a block diagram of the conventional example, and Figs. 5 and 6 are waveform diagrams for explanation. . 10...Mono multi, 13...Time constant circuit, 1
4... Switch means.

補正 昭62.10.1 図面の簡単な説明を次のように補正する。 明細書第6頁第18行目を下記の如く補正する
。 「第5図、第6図は説明のための波形図である
。又、第7図は他の実施例の回路図である。」
Amendment October 1, 1982 The brief description of the drawing is amended as follows. Page 6, line 18 of the specification is amended as follows. ``Figures 5 and 6 are waveform diagrams for explanation. Also, Figure 7 is a circuit diagram of another embodiment.''

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 周波数変調音声信号が複数のトラツクに記録さ
れた記録媒体から複数の回転ヘツドを用いて再生
する磁気記録再生装置の雑音除去回路において、
復調音声信号の前値保持を行なうホールド回路と
、ヘツド切換信号に基づきホールドパルスを作成
するホールドパルス発生回路と、テープ速度判別
信号に基づきホールドパルス幅を変更するスイツ
チ手段を備えることを特徴とする雑音除去回路。
In a noise removal circuit for a magnetic recording and reproducing device that reproduces frequency modulated audio signals from a recording medium recorded on a plurality of tracks using a plurality of rotating heads,
The present invention is characterized by comprising a hold circuit for holding the previous value of the demodulated audio signal, a hold pulse generation circuit for generating a hold pulse based on a head switching signal, and a switch means for changing the hold pulse width based on a tape speed discrimination signal. Noise removal circuit.
JP11688186U 1986-07-30 1986-07-30 Noise elimination circuit Expired - Lifetime JPH075522Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11688186U JPH075522Y2 (en) 1986-07-30 1986-07-30 Noise elimination circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11688186U JPH075522Y2 (en) 1986-07-30 1986-07-30 Noise elimination circuit

Publications (2)

Publication Number Publication Date
JPS6324705U true JPS6324705U (en) 1988-02-18
JPH075522Y2 JPH075522Y2 (en) 1995-02-08

Family

ID=31001885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11688186U Expired - Lifetime JPH075522Y2 (en) 1986-07-30 1986-07-30 Noise elimination circuit

Country Status (1)

Country Link
JP (1) JPH075522Y2 (en)

Also Published As

Publication number Publication date
JPH075522Y2 (en) 1995-02-08

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