JPS6246562A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form an IC, which operates at high speed and has the high degree of integration and excellent mass productivity, by modulating conductivity between a pair of electrodes having ohmic properties to holes formed in a first semiconductor layer by injecting electrons to a second semiconductor layer from a third semiconductor layer. CONSTITUTION:Holes are induced on the reverse side of a hetero-interface between a first semiconductor layer 12 and a second semiconductor layer 13 in response to the quantity of electrons injected toward an electrode 15 along the hetero-interface from a control electrode 17, and a hole channel 19 having high conductivity is shaped. The channel holes are accelerated between electrodes 15, 16, and large currents can be made to flow. That is, the channel fills the same role as a field-effect transistor FET using a hetero-interface having the different energy levels of valence bands as a channel. That is, the modulation mode of currents means conductivity modulation by electron injection, and the channel functions in a FET manner.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device that operates at high speed, and particularly to a semiconductor device that uses holes as carriers.

[Prior art and its problems]

In recent years, research and development of ultrahigh-speed devices as devices for high-speed computers has been actively conducted. Among such ultra-high-speed devices, bipolar transistors are attracting attention as they have a large current driving capability. In particular, as a high-performance bipolar transistor using a compound semiconductor such as 0aAs, a so-called hetero bipolar transistor (
HBT) and its IC implementation are being researched.

For example, the 1981 International Conference on Electronic Devices (Inter
national electron devices
Meeting) Digest, pages 629-632
As shown in the page, GaAs is used for the base and Aβ is used for the emitter.
The npn type using GaAs has been well studied. However, HBTs have extremely complex structures and processes, and many problems remain in achieving high integration. In addition, the capacity between the collector bases is especially large, and the high speed is also limited. Furthermore, although a complementary type structure has great advantages in achieving high integration, the current situation is that a pnp type structure in which holes are used as carriers has not been obtained.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a novel semiconductor device that uses holes as carriers and has a large current drive capability and is suitable for ultra-high-speed ICs.

[Structure of the invention]

In the semiconductor device of the present invention, a low impurity density or p-type second semiconductor having a larger electron affinity and a sum of electron affinity and band gap than the first semiconductor layer is formed on the first semiconductor layer with a low impurity density. layer and a third semiconductor layer for injecting electrons, comprising a pair of ohmic electrodes formed with respect to the first semiconductor layer, and a pair of ohmic electrodes formed in the first semiconductor layer. In contrast, the conductivity between the pair of ohmic electrodes is modulated by injecting electrons from the third semiconductor layer to the second semiconductor layer.

[Detailed Description of Structure] FIG. 1 is a schematic structural sectional view showing an example of the basic structure of a semiconductor device according to the present invention.

This semiconductor device includes a high-resistance substrate 11, for example, a semi-insulating I
A first semiconductor layer 12 having a low impurity density, for example, an undoped In/l'As layer, and a second semiconductor layer having both a larger electron affinity and a sum of electron affinity and band gap than the first semiconductor layer are formed on the nP substrate. A semiconductor layer 13, for example an undoped InP layer, a third semiconductor layer 14 for electron injection, for example an n''-InP layer, and a pair of ohmic electrodes 15 formed on the first semiconductor layer 12. 16, for example p”
-InA! As regions 15a, 16a and Au-Zn ohmic electrode 15b.

A pair of electrodes consisting of 16b and p''-InP 1
4 is loaded with an ohmic control electrode 17.

A band diagram in a thermal equilibrium state under the control electrode 17 of the semiconductor device having the above structure is shown in FIG. 2, where E is shown. , EF, and EV represent the energy levels of the lower end of the conduction band, the Fermi level, and the upper end of the valence band, respectively.

Now, consider the case where the electrode 15 is grounded, a sufficiently large negative voltage is applied to the control electrode 17, and electrons are injected. FIG. 3 shows a band diagram under the control electrode 17 in this case. In the figure, the injected electrons are indicated by marks, and the state of injection is indicated by arrows. At this time, the electron is the first
is accumulated on the second semiconductor layer side of the hetero interface between the first semiconductor layer 12 and the second semiconductor layer 13 due to the difference in the energy level of the conduction band between the semiconductor layer 12 and the second semiconductor layer 13. . The accumulated electrons are indicated by 18. These electrons move along the heterointerface, but at the same time induce holes to maintain charge neutrality. In this case, the induced holes are accumulated on the first semiconductor layer side due to the difference in the energy level of the conduction band between the first semiconductor layer 12 and the second semiconductor layer 13. The accumulated holes are indicated by 0 mark 19.

FIG. 4 shows the flow of holes and electrons when a negative voltage is applied to the electrode 16 in this state. Holes are induced on the opposite side of the hetero interface in proportion to the amount of electrons injected from the control electrode 17 toward the electrode 15 along the hetero interface between the first semiconductor layer 12 and the second semiconductor layer 13, A highly conductive hole channel is formed.

This channel hole is accelerated by the electric field between the electrodes 15 and 16, and a large current can flow. That is, the channel behaves similar to a field effect transistor (FET) whose channel is a heterointerface having different energy levels in the valence band. That is, the current modulation mode is conductivity modulation by electron injection, and the channel is FET-like.

Here, the ratio of the current in the hole channel to the current flowing out to the control electrode 17, that is, the current amplification factor, is as follows:
And the smaller the outflow of injected electrons, the larger it becomes. In this semiconductor device, the injected electrons are accumulated at the heterojunction interface between the first and second semiconductor layers 12.
The hole 1 is less likely to flow out to the semiconductor layer 12 side, and the hole 1
Since it is located a little apart from 9, it is less likely to be recombined with holes, and therefore less likely to disappear. Furthermore, electrodes 15 and 17
The electric field between them is small, and the electron current is small. Further, holes in the channel are also less likely to flow out to the control electrode 17 side due to the barrier provided by the second semiconductor layer 13. Furthermore, since the hole channel is formed at a high-quality heterointerface with few impurities, the hole becomes extremely fast and the channel current becomes large. Therefore, in the semiconductor device of the present invention, a large current amplification factor can be obtained even when holes are used as carriers. Further, the second semiconductor layer between the control electrode 17 and the electrode 16 is depleted like an FET, and therefore has a small feedback capacitance between the control electrode 17 and the electrode 16 like an FET. That is, this semiconductor device has a simple structure similar to that of an FET, high speed, small parasitic resistance and parasitic capacitance, and realizes large current drive comparable to that of a bipolar transistor.

Note that the InP layer 13 of the second semiconductor layer may be p-type doped, but in this case, the layer 13 is sufficiently thin and n''-p doped.
It is necessary that the number of carriers is completely depleted by the junction depletion layer, and that the number of carriers in the layer 13 as well as in the channel layer 12 in a thermal equilibrium state is negligible with respect to the injected electrons.

〔Example〕

The structure of one embodiment of the semiconductor device of the present invention is shown in FIG.

A semi-insulating InP substrate is used as the substrate 11, and the first semiconductor layer 12 is formed by undoped I with an electron density of 5 XIO" am-3 and a thickness of 3000 by molecular beam epitaxy.
As the nΔj2As layer, and as the second semiconductor layer 13, an undoped InP layer with an electron density of IX1015 cm-' and a thickness of 200 nm, and as the third semiconductor layer 14 for electron injection, Sl was doped with IXIO19am-3. Successively grow a 100-layer n''-InP layer.

Deposit β on the n''-InP layer 1 and then form the electrodes 21 and 22.
A resist pattern is formed to cover the gap, Aβ is etched using this mask, and side etching is further performed to form the control electrode 17. Using the mask again, A
U-Zn vapor deposition, list-off, and heat treatment are performed to form ohmic electrodes 21 and 22.

Control electrode 17 is therefore formed in self-alignment between ohmic electrodes 21 and 22. In this embodiment, these alloy layers also serve as 15a and 15b and 16a and 16b in FIG. Further, using these electrodes as a mask, the n''-InP layer 14 between these electrodes is etched to complete the device.The electrode length of the electrode 17 is 0.5
The distance between the electrodes 21 and 22 is 2 μm.

In this embodiment, the electrode 21 is grounded and the control electrode 17 is applied with a negative voltage of 1 cm, for example, 0.
．． When a negative voltage of 6 V or more is applied, a current flows between the electrodes 21 and 22, and when the negative voltage to the control electrode 17 is increased, that is, the amount of electron injection is increased, the channel current increases exponentially, resulting in a good condition. Transistor operation with high current drive of hole carriers can be obtained.

In the above description, InP and InAβAs are used as the semiconductor layer.
Although we have described an example using semiconductors, it goes without saying that other semiconductors may be used as long as they satisfy the conditions regarding electron affinity and the sum of electron affinity and band gap. Further, although the case where a grown crystal layer is used as the n' layer 14 as an electron injection source has been described, it is clear that it may be formed in the second semiconductor layer 13 by ion implantation.

〔Effect of the invention〕

As described above, according to the present invention, a high-performance transistor capable of high current operation is realized with a simple structure similar to an FET, and it becomes possible to realize a high-speed, highly integrated IC that is excellent in mass production. .

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the basic structure of the semiconductor device of the present invention, FIGS. 2 and 3 are band diagrams for explaining the present invention in detail, and FIG. 4 is a diagram showing the flow of electrons and holes. FIG. 5 is a diagram showing an embodiment of the present invention. 11・・・・・・・・・・・・・・・・・・High resistance board 12・・・・・・・・・・・・・・・・・・・・・
・First semiconductor layer 13・・・・・・・・・・・・・・・
. . . Second semiconductor layer 14 . . .
......Third semiconductor layer 15.16...
・・・・・・・・・・・・P-type ohmic electrode 17・
・・・・・・・・・・・・・・・・・・・・・Control electrode 1
8・・・・・・・・・・・・・・・・・・・Injected electron 19・・・・・・・・・・・・・・・・・・Channel hole substitute People Patent Attorney Yoshiyuki Iwasa Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] (1) A low impurity density or p-type second semiconductor layer having a larger electron affinity and a sum of electron affinity and band gap than the first semiconductor layer, and a p-type second semiconductor layer on the low impurity density first semiconductor layer; a third semiconductor layer for injecting holes formed in the first semiconductor layer, and a pair of ohmic electrodes formed with respect to the first semiconductor layer; The conductivity between a pair of ohmic electrodes is the third
1. A semiconductor device characterized in that modulation is performed by injecting electrons from a semiconductor layer into a second semiconductor layer.