JPS62464B2 - - Google Patents

Info

Publication number
JPS62464B2
JPS62464B2 JP14857182A JP14857182A JPS62464B2 JP S62464 B2 JPS62464 B2 JP S62464B2 JP 14857182 A JP14857182 A JP 14857182A JP 14857182 A JP14857182 A JP 14857182A JP S62464 B2 JPS62464 B2 JP S62464B2
Authority
JP
Japan
Prior art keywords
pulse
counter
pulse train
counts
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP14857182A
Other languages
Japanese (ja)
Other versions
JPS5938661A (en
Inventor
Tadashi Ichioka
Masayuki Terajima
Tomoyasu Hachiro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Electric Manufacturing Co Ltd
Priority to JP14857182A priority Critical patent/JPS5938661A/en
Publication of JPS5938661A publication Critical patent/JPS5938661A/en
Publication of JPS62464B2 publication Critical patent/JPS62464B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01PMEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P3/00Measuring linear or angular speed; Measuring differences of linear or angular speeds
    • G01P3/42Devices characterised by the use of electric or magnetic means
    • G01P3/44Devices characterised by the use of electric or magnetic means for measuring angular speed
    • G01P3/48Devices characterised by the use of electric or magnetic means for measuring angular speed by measuring frequency of generated current or voltage
    • G01P3/481Devices characterised by the use of electric or magnetic means for measuring angular speed by measuring frequency of generated current or voltage of pulse signals
    • G01P3/489Digital circuits therefor

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Linear Or Angular Velocity Measurement And Their Indicating Devices (AREA)
  • Measurement Of Current Or Voltage (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は、可変速回転体の速度をデイジタル的
に検出する速度検出装置に関するものである。 例えば、モータを可変速制御する場合、速度検
出を行うことは速度精度を要求されるものでは不
可欠である。また、高精度の制御を行う場合に
は、アナログ式では限度があり、ドリフトのない
デイジタル式が採用されている。速度精度を上げ
るためには、パルスピツクアツプ等で速度に比例
した周波数のパルス列を得、速度設定パルス列と
比較する方式とするが、単に速度精度の向上だけ
でなく、速度の絶対値を精度良く、しかも定めら
れた時間以内の応答で検出することが要求される
場合が数多くある。この場合にはデイジタル式で
あつても次のような問題点がある。 即ち、デイジタル式では、一般に精度と応答時
間が相反する要素となつており、可変速範囲が広
い場合、全域に亘つて一定の精度が保たれ、応答
時間も一定時間内であることは難しい。 例えば、可変速範囲が1:nであればパルス列
の1パルス間隔は1〜nまで変化し、高速時の精
度を出すために基準クロツクパルス列の周波数を
高くすると、低速時にはカウンタがオーバーフロ
ーしてしまうという不都合が生じ、これを避ける
ためには高速時の精度を犠性にせざるを得なかつ
た。 なお、高速時にはパルス列それ自体を一定時間
カウントし、低速時には周期を測定するなどパル
ス列の周波数により検出方法を切替える方法もあ
るが、検出の応答時間が一定でなく、また精度を
所定の値にするためにはビツト数を多くしなけれ
ばならないなど実用上問題がある。 本発明は上記事情に鑑みてなされたもので、測
定すべきパルス間隔が常に一定となるよう予めパ
ルス列の隣同士のパルス間隔を測定し、パルス列
の何パルス間を測定すべきかを判断することによ
り、精度、応答時間共可変速範囲全域に亘り常に
一定とすることができる速度検出装置を提供する
ことを目的とする。 以下、本発明を図示の実施例に基づいて詳細に
説明する。 第1図は本発明の一実施例を示すもので、1は
パルス列f1の1パルス間隔におけるクロツクパル
スfckの数をカウントするカウンタ、2はこのカ
ウンタ1のカウント結果nと定数kからk/nを演
算する演算器で、小数点以下は切上げとする。3
はこの演算器2の出力をプリセツト値とするプリ
セツトカウンタで、パルス列f1のパルスの立下が
りでゲートが開かれ、以後同パルス列f1のパルス
立下がりでダウンカウントを行い、k/n個をカウ
ントする。4はプリセツトカウンタ3のダウンカ
ウント動作時間、つまりパルス列f1のk/n個のパ
ルス間におけるクロツクパルスfckの数をカウン
トするカウンタ、5はこのカウンタ4の出力m、
前記演算器2の出力k/n、クロツクパルス周波数
ckから
The present invention relates to a speed detection device that digitally detects the speed of a variable speed rotating body. For example, when variable speed control is applied to a motor, speed detection is essential for motors that require speed accuracy. Furthermore, when performing high-precision control, analog systems have their limits, so digital systems with no drift are used. In order to improve speed accuracy, a pulse train with a frequency proportional to the speed is obtained using a pulse pickup, etc., and compared with the speed setting pulse train. Moreover, there are many cases in which detection is required with a response within a predetermined time. In this case, even if it is a digital type, there are the following problems. That is, in a digital system, accuracy and response time are generally contradictory elements, and when the variable speed range is wide, it is difficult to maintain constant accuracy over the entire range and to keep the response time within a constant time. For example, if the variable speed range is 1:n, the pulse interval of the pulse train changes from 1 to n, and if the frequency of the reference clock pulse train is increased to improve accuracy at high speeds, the counter will overflow at low speeds. This caused the inconvenience of storage, and to avoid this, accuracy at high speeds had to be sacrificed. There is also a method of switching the detection method depending on the frequency of the pulse train, such as counting the pulse train itself for a certain period of time at high speeds and measuring the period at low speeds, but the detection response time is not constant, and the accuracy must be set to a predetermined value. This poses practical problems, such as the need to increase the number of bits. The present invention has been made in view of the above circumstances, and it is possible to measure the pulse interval between adjacent pulses in a pulse train in advance so that the pulse interval to be measured is always constant, and to determine how many pulses in the pulse train should be measured. It is an object of the present invention to provide a speed detection device that can keep both accuracy and response time constant over the entire variable speed range. Hereinafter, the present invention will be explained in detail based on illustrated embodiments. FIG. 1 shows an embodiment of the present invention, in which 1 is a counter that counts the number of clock pulses f ck in one pulse interval of pulse train f 1 , and 2 is a counter that counts the count result n of this counter 1 and a constant k to k/ A calculator that calculates n, rounding up the decimal places. 3
is a preset counter that uses the output of this arithmetic unit 2 as a preset value.The gate is opened at the falling edge of the pulse train f1 , and after that, it counts down at the falling edge of the pulse train f1 , and counts down k/n counters. count. 4 is a counter that counts the down-count operation time of the preset counter 3, that is, the number of clock pulses fck between k/n pulses of the pulse train f1 ; 5 is the output m of this counter 4;
From the output k/n of the arithmetic unit 2 and the clock pulse frequency f ck

【式】の演算を行い、入力である パルス列f1の周波数をデイジタルコードで出力す
る演算器、6は回転体7の速度に比例した周波数
のパルス列f1を得るパルスピツクアツプである。 次に、動作を第2図のタイムチヤートを参照し
ながら説明する。カウンタ1においてはパルス列
f1のパルス間隔をクロツクパルスfckによりカウ
ントする。このカウント結果、例えばn1個と定数
kにより演算器2でk/nの演算を行い、小数点以下 を切上げた値を時刻t1にプリセツトカウンタ3に
ロードする。プリセツトカウンタ3ではパルス列
f1のパルス立下がりでゲートが開かれ、以後パル
ス列f1のパルス立下がりでダウンカウントを行
い、k/n個をカウントする。カウンタ4では時刻t1 のパルス立下がりからある時間後に出力されるk/n 個目のパルスの立下がり(時刻t2)までをクロツ
クパルスfckでカウントする。この結果のm1から
演算器5において
A calculator 6 calculates the formula and outputs the frequency of the input pulse train f 1 as a digital code, and 6 is a pulse pickup that obtains the pulse train f 1 with a frequency proportional to the speed of the rotating body 7. Next, the operation will be explained with reference to the time chart shown in FIG. In counter 1, the pulse train
The pulse interval of f1 is counted by the clock pulse fck . Using this count result, for example, n 1 and a constant k, the arithmetic unit 2 calculates k/n 1 , and the value rounded up after the decimal point is loaded into the preset counter 3 at time t 1 . In preset counter 3, pulse train
The gate is opened at the falling edge of the f 1 pulse, and thereafter, a down count is performed at the falling edge of the pulse train f 1 to count 1 k/n. The counter 4 uses a clock pulse fck to count from the falling edge of the pulse at time t1 to the falling edge of the k/n- th pulse (time t2 ) which is output after a certain time. From this result m 1 , in computing unit 5

【式】の演算を行い、 入力であるパルス列f1の周波数をデイジタルコー
ドで出力する。 また、カウンタ1では(k/n−1)個目のパルス とk/n個目のパルスの間隔をカウントし、その結果 n2を用いて演算器2でk/nの演算を行い、その結果 をt2時点で再びプリセツトカウンタ3に入力す
る。この後、前述と同様にカウンタ4においてパ
ルス列f1のパルスカウントを行い(t2〜t3)、その
結果のm2を用いて演算器5で演算を行う。 このような動作を繰返し行つて回転体7の速度
をデイジタル値で出力する。この場合、パルス列
f1の最大値、クロツクパルス周波数fck、定数k
の値は要求される精度、応答時間、可変速範囲に
応じて適宜定める。例えば、f1の最大値が
10KHz、可変速範囲が1:100、応答時間が10m
s、精度が±0.02%であれば、fck=500kHz、
k=5000と設定すると、要求が満たされる。 なお、演算器2,5における演算、タイミング
の管理はマイクロコンピユータを用いて行うが、
演算時間に問題がある場合はテーブルに1/nのデ
ータを持つといつた方法で解決可能である。 以上のように本発明によれば、測定すべきパル
ス間隔が常に一定となるよう予めパルス列の隣同
士のパルスの間隔を測定しパルス列の何パルス間
を測定すべきかを判断しているため、検出の応答
時間、精度は可変速範囲全域に亘つて一定に保た
れ、しかもオーバーフロー等の問題は皆無であ
る。
Calculate [Formula] and output the frequency of the input pulse train f1 as a digital code. In addition, the counter 1 counts the interval between the (k/n 1 - 1)th pulse and the k/n 1st pulse, and the calculation unit 2 uses the result n 2 to calculate k/n 2 . The result is inputted into the preset counter 3 again at time t2 . Thereafter, the counter 4 counts the pulses of the pulse train f1 ( t2 to t3 ) in the same manner as described above, and the arithmetic unit 5 performs calculations using the result m2 . By repeating these operations, the speed of the rotating body 7 is output as a digital value. In this case, the pulse train
Maximum value of f 1 , clock pulse frequency f ck , constant k
The value of is determined as appropriate depending on the required accuracy, response time, and variable speed range. For example, if the maximum value of f 1 is
10KHz, variable speed range 1:100, response time 10m
s, if the accuracy is ±0.02%, f ck = 500kHz,
Setting k=5000 satisfies the request. Note that calculations and timing management in the calculation units 2 and 5 are performed using a microcomputer.
If there is a problem with calculation time, it can be solved by having 1/n data in the table. As described above, according to the present invention, the interval between adjacent pulses in a pulse train is measured in advance so that the pulse interval to be measured is always constant, and it is determined how many pulses in the pulse train should be measured. The response time and accuracy are kept constant over the entire variable speed range, and there are no problems such as overflow.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る速度検出装置の一実施例
を示すブロツク図、第2図は動作説明のためのタ
イムチヤートである。 1及び4……カウンタ、2及び5……演算器、
3……プリセツトカウンタ、6……パルスピツク
アツプ、7……回転体。
FIG. 1 is a block diagram showing an embodiment of the speed detection device according to the present invention, and FIG. 2 is a time chart for explaining the operation. 1 and 4...Counter, 2 and 5...Arithmetic unit,
3...Preset counter, 6...Pulse pick-up, 7...Rotating body.

Claims (1)

【特許請求の範囲】 1 基準クロツクパルスfckを計数して回転体の
回転速度に応じた周波数の入力パルスのパルス間
隔を測定するカウンタと、クロツクパルスカウン
ト数nで定数kを割る演算器と、k/nをプリセツ
ト値として入力パルスの到来毎にダウンカウント
するプリセツトカウンタと、k/n個の入力パルス
測定時間におけるクロツクパルス数mをカウント
するカウンタと、【式】の演算を行つてデ イジタル量の速度検出値を出力する演算器とを具
備してなる速度検出装置。
[Claims] 1. A counter that counts the reference clock pulse fck to measure the pulse interval of an input pulse having a frequency corresponding to the rotational speed of the rotating body, and an arithmetic unit that divides the constant k by the clock pulse count number n. , a preset counter that counts down every time an input pulse arrives with k/n as a preset value, a counter that counts the number of clock pulses m during the measurement time of k/n input pulses, and a digital A speed detection device comprising: a calculation unit that outputs a speed detection value of a quantity;
JP14857182A 1982-08-27 1982-08-27 Apparatus for detecting speed Granted JPS5938661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14857182A JPS5938661A (en) 1982-08-27 1982-08-27 Apparatus for detecting speed

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14857182A JPS5938661A (en) 1982-08-27 1982-08-27 Apparatus for detecting speed

Publications (2)

Publication Number Publication Date
JPS5938661A JPS5938661A (en) 1984-03-02
JPS62464B2 true JPS62464B2 (en) 1987-01-08

Family

ID=15455716

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14857182A Granted JPS5938661A (en) 1982-08-27 1982-08-27 Apparatus for detecting speed

Country Status (1)

Country Link
JP (1) JPS5938661A (en)

Also Published As

Publication number Publication date
JPS5938661A (en) 1984-03-02

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