JPS6246494A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To simplify improvement of a reading speed of a memory device by rapidly discharging a data line selectively performed according to the storing state of a memory element. CONSTITUTION:The data stored in a conductive or a non-conductive state by an NMOS transistor Mm in a memory cell 1 is read as the logic data '1' or '0'. The Mm in a memory state of on is connected to a data line Ld, when an electric potential Vp starts to be lowered, an electric potential Vd of a data line is lowered to a threshold Vth2 of a discharge circuit 3, then an nch MOSFET 2 is conductive and an electric charge of the line Ld is forcibly pulled out. Thereby, fall of the electric potential Vd is accelerated, a time td is shortened, until the electric potential Vd goes <= an input threshold Vth1 of a sense circuit 2, and a rise of a reading output voltage Vout is accelerated and then reading speed is made faster.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is particularly effective when applied to semiconductor memory device technology and also to non-volatile semiconductor memory devices, such as MIS (metal-insulator-semiconductor). MNOS (Metal N1tride) is a type of transistor.
Oxide Sem1conductor: Metal-
EEP using nitride monoxide semiconductor) transistor
- It relates to a technology effective when applied to ROM (electrically erasable and writable non-volatile memory).

[Background technology]

As a non-volatile semiconductor memory device, for example,
As described in Japanese Patent No. 9-22356 and Japanese Patent No. 48-12372, many EEP-ROMs using MNOS (MNOS) transistors as non-volatile storage elements have recently become available. In addition, FIG. 3 (at(bl) shows a part of the EEP-ROM using the MNOS transistor and an example of the operation of that part.

The EEP-ROM, a portion of which is shown in FIG. Word line Tw, data line Ld, precharge (
It includes a MOS transistor M1 for preliminary illumination, a read sense circuit 2, and the like.

Vdd represents a power supply, φp (negative logic) represents a clock pulse for precharge control, and Vout represents a read output voltage.

At the same pressure, each memory cell 1 has one MN
It is composed of an OS transistor Mm and a MOS transistor Mn. MNOS transcriber Mm is “1”
This MNO8I transistor Mm, which holds stored data in a conductive or non-conductive state, connects the data line Ld to the ground potential through a paired MOS transistor Mn. connected between. M
The OS transistor Mn is used as a switching element and is selectively driven into conduction via the word line Lw.

The data line Ld is precharged to a constant potential (Vp) by the MOS transistor Ml, and then is selectively discharged by being connected to the MNO8) transistor Mm. Cs indicates the capacitance of the data line Ld. This capacitance Cs is inevitably parasitic to the data line Ld.

The sense circuit 2 reads out the potential on the data line LdK connected to the transistor Mm (MNO8) in binary form using a predetermined input threshold value Vthl. Assuming that the transistor Mm (MNO8) in MNO8 is in the ON memory state (this is defined as "1"), the data line Ld precharged to a constant potential VpK is turned on (ON). ) is discharged by transistor Mm.

Then, the potential Vd of the data line Ld decreases with time as shown in FIG. The read output voltage Vout appearing on the output side of the sense circuit 2 rises and reaches the logic level of HC high level "1"). In other words, if the storage data of '1' is read out and the MNOS transistor register Mm in the selected storage cell 1 is in the OFF storage state (this is defined as '0'), then Since the data @Ld is not discharged and maintains a high potential, "0" is read out, contrary to the above.

As described above, the data stored in the conductive or non-conductive state of MNO8) transistor Mm in the memory cell 1 is read out as binary logical data of '1' or '0'. There is.

However, in this type of nonvolatile semiconductor memory device,
The inventors have found that the following problems exist.

That is, as shown in Figure 3, K, the above-mentioned EEP-R
In OM, the MNOS transistor M in the selected memory cell 1
m is data! After being connected to Ld, the read output voltage Vou
Until t rises, the trap is the capacitance Cs of the above data @Ld
It is necessary to wait for a time td until the K precharged charges are sufficiently discharged through the MNOS transistor Mm.

However, in general, MNO8 as a nonvolatile memory element
),y-)-r,1MmcDoy (ON)a7a
The conductivity of L"e', so-called β, is compared to a MOS (MOS) transistor as a normal switching element.
Significantly thi5L゛;:0f=6. -f:tDMN
OS) 57-)x fi.

Even if Mm is connected to data@LdK, the data
i line 1"0"'9++-0'flR'kl<*
118#Desk 2 [I can't. As a result, as shown in FIG. 3(b), the drop in the voltage line potential Vd becomes slow, and it takes 1° longer for the readout ratio to start rising. This means that this type of non-volatile
□ A major factor in slowing down the read speed of semiconductor memory devices
[Objective of the Invention] An object of the present invention is to improve the reading speed of a nonvolatile semiconductor memory device by quickly discharging the data line selectively depending on the storage state of the nonvolatile memory element. Our goal is to provide technology that allows you to easily increase speed.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief description of typical inventions disclosed in this application is as follows.

In other words, when the precharged charge on the data line is discharged to a certain extent by the nonvolatile memory element in the conductive storage state, wait for the potential of the data line to naturally fall to the input threshold of the sense circuit. Instead, a discharge circuit is provided to actively draw out the charge from the data line, thereby achieving the purpose of accelerating the fall of the potential of the data line and increasing the read speed.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG.
(a) shows the circuit portion thereof, and (bl) shows an example of the operation of that portion.

The nonvolatile semiconductor memory device shown in the figure is the MNO described above.
S) E using Langinuta Mm as a non-volatile memory element
It is an EP-ROM, and its basic configuration is the same as that described above.

That is, the same figure (EEP-RO showing a part of alK)
M includes a memory cell 1, a word line LW, a data line Ld, a precharge (MOS for preliminary light) transistor M1, a read sense circuit 2, and the like. Vdd is the power supply, φp
(negative logic) is the precharge control clock pulse, Vo
ut indicates the read output voltage, respectively.

In the figure, each memory cell 1 has one MN
It is composed of an OS transistor Mm and a MOS transistor Mn. MNOS) transistor Mm is “1”
Alternatively, bit storage data of "0" is held in correspondence with a conductive or non-conductive state. This MNOS transistor register Mm transmits data #! via a MOS transistor Mn paired with it. Connected between Ld and ground potential. M.O.
The S transistor Mn is used as a switching element and is selectively driven into conduction via the word line Lw.

The data line Ld is precharged to a constant potential (Vp) by a MOS transistor M1, and then selectively discharged by being connected to the MNOS transistor Mm. Cs indicates the capacitance of the data line Ld. This capacitance iCs is inevitably parasitic on the data line Ld.

The sense circuit 2 reads out the potential on the data line Ld connected to the MNOS transistor Mm in binary form using a predetermined input threshold value Vth1. Assuming that the transistor Mm (MNOS) in the transistor Mm is in the ON memory state (this is defined as "1"), the data line Ld precharged to a constant potential Vp is turned ON. MNOS) is discharged by transistor Mm.

Then, as shown in 5 in FIG.
The successive output voltage Vout appearing on the output side of the circuit rises and reaches the logic level of H (high level "1"). In other words, the stored data of "1" is read out. Also, the MNOS transistor Mm in the selected memory cell 1 is turned off (O
FF)′: Memory state of (Let this be 10″.,) If there is K
1□, the data line Ld is not discharged and has a high potential.
- is maintained, so '0' is read out, contrary to the above.

□ In the above manner, the MNOS in memory cell 1)
1 The data stored in the conductive or non-conductive state of transistor Mm is logical data of “1” or “0”.
It is read out as a result. :Here, in the embodiment shown in FIG. 1, in addition to the above-mentioned configuration, the precharge charge of the data line Ld is discharged to a certain extent by the MNOS transistor MmK in the ON storage state. In this case, a discharge circuit 2 is provided which actively extracts the charge from the data line Ld without waiting for the potential Vp of the data line Ld to naturally drop to the input threshold value vthi of the sense circuit 2. It is being

As shown in FIG. 1(a), the discharge circuit 3 includes an n-channel MOS transistor M2 and an N-channel MOS transistor M2 connected in series between a data line Ld and a ground potential.
OS) A transistor M5 and a pair of complementary MOS transistors M3 . It is composed of M4. The potential Vd of the data line Ld is connected to the complementary MOS transistor M3. The common gate of M4, i.e. the inverter input button, is given to its complementary M
O8) Transistor M3. The inverter output appearing at the common drain so-called node of M4 is the n-channel MO
8) The gate of the N-channel MOS transistor M5 is inputted to the gate of the transistor M2 for the precharge control. 7ri2riyuφp2>i people are added. From this K, :The N-channel MOS) transistor M5 is set to keep the ON state at all times except during precharging. Air, J:, E*711) fi7. I) MOS L57
') 'Star M3. As shown in FIG. 1(b), the input threshold Vth2 of the inverter by M4 is between the precharge potential Vp and the input threshold Vthl of the sense circuit 20, more specifically, the precharge potential It is set at a location slightly lower than Vp and certainly lower than the precharge potential Vp.

With the above configuration, the MNOS transistor Mm in the ON storage state is connected to the data line Ld, so that the potential Vp of the data line Ld is increased.
begins to decrease, the data line potential Vd reaches the input threshold Vt of the discharge circuit 3, as shown in FIG. 1(b).
When the voltage drops to h2, the n-channel MO8
) The transistor M2 becomes conductive, and the charge from the data line Ld is forcibly drawn out. This button accelerates the fall of the data line potential Vd, and the time t until the potential Vd becomes less than the input threshold Vthl of the sense circuit 2.
K so that d is significantly shortened. As a result, the read output voltage Vou appearing on the output side of the sense circuit 2
The rise of t is accelerated, and a high read speed can be easily achieved.

FIG. 2 shows the EEP-ROM described above over a rather wide area.

As shown in the figure, the discharge circuit 3 need only be provided for each data line Ld. Therefore, the number of discharge circuits 3 is only the number of data lines Ld, and the readout speed can be increased without complicating the configuration of the peripheral circuits. can be significantly improved. Note that the decoder/driver 4 shown in the figure is for selecting and driving the ite word MLw based on address data and the like.

〔effect〕

(1) When the precharged charge on the data line is discharged to a certain extent by the nonvolatile memory element in the conductive storage state, by providing a discharge circuit that actively drains the charge on the data line, the data line can be discharged. The effect is that the fall of the potential can be accelerated and the read speed can be easily increased.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the discharge circuit 3 may be constructed of a negative resistance element or the like.

[Application field]

The above description has been made of the case where the invention made by the present inventor is applied to the EEP-ROM technology, which is the background field of application, but the invention is not limited to this.
For example, it can be applied to mask ROM or ultraviolet erasable ROM technology.

[Brief explanation of the drawing]

Figure 1 (al, (bl) is a diagram showing the main part of a non-volatile semiconductor memory device to which the present invention is applied. Figure 2 is a slightly wider view of the non-volatile semiconductor memory device partially shown in Figure 1 (al). Figure 3 (al(
bl is a diagram showing a portion of a conventional nonvolatile semiconductor memory device. 1...Memory element, 2...Sense circuit, 3...Discharge circuit, Mm...MNOS as a non-volatile memory element)
Transistor, Ld...data line, Lw...word line, Fig. 1 (a-) 0 ・tan ψ Fig. 2 Fig. 3 (between 0 and

Claims (1)

[Claims] 1. A non-volatile memory element that retains stored data in either a conductive or non-conductive state, and a selectively connected non-volatile memory element that is pre-charged to a constant potential. A non-volatile semiconductor memory device comprising: a data line discharged to a discharge that forcibly discharges the data line when the potential on the data line connected to the storage element drops to a threshold set between the pre-charge potential and the input threshold of the sense circuit; A nonvolatile semiconductor memory device characterized by comprising a circuit. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile memory element is a memory element having an MIS (metal-insulator-semiconductor) transistor structure.