JPS6246364Y2 - - Google Patents

Description

[Detailed description of the invention] The invention is based on an optical system, etc. that is placed between the scanning element and the original when the original is read and scanned by the self-scanning element in a flat scanning type facsimile machine. The present invention relates to a circuit for correcting shading distortion.

Generally, when reading a document using a flat scanning facsimile machine, for example, as shown in Fig. 1,
Irradiating the surface of the original 1 with a light source 3 such as a fluorescent lamp,
The reflected light is imaged by a lens 2 or the like on a self-scanning type document reader 4 made of CdS or the like, and an image signal is obtained by scanning the reader 4 electronically.

In the case of such reading scanning, the original 1 is scanned by the light source 3.
If the reflected illuminance on the surface of is uniform in the scanning line direction, the amount of light incident on the reader 4 will be different from the part corresponding to the periphery of the scanning line to the central part due to the so-called shading distortion of the lens 2. Therefore, the image signal derived from the reader 4 changes in a substantially symmetrical manner as shown in FIG. Note that in FIG. 2, a broken line arrow represents one arbitrary scanning line.

As a method for correcting such shedding distortion, the applicant has already proposed the circuit configuration shown in FIG. 3. First, this circuit will be explained and the problems to be solved by the present invention will be presented.

In FIG. 3, reference numeral 4 denotes the above-mentioned original reader which starts reading scanning by applying a start pulse ST, 5 an image signal amplification circuit which amplifies the output signal of this reader 4, and 6 a reference numeral 6 denotes the above-mentioned pulse ST. and a circuit for obtaining a clock pulse CP for driving the reader 4 and creating a correction signal representing the shading characteristic;
is a differential amplifier circuit into which the correction signal and the image signal from the amplifier circuit 5 are introduced as two inputs.

The correction signal generation circuit 6 starts operation by applying ST to a frequency dividing circuit 8 that divides the CP into an appropriate frequency, and counts the CP by a number corresponding to the number of elements of the reader 4. a counting circuit 9 that stops when the pulse signal is reached; a control pulse generating circuit 10 that obtains the outputs of both circuits 8 and 9 and generates various pulse signals to be described later; and a control pulse generating circuit 10 that sequentially switches the amplification degree for each pulse signal. a pulse amplification circuit 11 that amplifies;
It consists of a low-pass filter 13 that smoothes the output signal of this circuit 11.

That is, in the circuit shown in FIG. 3, as can be seen from the waveform diagram shown in FIG _. Q ₈ is generated, each of these pulse signals is inverted and amplified to a predetermined size in the pulse amplification circuit 11, and serially derived to convert into a staircase wave signal SD, and this signal is passed through the low-pass filter 13. The correction signal SA approximates the shading characteristic shown in Fig. 2 to a parabolic wave shape, and
This signal SA is differentially amplified with the image signal VI from the image signal amplification circuit 5 in the differential amplifier circuit 7, thereby obtaining the image signal VO whose shading distortion has been corrected.

In the operating model shown in FIG. 4, the number of elements in the reader 4 is 1024 and the frequency division ratio of the frequency divider circuit 8 is 64, so the output pulse BP of the frequency divider circuit 8 is
1024÷64=16 are derived in one scanning period 1L, and eight types of pulse signals Q ₁ to Q ₈ are generated from the control pulse generation circuit 10.

By the way, in the circuit shown in FIG. 3, if the low-pass filter 13 is composed of, for example, an integrating capacitor, the correction signal SA will change as shown by the solid line in FIG. 4 due to the delay effect of the filter 13. Therefore, it is not possible to completely correct the shading distortion, which is substantially symmetrical in the left and right sides of the image signal VI.

Therefore, the present invention proposes a shedding distortion correction circuit that eliminates such drawbacks.
The details will be explained below.

FIG. 5 shows a schematic configuration of a shading distortion correction circuit according to the present invention. In this figure, the same parts as those in FIG. 3 are given the same reference numerals, and the explanation will be omitted, and only the characteristic parts will be explained.

That is, in the circuit of FIG. 5, the correction signal generation circuit 6
The frequency dividing circuit 14 within the clock divides the clock pulse CP into two high and low frequencies ₁ and ₂ (for example, ₁ = 2 ₁ ) that are in synchronization with each other, and the pulses BP ₁ and BP ₂ obtained by this frequency division are Gate circuit 15
This gate circuit is connected to the control pulse generation circuit 1.
T flip-flop 1 triggered on output of 0
By switching according to the output of 6, the pulses BP ₁ and BP ₂ are selectively derived as BP ₁ in the first half of the scanning period 1L and BP ₂ in the second half, and each of the derived pulses is used as the pulse It is characterized in that it is introduced into the creation circuit 10.

FIG. 6 shows an embodiment of such a correction signal generating circuit 6. In FIG. That is, the control pulse generation circuit 10
Cascade-connected 4-bit shift registers 16a to 16 each use pulses derived from the gate circuit 15 as input to the first stage, and output from the counting circuit 9 as a reset signal (reset state at "low") to each stage.
d, and OR gates 17a to 17h into which each bit output of this shift register is introduced as shown. In addition, the pulse amplification circuit 11
are resistors R ₁ to _{R 8} (R ₁ >R ₂ >...) inserted in each output path of the OR gates 17a to 17d, respectively.
> R ₈ ), an operational amplifier 18 in which one commonly connected end of each of these resistors is connected to the inverting input side and the non-inverting input side is grounded, and the above-mentioned resistors R ₁ to _{R 8} are combined to form the above-mentioned amplifier. It consists of a feedback resistor Rf that determines the amplification degree of 18. Then, the low pass filter 13 in FIG.
is constructed by connecting a capacitor _C1 in parallel to the feedback resistor Rf.

On the other hand, the gate circuit 15 has one input each of the output pulses BP ₁ and BP ₂ of the frequency dividing circuit 14, and receives the non-inverting output of the flip-flop 16 and the inverter 19.
AND gates 20a, 2 whose outputs are input to each other
0b, and an OR gate 21 having two inputs, each output of this gate. The flip-flop 16 then uses the highest bit output S ₈ of one of the shift registers 16b as a trigger input.
However, the output CO of the counting circuit 9 is also applied as a reset input ("low" and reset state).

Here, as explained in FIG. 4, the correction signal generation circuit shown in FIG.
This is an example of dividing into sections. Therefore, the frequency divider circuit 14 outputs a pulse during the 1L period.
Two frequency division ratios are appropriately selected according to the number of elements of the reader so that a total of 16 BP ₁ and BP ₂ are derived. That is, during the period when the highest bit output _S8 of the shift register 16b is "low", one AND gate 20a of the gate circuit 15 is opened and the higher frequency divided output pulse _BP1 is also output from the above bit. After the output _S8 becomes "high", the other AND gate 20b opens and eight of each of the lower frequency divided output pulses _BP2 are introduced into the first stage shift register 16a. be.

Therefore, the signal waveforms of each part of the circuits of FIGS. 5 and 6 are as shown in FIG. 7, as can be seen from the above explanation. That is, since the staircase wave signal SD derived from the pulse amplification circuit 11 becomes as shown in the figure, when this signal is subjected to the smoothing and delaying effect of the low-pass filter 13 (or capacitor C ₁ ),
The image signal VO is converted into a substantially symmetrical correction signal like SA in the figure, thereby obtaining an image signal VO from which shading distortion has been substantially completely removed.

Although the explanation has been given by taking as an example the case of obtaining a correction signal representing symmetrical shading characteristics, the present invention can also be applied to the case of obtaining a shading correction signal approximated by a curve other than a parabolic curve. That is, in that case, the number of divisions of one scanning period 1L, the type of pulse derived from the frequency dividing circuit 14, and the amplification degree of the pulse amplification circuit 11 for each pulse from the control pulse generation circuit 10 (the circuit shown in FIG. Then, Rf/Ri, determined by i=1, 2, 3, etc.) can be set appropriately.

Furthermore, since the delay effect of the low-pass filter 13 varies greatly depending on the cut-off frequency of this filter, this point should also be taken into consideration when determining the frequency division ratio of the frequency divider circuit 14, that is, the frequency of the divided output pulse. There is a need.

Since the shading distortion correction circuit of the present invention is constructed as described above, it is possible to substantially completely correct shading distortion of an image signal, and it is highly effective when implemented in a facsimile machine.

[Brief explanation of drawings]

Fig. 1 is a diagram schematically showing the original reading mechanism of a flat scanning facsimile, Fig. 2 is a diagram for explaining the shading distortion, Fig. 3 is a diagram showing a conventional shading distortion correction circuit, and Fig. 4 5 is a diagram showing the schematic configuration of the shading distortion correction circuit according to the present invention, FIG. 6 is a circuit diagram of one embodiment of the main part, and FIG. 7 is a diagram showing the signal waveforms of each part. 6 is a signal waveform diagram of each part in FIG. 6. FIG.

Claims (1)

[Claims for Utility Model Registration] In a plane scanning type facsimile device using a self-scanning type original reading means, the clock pulses for driving the reading means are provided with several types of pulses that are in synchronization with each other and have different frequencies. a frequency dividing means for dividing the frequency into signals; a gate means for selectively deriving each pulse signal from the frequency dividing means by switching in the middle of a scanning period of the reading means; and a gate means for selectively deriving each pulse signal from the gate means. a pulse generating means for deriving a pulse corresponding to each small section when the scanning period is divided into a plurality of parts, and a pulse amplification configured to sequentially change the amplification degree for each pulse from the pulse generating means. means for obtaining the output of the pulse amplifying means and creating a correction signal representing the shading characteristics of an optical system or the like disposed in front of the reading means; A shading distortion correction circuit for a facsimile device, comprising means for deriving an image signal whose shading characteristics are corrected by amplification.