JPS6246351A - Method and device for analyzing action of microprocessor - Google Patents

Abstract

PURPOSE:To attain action analysis speedily and exactly by transmitting information to a secondary memory circuit through a gate according to the order of an instruction so as to store, preventing an instruction, which need not be executed, from being stored, transmitting the stored contents to the main body of an emulator and displaying only necessary information according to the order of the instruction. CONSTITUTION:A program reference separating circuit 12 judges the signal of a bus to which a microprocessor 5 to be measured is connected. Here, said signal is the input of a primary memory circuit 15. If said signal is not a program reference, a select gate 16A selects the output of an input circuit 11, and writing and outputting in the primary memory circuit 15 are inhibited. The selected output of an input circuit 11 is impressed and written in a secondary memory circuit 17. Then a continuity detecting circuit 14 judges the program reference. If the program is discontinuous and the instruction during the previous period is not an operational code, it is written in a secondary memory circuit 17. A signal written in the secondary memory circuit 17 is transmitted to the emulator main body part 20 according to the order of the instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method and apparatus for analyzing the operation of a microprocessor. More specifically, it relates to an emulator for debugging microprocessors. In particular, the present invention relates to an emulator used for debugging the hardware and software of a microprocessor that performs a brief fetch operation.

[Prior Art] Emulators are used to debug the hardware and software of microprocessors in devices including microprocessors.

This emulator has an address bus connected to the microprocessor under test to be debugged.

Signals from a data bus and a control bus (hereinafter referred to as bus) are stored in a storage device in the main body of the emulator, and the stored contents are displayed for operation analysis.

This bus carries signals that allow the microprocessor under test to read and write data and programs from the memory attached to the microprocessor under test.
According to the order in which the signals are transmitted, the signals are sequentially fetched into the emulator and analyzed.

However, if the microprocessor under test performs a brief fetch operation,

. Engineering. Oh, yeah. . The read cycle □ of the next instruction is inserted between the memory read or write □ cycle caused by o1 □ and :.
: In cases where the addresses read by the rough instruction are not consecutive.
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□1: Because it also reads instructions without .
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(7)*(485t: - month, 1 was lost.

Here, a briftetch operation is an operation in which a microprocessor performs a series of operations, such as an operation in which a microprocessor reads or occupies the memory generated by reading an instruction and then executing that instruction one line. Instead, while executing this command, 1.
It is referred to as 01 which performs 8 parallel 1 operations for reading 9gi0 instructions.

Therefore, the briefetch operation increases processing speed. In particular, 16-bit microprocessors cannot perform briefetch operations.
1. There are many things you can do.

[Problems to be Solved by the Invention] A bus connected to a microprocessor that performs such a briefetch operation has a problem in that the next instruction is not transmitted between reading an instruction and reading or writing the memory resulting from the execution of that instruction. In conventional emulators, which display the bus status in the order in which they are transmitted on the bus, the correlation between the read of an instruction and the subsequent memory access or write caused by the execution of that instruction is not known. It was difficult to understand.

Also, if the addresses read by the instruction are not consecutive,
Instructions that do not need to be executed are also read for the brief fetch operation, and this is also sent to the emulator main unit on the bus, so the emulator main unit collects unnecessary data and displays it. In order to
Furthermore, it made operation analysis difficult.

[Means for Solving the Problems] The present invention has been made to solve these problems. □By switching the order, the reading of the next instruction that occurs between the reading or writing of the memory that has been read or written is performed so that the reading of the next instruction occurs next to the reading or writing of the memory that occurred due to the reading of the instruction and its execution. I made it.

Also, even if the addresses read by the instruction are not consecutive,
- In this case, reading instructions that do not need to be executed are not sent to the main body of the emulator. To change this order, the data on the bus is applied to the primary storage circuit, a gate is provided to which the data on the bus and the output of the primary storage circuit are applied, and the output of this gate is sent to the secondary storage circuit. I made it so that it was memorized.

[Function] Information is sent and stored in the secondary storage circuit according to the order of instructions by this gate, instructions that do not need to be executed are not stored, and the contents of this storage are sent to the main body of the emulator. Only the necessary information is displayed in the order of the instructions, allowing for quick and accurate operation analysis.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention, and will be explained using this diagram.

In FIG. 1, 5 is a microprocessor to be measured which is included in the system under test, and 6 is a device for reading and writing instructions to be executed and data generated as a result of execution by access of the microprocessor to be measured 5. memory.

Reference numeral 11 denotes access signals and data signals (
Below is the contents of the bus. ), 12 indicates that when the microprocessor under test 5 reads out the memory 6, the instruction being read is the program reference (this is called a program reference). a program reference separation circuit for outputting a program reference signal QP by distinguishing whether data generated as a result of execution is being read from the memory 6 or written to the memory 6 (this is called a data reference); Reference numeral 13 indicates an operation code detection circuit that detects an instruction executed by the microprocessor 5, for example, the first word (operation code) of an instruction consisting of three words, and outputs whether or not it has been detected. Reference numeral 14 indicates the microprocessor 5 under test.
When reading an instruction from the memory 6 (program reference), as soon as the program reference signal P is received, the address in the memory 6 containing the instruction is continuous with the address containing the previously read instruction. A continuity detection circuit 15 detects whether or not the operation code and operand (instruction 2nd word onwards) Primary storage circuit for storing □, 16A is program/reference separation circuit 1
The contents of the bus output from the input circuit 11 are stored in the primary storage circuit 15 by the program reference signal P from the input circuit 11.
Input circuit 1
Select 1 to select whether to output directly from 1 gate,
17 is a secondary storage circuit for storing the output of the select gate 16A other than instructions that are not executed; 18;
receives the program reference signal P, the output of the operation code detection circuit 13, and the output of the continuous detection circuit 14, and stores the output of the select gate 16A in the secondary storage circuit 17.
19 is a secondary storage control circuit for sending a control signal for storing things other than instructions that are not executed;
15.16A and 17.18, which characterizes the motion analysis device according to the present invention. 20 monitors by displaying the contents of the bus sent from the secondary storage circuit 17 of the emulator unit 19 in order to trace the operating state of the microprocessor 5 under test, and is built in instead of the memory 6. The main body of the emulator has a display section for reading from or writing to the memory and correcting bugs in the contents of the memory 6 (reference materials: e.g. Iwatsu Giho, Perrnall Emulator 5L)
-4802, Publisher: Miyazaki Tsushin: Engineering a8□,
E□□. 59*6J130B1,. :: No. 1.23, pp. 1.11 to 19), and together with the emulator unit section 19 constitute a motion analysis device.

Here, an example of the internal configuration of the memory 6 is shown in FIG. For example, each instruction:
If it consists of 3 words, the first word is turned on.
The 1st becode, 2nd and 3rd words are operands. Many types of commands (...
・M-1, M.

The operation codes and operands (M+1, . . . ) are stored at successive addresses in the memory 6 in the order shown.

FIG. 2 shows an example where the microprocessor 5 under test performs a prefetch operation and the instructions are consecutive. When a read instruction is read from the memory 6 and executed, the bus connected to the microprocessor 5 is It shows how the contents are sent from the emulator unit section 19 to the emulator main body section 20.

The input to the primary storage circuit 5 in FIG. 1, the first word (opcode) of instruction 1, and the instruction 1 shown in period T3.
between the second word (operand) of "instruction 1 operand" and "operand of instruction 1", which is the data read from memory 6 that was generated due to the execution of the instruction read earlier than instruction 1, due to the prefetch operation. A memory read '' is inserted in period T2.Furthermore, in period T5, the 'memory read by instruction 1' that occurs due to the execution of instruction 1 is inserted into the bus connected to the microprocessor 5 under test. Before the hail, period T
In period T6, the read state of the opcode of instruction 2 to be executed next to instruction 1 is read. In period T6, the operand of instruction 2 is read.

Hail!

The input of the primary storage circuit 15 shown in FIG. 2(a) is
If the instructions are sent to the emulator main unit 20 and displayed in the same order, it would be difficult to analyze the operations because they are not in the order of the instructions due to the prefetch operation.

Here, FIG. 2 shows how the contents of the bus connected to the microprocessor under test 5 are sent to the emulator main unit 20 by changing the order shown in FIG. (b) to (CI>).

During period T1, the bus connected to the microprocessor under test 5 receives the "opcode of instruction 1".

The operation code of instruction 1 is read out from the primary storage circuit 15 through the input circuit 11.
The select gate 16A1 is sent to the program/reference separation circuit 12, the opcode detection circuit 13, and the continuity detection circuit 14.

The program/reference separation circuit 12 detects the operation end or outputs the reference signal "'P" (Fig. 2(b)) or reads the memory by an instruction. When it is detected and determined to be a data reference, the program reference signal ``P'' is not output (shown as D tt in Fig. 2(b)), but during period T1, the operation code of instruction 1 is read. Therefore, it is in the program reference state and outputs the program reference signal "Poo". As a result, the opcode of instruction 1 is written into the primary storage circuit 15 in place of the operand par of the previous instruction, which has already been written and is the content of the primary storage circuit.

When the operation code detection circuit 13 detects an operation code, its output becomes "H" (level), and when it does not detect an operation code, its output becomes "L" (level) (FIG. 2(d)). During period T1, the operation code detection circuit 13
The output of is "F1".

The continuity detection circuit 14 is a circuit that checks the continuity of the addresses containing the instructions.If the addresses in the memory 6 containing the instructions (see FIG. 5) are continuous in the presence of the program reference signal P, it is determined as "continuous". When the signal is discontinuous, “Non-delivery i)・1” (7) (fi@
. Ka. , car 3. Huh, crab r**! Output when reading data generated as a result of executing step 1 from memory 6 (reading or writing to memory 6)
i;□i] No. Therefore, in period T1, period T1
□11.1 In the period before 1, the operand of the instruction before instruction 1
1・Because there is □ii′ (not shown)・Operation of instruction 1
・It is continuous with the j-becode (see FIG. 5), and the output of the detection circuit 14 is "continuous".
j When the program reference signal ``P'' is output, the select gate 16A switches to the primary storage circuit.
Select the output of the leak 15 and send it to the secondary storage circuit 17, 11a. 5 Yu! J'7. L/) 2 pieces 8
44 P N jfi kaka. 11 □□, yo, t, tsu8. Goo 1. ．． 16 Eh, yo, island. 1'i・
1 Select the output of path 11 and send it to secondary storage circuit 17
;:, i;□. During period T1, program revision
:・(Since there is a sense signal “P”, select
□'j to 16A is the primary memory circuit 15 (7
) Select the output and , :32nd memory circuit 1
I am sending it to 7. ('1゜In the period T1, the input of the secondary storage circuit 17 is 1
The "previous instruction operand" of instruction 1, which is the content of the next storage circuit 15, is input (FIG. 2(f)).

In the output of the secondary storage circuit 17, the "opcode of the previous instruction" of the instruction 1 exists in the period T1 (see FIG. 2).
q)).

Similarly, during period T2, the data reference (D>
2(b)>, the contents of the primary storage circuit 15 are "operand pars of instruction 1 (C), and the contents of the primary storage circuit 15 are
5 is not filled in, the output of the opcode detection circuit 13 is L tp (d), and since it is not a program reference, there is no output of the continuity detection circuit 14 (e).
, the select gate 16A selects the output of the input circuit 11, so that the "memory read according to the previous instruction" is input to the secondary storage circuit 17 (f), and from the secondary storage circuit 17, the "previous instruction The operands of are output (g).

In the period T3, the program/reference separation circuit 12 also performs the program/reference separation circuit 12 in the same manner.
)...,; The reference signal ゛P'' is output and the primary memory
1. 1. In step 15, there is a data reference in period T2.
□, ・No new writing is performed because the .
;, ] are stored, and the output of the opcode detection circuit 13 is
;,1 The power is "L", and the output of the continuous detection circuit 14 is
, :・"Continuous", select gate 16A
1 1.1 The secondary memory circuit is used to select the output of the number memory circuit 15.
□゛''I::・ The input of path 17 is the content of primary memory circuit 15
, ("Operation code of instruction 1" is applied, secondary memory circuit ・□,) From path 17, "Memory read by previous instruction":;
] is output.
・70g degree rift in 'mT? The program and
Reference −)・i: The signal “p pt” is output, and the contents of the primary storage circuit 15 are
, :"j is the operand of instruction 1, and the opcode check
,i.

The output of the output circuit 13 is "H", and the continuous detection circuit
The output of 1・1 14 is “Pa continuous” and goes to Select Go 1.
・j16A selects the output of the primary storage circuit 15, so the input of the secondary storage circuit 17 is connected to the primary storage circuit 15.
The "operand of instruction 1" which is the content of is applied, and the "operand of instruction 1" is output from the secondary storage circuit 17.

In period T5, the program/reference separation circuit 12 detects the data reference (D>
The contents of the next storage circuit 15 are "Operation code of instruction 2" is stored, and the output of the operation code detection circuit 13 is "L".
11 and is not a program reference, there is no output from the continuous detection circuit 14, and the select gate 1
6A selects the output of the input circuit 11 and outputs "memory read by instruction 1", this "memory read by instruction 1" is applied to the input of the secondary storage circuit 17, and 2
The next storage circuit 17 outputs "operand of instruction 1".

During the period T6, the program reference separation circuit 12 outputs the program reference signal "P", and the primary storage circuit 15 receives the data during the period ET5.
Because it was a reference, no writing was done, and 1i 6 ” N'?'2 (
7):t<ml) "7')'Ha'a6
'n-Tao・Ill・Opcode detection circuit 1
The output of No. 3 is "L", and the output of No. 11 continuous detection circuit 14 is "continuous".
The output gate 16A receives the output of the primary storage circuit 15.
1::: Since it is selected, the input of the secondary memory circuit 17 is the primary one.
1:1::1 The contents of the memory circuit 15 “Operation code tp of instruction 2”
, 1° are applied, and the secondary storage circuit 17 outputs "memory read according to instruction 1: 1:(:11").
, :: As is clear from the above operations, Fig. 2 (
a) 11': If we compare 11 and (g), the prefetch operation
':1:1 Therefore, in period T1 of (a), "operation of instruction 1"
,.

Code °′ indicates “memory read by previous instruction”
, 11::: The previous entry is in period T4 in Figure 2 (Q).
::.

′:1 “Memory read by previous instruction”
The :: order is changed and output from the secondary storage circuit 17. □'1 The signals :, : are sent to the emulator main unit 20 in the order of the commands.

Similarly, in period T4 in FIG. 2(a), 'instruction 1
The opcode of instruction 2 that appears before the memory read is input to the secondary storage circuit 17 during rIfJ period T6 of (G), and is input to the secondary storage circuit 17 during period T7 (not shown) of (Q>). The signal is output from the circuit 17, and the signal is sent to the emulator body 20 in the order of the instructions.

(2) The display on the simulator body 20 is continuous from the reading of the instruction to its execution, making it easy to analyze the operation.

Next, FIG. 3(a) shows BRΔ (abbreviation of 13ranch AlwaVS, one of the di-thump-type operations of a microprocessor) among the 1-word jump-type instructions. B.I.
T MICROPROCESSOR, Proqram
mers ReferenCe Manual
Page 77, 4th edition, 1984, published by Motorola) is executed, and shows an example of the contents of the bus connected to the microprocessor 5 under test. In the main body 2o
Figures 3 (b) to (l) show how it is moved by 1°.
, 1. ::1: In Figure 3, a jump command is a specified
1::': Mail 1 6' 7) Address ``Fly ξ Pa instruction 1'' 71.
．． .

The jump destination instruction is the memory 6 specified by the jump instruction.
:' Refers to the instruction stored at address.
l111・.

As shown in Figure 3(a), the microbe under test
1□′. Yay4j5 (Diyo,, □7, Yu., Yuka,
1. It is input to the primary storage circuit 15 via □111, and during period T1, the operation code of ``jump instruction 1'' is
:::v"h<'IQfJT cgpz-co
"'nN')*@GLc"6% i,.

There is Mori Leadpa. In period T3, actually
: Opcode of instruction 2 that is not executed”, i.e.
11: Aaaaaaaaaaaaaaaaaaaaaaaa1□1o
oka, tsu□ -・□IJ 6G, : oil r, t)7
f@:1 (7) uImt:y@b, tLTIl116
7.3, a, wa, tsu □work, work, ga 9. . l 汀j
': i.: Applied to the input of path 15. During period T4,
“Jump destination instruction 3 opcode °’ is applied
1.1.1, and in period T5, the operand of the jump destination instruction 3, "operand of instruction 3", is applied,
During period T6, the "opcode of instruction 4" is applied.

During the period T1, the program reference separation circuit 12 outputs the program reference signal "P" as shown in FIG. 3(b), as in the case of FIG. Output. As a result, the operation code of jump instruction 1 is written into the primary storage circuit 15 as shown in (C) instead of the previously written operand of the previous instruction. When the operation code is detected, it outputs "H" as shown in (d). (a) “
The operation code '' of jump instruction 1 is the "operand of the previous instruction" ((C
)) and the addresses stored in the memory 6 are consecutive, so the continuity detection circuit 14 outputs a "continuous" signal as shown in (e). When the program reference signal “P” is output, select
Since the gate 16A selects the output of the primary storage circuit 15, the input of the secondary storage circuit 17 is 1 as shown in (f).
“Operand of the previous instruction” which is the contents of the next storage circuit 15
is applied and stored as shown in l) for a period T2.
It is output in .

In period T2, the program/reference separation circuit 12 detects the data reference (D), the content of the primary storage circuit 15 is "the operation code of jump instruction 1", and the output of the operation code detection circuit 13 is " Since the data reference is detected,
There is no output from the continuous detection circuit 14, and the select gate 16
In order to select the output of the input circuit 11, A outputs "memory read according to the previous instruction", which is input to the secondary storage circuit 17, and from the secondary storage circuit 17, the "memory read according to the previous instruction" is output. "operand" is output.

During the period T3, the program reference separation circuit 12 outputs the program reference signal "P". The contents of the primary storage circuit 15 are stored in the period T2 because the data reference is detected in the period T2.
The operation code of jump instruction 1 remains the same.

The output of the operation code detection circuit 13 is "H09".

Since the jump instruction 1 and the unexecuted instruction 2 are stored in consecutive addresses in the memory 6, the output of the continuity detection circuit 14 is ``'Continuous'''', and since P'' has been detected, the select Gate 16A is primary storage circuit 15
Select the output of The input of the secondary storage circuit 17 is applied with the contents of the primary storage circuit 15, ie, the opcode of jump instruction 1, and the secondary storage circuit 17 outputs ``memory read by previous instruction''.

During period T4, the program reference signal “P” is output from the program reference separation circuit 12. The operation code of instruction 2 which is not executed is stored in the primary storage circuit 15, and the operation code detection circuit 13 The output is “H99. Since the address of the jump destination instruction 3 stored in the memory 6 is not continuous with the address of the unexecuted instruction 2, the continuity detection circuit 14 outputs "discontinuous". Since the output of the program/reference separation circuit 12 is “P”,
The select gate 16A is the primary memory time '1815 (D
Bd7) F'S Revised biography 2' ``Ryu 17ha 1to 1j
The “operation code of instruction 2 that is not executed”, which is the content of the primary memory circuit 15, is applied to the input voltage, and the output of the secondary memory circuit 1 is
7 outputs the "operation code of jump instruction 1". The secondary storage control circuit 18 to which “discontinuous” was applied is configured to receive the previous instruction (instruction applied during period T3, i.e., “
Instructions that are not executed.

2 operation code"), and if it is an operation code, the write signal to the secondary storage circuit 17 is not output, and the 2 operation code is checked.
The next memory circuit 17 stores the applied instruction 2 which is not executed.
"opcode" cannot be memorized. "Discontinuous"
Even so, if the previous command (command applied during period T3) is not an opcode or is continuous, the secondary storage control circuit operates and causes the secondary storage circuit to store the input.

During the period T5, the program reference separation circuit 12 outputs the program reference signal "P". The primary storage circuit 15 stores “the operation code of the jump destination instruction 3”, and the operation code detection circuit 1
The output of 3 is "L''. Since the operand of instruction 3 and the operation code of jump destination instruction 3 are consecutive in the memory 6 (see FIG. 5), the continuity detection circuit 1
4 outputs "continuous". Since P is output, the select gate 16A selects the output of the primary storage circuit 15, and the input of the secondary storage circuit 17 receives the contents of the primary storage circuit 15. "Operation code of jump destination instruction 3" is applied. Here, since the period T4 is "discontinuous" and the previous instruction (period T3) was an opcode, the secondary storage control circuit 18 does not operate, and the memory contents of the secondary storage circuit 17 are not rewritten. Therefore, the secondary storage circuit 17 continues to output the "operation code of jump instruction 1" during period T4. Due to this operation, the "opcode of instruction 2 that is not executed" is secondary.11. . 6
１□, )□ka,, yoga, gai. 1. .

1,, Period T6 “°o°゛1′”・pu0g°°Nofurun
:: Program reference □ 85"p"i;+b=""'・111"154mG" from the space separation circuit 12
: "Operand of instruction 3" is stored. The output of the operation code detection circuit 13 is "H". Command 4°“
*f; 3 (!:3i@L'T'i' 6 b"
)M@@ff1O”let 14:.

The output of is “continuous”. select gate 16
'A <* 1 &E? ! ! I'm 15 (Dm
f) @”1nlt 6(7)1', 21st storage circuit 17
The contents of the primary storage circuit 15 are applied to the input of the secondary storage circuit 17, and the secondary storage circuit 17 outputs the "operation code of jump destination instruction 3".

In this way, the "opcode of unexecuted instruction 2" generated by the BRA operation in the brief fetch operation on the bus connected to the microprocessor under test 5 is not outputted from the secondary storage circuit 17, but is stored in the emulator main body 20. Since it is not sent, operation analysis becomes easier.

The operations shown in FIGS. 2 and 3 will now be explained with reference to the flowchart in FIG. 4.

The program reference separation circuit 12 determines whether the signal on the bus connected to the microprocessor under test 5, which is an input to the primary storage circuit 15, is a program reference that is an opcode or an operand of an instruction (S
TEP81>.

If it is determined that it is a program reference (ST
EP81Y), the program reference signal P is output from the program reference separation circuit 12, the output of the primary storage circuit 15 is selected and sent to the secondary storage circuit 17, and the output of the input circuit 11 is output from the primary storage circuit 15. (STEP 82).

If it is not a program reference (STEP 8)
1N>, the select gate 16A selects the output of the input circuit 11, and writing and output of the primary storage circuit 15 are prohibited (STEP 83).

The output of this selected input circuit 11 is the secondary storage circuit 17
is applied and written (STEP 87).

Next, the continuity detection circuit 14 determines whether the program references are continuous (5TEP84), and if they are continuous (S
TEP84Y), write to the secondary storage circuit 17 (STE
P87). If it is discontinuous (STEP 84N>, determine whether the instruction in the previous period is an opcode or not 5TEP 85),
If it is an opcode (STEP 85Y), it is not written to the secondary storage circuit 17 (STEP 86). If it is not an opcode (STEP 85N>, it is written to the secondary storage circuit 17 (
STEP 87).

The signals written in the secondary storage circuit 17 are sent to the emulator main unit 20 in the order of the instructions (STEP 8B>
.

The contents of the next bus are then analyzed and the operations described above are repeated.

[Effects of the Invention] As is clear from the above explanation, the prefetch operation eliminates unnecessary instructions even if the order of signals on the bus is not in the order of instructions or even if instructions that do not need to be executed are included. The system sends signals from the emulator unit to the emulator main unit and displays them in the order specified by the commands. This eliminates the possibility of starting incorrect processing work due to unnecessary commands, making operation analysis easier. The effects of the present invention are extremely large, since the hardware and software of the microprocessor can be quickly debugged.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the device of the present invention, FIGS. 2 and 3 are explanatory diagrams of the operation of the device shown in FIG. 1, and FIG. 4 shows the procedure for processing signals in the device. The flowchart shown in FIG. 5 is a diagram showing the internal configuration of the memory 6. 5... Microprocessor under test 6... Memory 11... Input circuit 12.
・Program/reference separation circuit 13 ・Operation code detection circuit 14 ・Continuity detection circuit 15 ・Primary storage circuit 1
6A...Select gate 17...Secondary memory circuit 18...Secondary memory control circuit 19...Emulator unit section 20...Emulator main body.

Claims (2)

[Claims] (1) Among bus signals that are access signals and data signals that access the memory to be accessed by the microprocessor under test from the bus connected to the microprocessor under test, the operation code and operand in which instructions are written are When one of the opcode and operand is detected by the program reference for detecting either one, the detected opcode and operand are already stored in the primary storage circuit for storing one of the detected opcode and operand. gated so as to selectively apply the stored contents related to the previous instruction to the secondary storage circuit, and when neither the opcode nor the operand is detected, the bus signal is not stored in the primary storage circuit. gated to selectively transmit to the secondary storage circuit;
A case other than the case where the address in the memory where the instruction is written is discontinuous with the address in the memory where the instruction before the instruction is written and the opcode of the instruction before the instruction is detected. The storage contents of the primary storage circuit selectively applied to the secondary storage circuit and the bus signal selectively gated and transmitted are stored in the secondary storage circuit; A method for analyzing the operation of a microprocessor, characterized in that the contents stored in a next storage circuit are sent out in the order in which they were stored. (2) To extract, from the bus connected to the microprocessor under test, a bus signal containing an operation code, an operand, and a data signal in which an instruction for accessing the memory to be accessed by the microprocessor under test is written. input means; program reference separation means for outputting a program reference signal when either the opcode or the operand is detected, and not outputting the program reference signal when not detected; and the program reference signal. a primary storage means for storing the output of the input means when the program reference signal is received; and a primary storage means for storing the output of the input means when the program reference signal is received; gating means for selectively gating the output of the input means; opcode detection means for detecting the opcode; and an address in the memory at which the instruction is written is an instruction preceding the instruction. continuity detection means for detecting whether the written address in the memory is continuous or discontinuous and outputting a continuous signal and a discontinuous signal; and a continuity detection means to which the output of the gate means is applied and controlled by a control signal. secondary storage means for storing and outputting the program reference signal, the signal from the operation code detection means, and the discontinuous signal, and when the instruction before the instruction is an operation code; an emulator unit section including a secondary storage control means for sending the control signal to be stored in the secondary storage section in other cases; and the secondary storage section included in the emulator unit section. 1. A microprocessor operation analysis device, comprising: an emulator main body for receiving and displaying the output of the emulator.