JPS6244366A - Grinding method for semiconductor wafer - Google Patents

Grinding method for semiconductor wafer

Info

Publication number
JPS6244366A
JPS6244366A JP18052185A JP18052185A JPS6244366A JP S6244366 A JPS6244366 A JP S6244366A JP 18052185 A JP18052185 A JP 18052185A JP 18052185 A JP18052185 A JP 18052185A JP S6244366 A JPS6244366 A JP S6244366A
Authority
JP
Japan
Prior art keywords
grinding
wafer
envelope
ground
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18052185A
Other languages
Japanese (ja)
Inventor
Kenji Yamane
健次 山根
Kazunari Sakamura
坂村 一成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NOUKATA TOSHIBA ELECTRON KK
Toshiba Corp
Original Assignee
NOUKATA TOSHIBA ELECTRON KK
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NOUKATA TOSHIBA ELECTRON KK, Toshiba Corp filed Critical NOUKATA TOSHIBA ELECTRON KK
Priority to JP18052185A priority Critical patent/JPS6244366A/en
Publication of JPS6244366A publication Critical patent/JPS6244366A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01039Yttrium [Y]

Abstract

PURPOSE:To make such an element as being small in contact resistance with an envelope formable so easily in a lapping process at the time of setting a brazing material, by installing grinding grooves of more than two directions on a grinding surface when grinding a semiconductor wafer with a grinding wheel. CONSTITUTION:A semiconductor wafer 2 of about 600mum in film thickness is clamped to a fixed block 1, rotating a grinding wheel 3a in an X direction, and this fixed block 1 is moved in a Y direction, whereby the wafer 2 is ground so as to be formed into about 300mum in film thickness. Likewise, it is ground so as to become about 200mum in the film thickness by a grinding wheel 3b, and a one directional grinding groove of several mum in depth is formed. Next, a position of the wafer 2 is rotatively moved as far as 90 deg., and its surface is lightly ground by a grinding wheel 3c, whereby a reticulate grinding groove is formed on a surface of the wafer 2. In succession, the wafer 2 on which the reticulate grinding groove is formed is divided into plural elements, and each grinding surface of these elements is stuck and locked to an envelope 5 via a brazing material. Thus, the wafer surface is reticulated at a lapping process whereby it contact resistance with the envelope 5 is reducible.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体ウェハの表面研削、特にグラインダラッ
ピング方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to surface grinding of semiconductor wafers, and in particular to a grinder lapping method.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来のグラインダラッピングの一例を図を用いて説明す
る。
An example of conventional grinder wrapping will be explained using a diagram.

一般に、シリコン単結晶をスライス(輸切り)して得ら
れたシリコンウェハは600μm程度の膜厚を有してい
る。このウェハを砥石により研削し200μm程度にす
るのがグラインダラッピング工程である。
Generally, a silicon wafer obtained by slicing a silicon single crystal has a film thickness of about 600 μm. In the grinder lapping process, this wafer is ground with a grindstone to a thickness of about 200 μm.

従来は第3図に示すようにシリコンウェハ2上で砥石3
を一方向に回転させることにより研削していた。
Conventionally, as shown in FIG.
Grinding was done by rotating the machine in one direction.

そしてこの研削されたウェハ2は複数の素子に分割され
、各素子は半導体装置の外囲器に固着用ロウ材で固定さ
れる。
The ground wafer 2 is then divided into a plurality of elements, and each element is fixed to the envelope of the semiconductor device with a fixing brazing material.

従来、上記のようにウェハ2の研削を砥石3の一方向の
回転のみにより行なっているため、このウェハ2の研削
面は第3図(b)に示すような一方向の研削溝が形成さ
れる。
Conventionally, as described above, the wafer 2 has been ground by rotating the grindstone 3 in only one direction, so that the grinding surface of the wafer 2 has grinding grooves oriented in one direction as shown in FIG. 3(b). Ru.

そして、このような一方向の研削溝の形成された素子を
外囲器にろう材で固着すると、外囲器との接触面積が小
さいため、この固着部での接触抵抗が太くなる。
When an element having such unidirectional grinding grooves is fixed to an envelope with a brazing filler metal, the contact area with the envelope is small, so the contact resistance at this fixed portion becomes large.

ところでPNアイソレーションによる集積回路では半導
体基板を通じての、寄生PNPなどによる漏れ電流が完
全には防止できない。このため上記のように素子と外囲
器との接触抵抗が大きい場合、漏れ電流により電圧降下
が大きくなる。そして、漏れ電流の生じた部分における
素子内部電位が不必要に高くなり近くの態動領域へ不所
望なバイアスを与え誤動作させる。
However, in integrated circuits using PN isolation, leakage current due to parasitic PNPs through the semiconductor substrate cannot be completely prevented. Therefore, when the contact resistance between the element and the envelope is large as described above, the voltage drop increases due to leakage current. Then, the internal potential of the device at the portion where the leakage current occurs becomes unnecessarily high, giving an undesirable bias to the nearby active region and causing it to malfunction.

また、上記素子への電気信号、例えばコレクタ電流を上
記外囲器の固着部から入出力する場合、ここで接触抵抗
が大きいと消費電力が大きくなってしまう。
Furthermore, when an electrical signal, such as a collector current, to the element is inputted or outputted from the fixed portion of the envelope, if the contact resistance is large here, the power consumption becomes large.

このような問題を解決する方法として、例えばウェハ2
の研削終了後、ダイヤモンドカッタなど研削面に複数の
引っかき傷を形成することも考えられるが、この場合工
程数が増えて生産効率が悪くなる。
As a method to solve such problems, for example, wafer 2
After the grinding is completed, it is possible to form multiple scratches on the grinding surface using a diamond cutter, but in this case, the number of steps increases and production efficiency deteriorates.

〔発明の目的〕[Purpose of the invention]

本発明は上記従来の問題点を解決し、半導体素子の外囲
器へのろう材による固着に際し、この外囲器との接触抵
抗が小さい素子をラッピング工程で簡単に形成すること
ができる半導体ウェハの研削方法を提供することを目的
とする。
The present invention solves the above-mentioned conventional problems, and provides a semiconductor wafer that can easily form elements with low contact resistance with the envelope in a lapping process when a semiconductor element is fixed to the envelope using a brazing material. The purpose of this invention is to provide a grinding method.

〔発明の概要〕[Summary of the invention]

本発明は上記目的を達成するための、研削砥石を用いて
半導体ウェハを研削するにあたりこの研削面に少なくと
も2方間以上の研削溝を形成することを特徴とする半導
体ウェハの研削方法である。
To achieve the above object, the present invention provides a method for grinding a semiconductor wafer, which comprises forming grinding grooves in at least two directions on the grinding surface of the semiconductor wafer when the semiconductor wafer is ground using a grinding wheel.

〔発明の実施例〕[Embodiments of the invention]

本発明方法を用いて半導体ウェハの裏面(外囲器との接
合面)を研削する一実施例を図を用いて説明する。
An example of grinding the back surface (joint surface with the envelope) of a semiconductor wafer using the method of the present invention will be described with reference to the drawings.

第1工程 第1図(a)に示されるように、固定台1に
膜厚的600μmの半導体ウェハ2を固定し、第1の砥
石3aを矢印×で示される方向に回転させる。そして固
定台1を矢印Yで示される方向へ移動させウェハ2を第
1の砥石3aにより膜厚的300μmになるよう研削す
る。(荒研削工程)第2工程 第1図(b)に示される
ように、荒研削工程により膜厚的300μmとなったウ
ェハ2をさらに第2の砥石3bにより、膜厚的200μ
mとなるよう研削する。この工程によりウェハ2には深
き数μmの一方向の研削溝が形成される。(中仕上工程
) 第3工程 第1図(c)K示されるように、ウェハ2の
位置を90°回転移動し第3砥石3cにより表面を軽ろ
く削る。これによりウェハ2の表面には第1図(d)に
示すように網目状の研削溝が形成される。
First Step As shown in FIG. 1(a), a semiconductor wafer 2 having a film thickness of 600 μm is fixed on a fixing table 1, and a first grindstone 3a is rotated in the direction indicated by an arrow x. Then, the fixed table 1 is moved in the direction indicated by the arrow Y, and the wafer 2 is ground by the first grindstone 3a to a film thickness of 300 μm. (Rough grinding process) Second process As shown in FIG. 1(b), the wafer 2 whose film thickness has become 300 μm due to the rough grinding process is further polished to a film thickness of 200 μm by the second grinding wheel 3b.
Grind it so that it becomes m. Through this step, a unidirectional grinding groove with a depth of several μm is formed on the wafer 2. (Intermediate finishing process) Third process As shown in FIG. 1(c)K, the position of the wafer 2 is rotated by 90 degrees and the surface is lightly ground with the third grindstone 3c. As a result, mesh-like grinding grooves are formed on the surface of the wafer 2 as shown in FIG. 1(d).

(最終仕上げ工程) 上記のようにして、網目状の研削溝の形成されたウェハ
2は複数の素子に分割され、個々の素子は第2図に示す
ように前述した研削面を、ろう材4を介して外囲器5V
こ接着・固定される。そしてこの素子2bの上面のt極
はポンディングワイヤ5への接着面をグラインダラッピ
ング工程で網目状にすることにより外囲器5との接触抵
抗を小さくすることができる。
(Final finishing process) As described above, the wafer 2 on which the mesh-like grinding grooves have been formed is divided into a plurality of elements, and each element has its ground surface polished by the brazing material 4 as shown in FIG. Envelope 5V through
This will be glued and fixed. The contact resistance of the t-pole on the upper surface of the element 2b with the envelope 5 can be reduced by making the adhesive surface to the bonding wire 5 mesh-like in a grinder wrapping process.

そしてこのようにゲラインダニ程で網目状の研削溝の形
成されたウェハ2は一方向の研削溝の形成されたウェハ
よりも表面積が大きくなる。このためこのウェハ2を分
割して形成される素子2bはろう材4との接合面積が大
きくなり、外囲器5との接触抵抗が低減する。
The wafer 2 in which the mesh-like grinding grooves are formed in this way has a larger surface area than the wafer in which the grinding grooves are formed in one direction. Therefore, the element 2b formed by dividing the wafer 2 has a larger bonding area with the brazing material 4, and the contact resistance with the envelope 5 is reduced.

従って、漏れ電流による不所望な高電位は低減され、誤
動作が防止される。そし7て消費電力も低減される。
Therefore, undesired high potential due to leakage current is reduced and malfunctions are prevented. 7) Power consumption is also reduced.

また、従来はろう材4として導電性の良いSn −pb
などの半田を用いていたが、多少半田より導電性は小さ
いが、安価な銀含有樹脂基等の接着剤を用いることが可
能となる。
Conventionally, Sn-pb, which has good conductivity, has been used as the brazing material 4.
Although the conductivity is somewhat lower than that of solder, it becomes possible to use an inexpensive adhesive such as a silver-containing resin base.

加えてろう材4との接触面積が太きいため外囲器5の接
着強度が向上する。
In addition, since the contact area with the brazing filler metal 4 is large, the adhesive strength of the envelope 5 is improved.

本発明は上記一実施例に限定されるものではなく、例え
ば半導体ウェハの膜厚は200μmでなくともよい。ま
た砥石は3種類以上用いてより細かな網目状の研削溝を
形成してもよい。
The present invention is not limited to the above embodiment; for example, the thickness of the semiconductor wafer may not be 200 μm. Further, three or more types of grindstones may be used to form finer mesh-like grinding grooves.

〔発明の効果〕〔Effect of the invention〕

本発明方法によると、研削砥石により半導体ウェハに網
目状の研削溝を形成することにより、外囲器との接触抵
抗の小さい素子を簡単に形成することができるという効
果がある。
According to the method of the present invention, by forming mesh-like grinding grooves in a semiconductor wafer using a grinding wheel, an element having low contact resistance with an envelope can be easily formed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)乃至(c)は本発明の一実施例方法を示す
工程図同図(a)はこの実施例により形成さ′れたウエ
ハ上の網目状の研削溝を示すウェハ斜視図、第一2図は
本発明の一実施例方法により研削されたウェハを分割形
成した素子を外囲器に接着・固定した状態を示す側面図
、第3図(a)は従来の研削方法を示す斜視図、同図(
b)は従来の一方向の研削溝の形成されたウェハを示す
斜視図である。 回     尺即 荊天 第1囚 (a) 第1図 (C) (d) 第2図 第 3  rA
1(a) to 1(c) are process diagrams showing a method according to an embodiment of the present invention. FIG. 1(a) is a wafer perspective view showing mesh-shaped grinding grooves on a wafer formed by this embodiment. , Fig. 12 is a side view showing a state in which an element formed by dividing a wafer ground by an embodiment method of the present invention is adhered and fixed to an envelope, and Fig. 3(a) is a side view showing a state in which an element formed by dividing a wafer ground by an embodiment method of the present invention is adhered and fixed to an envelope. Perspective view shown, same figure (
b) is a perspective view showing a wafer in which conventional unidirectional grinding grooves are formed; Time Shaku Soku Jingten 1st prisoner (a) Figure 1 (C) (d) Figure 2 3 rA

Claims (1)

【特許請求の範囲】[Claims] 研削砥石を用いて、半導体ウェハを研削するにあたりこ
の研削面に少なくとも2方向以上の研削溝を形成するこ
とを特徴とする半導体ウェハの研削方法。
A method for grinding a semiconductor wafer, which comprises forming grinding grooves in at least two directions on a grinding surface of the semiconductor wafer using a grinding wheel.
JP18052185A 1985-08-19 1985-08-19 Grinding method for semiconductor wafer Pending JPS6244366A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18052185A JPS6244366A (en) 1985-08-19 1985-08-19 Grinding method for semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18052185A JPS6244366A (en) 1985-08-19 1985-08-19 Grinding method for semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS6244366A true JPS6244366A (en) 1987-02-26

Family

ID=16084718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18052185A Pending JPS6244366A (en) 1985-08-19 1985-08-19 Grinding method for semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS6244366A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7098108B1 (en) * 1998-06-30 2006-08-29 Fairchild Semiconductor Corporation Semiconductor device having reduced effective substrate resistivity and associated methods
JP2018182129A (en) * 2017-04-17 2018-11-15 株式会社ディスコ Processing method of wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7098108B1 (en) * 1998-06-30 2006-08-29 Fairchild Semiconductor Corporation Semiconductor device having reduced effective substrate resistivity and associated methods
JP2018182129A (en) * 2017-04-17 2018-11-15 株式会社ディスコ Processing method of wafer

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