JPS6243900A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a nonvolatile semiconductor storage device with high reliability by adding a means for conducting the reliability test to a one-time PROM. CONSTITUTION:In setting data D1 to 0 level and a control signal D2 to 1 level, signals X, Y are set to a high voltage. Since an on-resistance of a MOS transistor 23 is selected as a large value, a load resistor as a load circuit 21 is increased and in wiring data, a very slight quantity of electrons only are injected to the floating gate of a memory cell 11. After the data is written, the cell is left for a long time at a high temperature and whether or not the electrons are lost from the floating gate is checked to conduct the reliability test. A cell where the electron is lost and whose voltage-current characteristic is deviated from a curve (c) shown in a figure 6 is thrown away as a defective cell.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a nonvolatile semiconductor memory device using a nonvolatile semiconductor element as a memory cell.

[Technical background of the invention and its problems] Ultraviolet erasable nonvolatile semiconductor memory device (hereinafter referred to as UV-
(referred to as EPROM) is well known.

Since this UV-EPROM can freely erase the stored contents with ultraviolet light, data can be written and erased many times.

FIG. 5 is a □ circuit diagram showing a typical configuration of a data writing circuit portion in the UV-EPROM as described above. Reference numeral 51 is a memory cell consisting of a MOS transistor having a floating gate structure, whose control gate is supplied with a selection output signal X from a row decoder, and 52 is a memory cell for column selection whose gate is supplied with a selection output signal Y from a column decoder. M.O.
The S transistor 53 is a load MOS transistor during writing, whose gate is supplied with the output data D from the write circuit, and these three transistors are connected directly between the high voltage vP for data writing and the ground voltage VSS.
and inserted into the column.

In this configuration, when writing data to the memory cell 51, that is, when writing data to the lf play game 1-,
When a child is to be injected, both signals X and Y are set to a high voltage, and data D is also set to a high voltage. When the data D is set to a high voltage, the transistor 53 is turned on, and a high voltage (P) is applied to one end of the transistor 52. At this time, this L transistor 52 is also turned on by the signal Y, so through this transistor 52,
A high voltage is applied to one end between the source and train of the memory cell 51. In the memory cell 51, the high voltage signal X is also applied to its control gel, so the impact ionization generated near the drain causes electrons and
A pair of holes is generated, and electrons from the holes are injected into the floating gate to write data.

FIG. 6 is a characteristic curve diagram showing the relationship between control gate voltage VG and train current ID in a nonvolatile memory cell having a 7f-free gate structure. Since the threshold voltage of a memory cell in which no electrons are injected into the floating gate 1 is low, its VG-ID characteristic is as shown by curve a in the figure. In other words, the drain current ID of VG (1-1 is the example,
is i4i 4 enough. On the other hand, since data writing is not possible as shown in -1-, and the threshold voltage of the memory cell is higher than y7, its VG-ID characteristic becomes the curve J- in the figure.

That is, the train current ID does not flow unless the value of VG is high to a certain extent, and the drain current hardly flows when the power supply voltage VC during normal reading is applied.

In this way, in the memory cell 51, data "1", "
0" is memorized. Once written data is erased by irradiating the floating gate with ultraviolet rays. By irradiating the floating gate with ultraviolet rays, the electrons previously stored in the l'? play game lose energy. is applied and discharged from the floating gate, thereby returning the threshold voltage of the memory cell to its original low value.

Such a UV-EPROM chip is sealed in an envelope with a glass window that transmits ultraviolet light because it is necessary to irradiate the floating gate of the memory cell with ultraviolet light. Such special envelopes are more expensive than ordinary plastic envelopes.

For this reason, UV-EPROM is more expensive than other memories.

By the way, it is said that most of the UV-EPROMs used above write data only once. In other words, the user only needs to write any data once at hand, and there is no need to erase it. For this reason, a UV-EPROM chip was enclosed in a normal plastic envelope without a window for ultraviolet irradiation, and data could not be erased but data could be written only once.
ROM exists. This type of PROM is called a one time FROM, and can be manufactured at low cost because it can be made of a normal plastic envelope.

However, since such a one-time FROM is enclosed in a plastic envelope, there is a disadvantage in that the reliability test of the memory cell cannot be performed before the product is shipped.

As noted above, the memory cells of non-volatile semiconductor devices are generally made of MOS +- transistors with a floating gate structure, and the reliability of such memory cells depends on the floating gate. It is involved in the loss of electrons from the In a normal UV-FROM, data is written to all memory cells once, electrons are injected into the floating gate, the voltage-current characteristics are changed to the curve shown in Fig. 6, and then the voltage is stored in a high temperature state for a long period of time, for example at 150°C. After leaving it for 48 hours, we conducted a reliability test by checking to see if electrons were pulled out of the floating gate. Electrons are extracted and those whose voltage-current characteristics change from the curve shown in FIG. 6 are discarded as defective products. On the other hand, those whose characteristics have not changed are then subjected to de-erasing by irradiation with ultraviolet rays, and the voltage-current characteristics are returned to curve a in FIG. 6 before being shipped.

However, in the conventional one-time FROM, which is enclosed in a plastic envelope, once data is written, it cannot be erased again. As mentioned above, it is not possible to perform a one-reliability test. For this reason, the one-time FROM has a disadvantage in that it has low reliability.

[Purpose of the Invention] This invention was made in consideration of the circumstances as described in Section I [7], and its purpose is to improve reliability by adding a means for testing reliability f'l to a one-time PROM. ,
An object of the present invention is to provide a nonvolatile semiconductor memory device with high reliability.

[Summary of the invention] Item 1] In order to achieve objective 1, in this invention, j'
The load resistance value of the load circuit, which is the load when injecting electrons into the lf floating gate of a memory cell consisting of an MO3+- transistor with a floating gate, is changed in accordance with a control signal, and this causes a slight drop in the floating gate. Kana Tsume electrons are injected to check for electron loss under high temperature conditions.

The electric current f injected into the n-type gate during this reliability test does not significantly change its threshold voltage, so it is shipped as a product as is without erasing, that is, emitting electrons.6:I can do.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a nonvolatile semiconductor memory device according to the present invention.

In FIG. 1, 11 each have a floating gate structure.
This is a memory cell consisting of an OS transistor. These plurality of memory cells 11 are arranged in a 7-trix shape in the row and column directions, and the control gates of the plurality of memory cells 11 arranged in the same row are connected in parallel to one of the plurality of row lines 12. It is connected.

Further, the drains of one memory cell 11 arranged in the same column are connected in parallel to one of the plurality of column lines 13. Furthermore, the sources of all memory cells 11 are commonly connected to ground voltage VSS.

Any one of the plurality of row lines 12 is selectively driven by the output of the row decoder 14. The row decoder 14 is supplied with a high voltage P used when writing data and a power supply voltage VC used when reading normal data. At times, a voltage VC is output to one selected row line 12, and at the time of data writing, a high voltage vP is output to one selected row line 12.

-11 The plurality of column lines 13 are connected to the data detection node 1 (1
are commonly connected. MO8I for selecting each column line above
- The gate of the transistor 15 is connected to each of a plurality of column selection lines 18 to which the selection output of the column decoder 17 is supplied. The column decoder 17 is also supplied with the high voltage vP and the power supply voltage VC used for normal data reading, and the column decoder 17 is supplied with the selected voltage when reading data from each memory cell 11. A voltage VC is output to one column selection line 1B, and a high voltage VP is output to one selected column selection line 18 during data writing.

A sense amplifier (S/A) 19 for detecting data read from the memory cell 11 is connected to the 1-2 data detection node 16. Furthermore, the node 16 has an M for load used when reading data.
The source of the OS transistor 20 and one end between the trains are connected. The source of this MOS transistor 20,
The other end between the drains and the gate are both connected to a power supply voltage VC used during normal data reading.

Further, a load circuit 21 is connected to the data detection node 16, which is used as a load when writing data to the -1-registered memory cell 11. As shown in the figure, this load circuit 21 is composed of two MOS transistors 22 and 23 whose sources and drains are connected in parallel between the node 16 and a high voltage □VP used for data writing, for example. □There is. And one of these MO8I-transistor
Data D1 output from the data input circuit 24 is supplied to the gate of □22. This MOS
MO8I-transistor 2 whose element dimensions, for example, the ratio W/L of channel width W to channel length, are adjusted so that the on-resistance value is sufficiently large relative to the transistor 22.
The control signal D2 is supplied to the gate of No.3. The data input circuit 24 is supplied with the high voltage ■P as a power source, and depending on the write data, either the high voltage ■P or the ground voltage VSS is applied to the data D1 (!: Selectively output.

Next, the operation of the PROM having the configuration as described in "2" will be explained.

FIG. 2 shows a nonvolatile semiconductor memory device (FR) having the configuration shown in FIG.
FIG. 2 is a circuit diagram showing a schematic configuration of a data write circuit portion in OM). 11 is the row decoder 1 to the control gate.
a memory cell 15 supplied with a selection output signal X from 4;
are column selection MOS transistors 22 and 23 whose gates are supplied with the selection output signal Y from the column decoder 17;
is load circuit 2 used as a load when writing data.
This is a MOS transistor constituting 1. When testing the reliability of this circuit, data D1 is set to ``0'' as shown in period T1 in the timing chart of FIG.
`` level, the control signal D2 is set to the ``1# level,'' and the signals X1Y are both set to high voltage.

When the control signal D2 is set to the "1" level, the transistor 23 in the load circuit 21 is turned on, and a high voltage is applied to one end of the transistor 15. At this time, since the transistor 15 is also turned on by the signal Y, a high voltage is applied to one end between the source and the train of the memory cell j] via the transistor 15. Memory cell 11
Since the high-voltage signal Data is essentially written. However, since the on-resistance of the MOS transistor 23 is set to a large value, the value of the load resistance as the load circuit 21 is also large, and when writing this data, the amount of lf free agate in the memory cell 11 is extremely small. of electrons are injected.

Therefore, the memory cell 11 to which this data has been written
In this case, the increase in threshold voltage is extremely small, and the characteristics showing the relationship between control gate voltage VG and drain current ID are as follows.
It becomes like the curve C in FIG. 6 above. That is, the power supply voltage VC when the value of VG is 1111 when the normal reading is 5V, for example.
Although the drain current ID flows sufficiently even in the lower range,
As shown by characteristic curve a, the threshold voltage is significantly higher than that of a memory cell to which no data has been written.

Next, after this data has been written, the device is left in a high-temperature state for a long period of time, and reliability is tested by checking whether electrons have been extracted from the floating gate. If the electrons are removed and the voltage-current characteristics change from curve C in FIG. 6, they are discarded as defective products. On the other hand, products whose characteristics have not changed are shipped as non-defective products.

The reliability test was carried out as shown in FIG. 6, and the characteristics of each memory cell 11 in the shipped PROM were as shown by curve C in FIG. In this state, the user of this PROM writes arbitrary data. When performing normal data writing in the circuit shown in FIG. 2, both the data D1 and the control signal D2 are set to the "1# level" as shown by period T2 in the timing chart of FIG. Set to a high voltage. By setting Dl and D2 to the #1" level, transistors 22 and 23 are both turned on in the load circuit 21, and the value of the load resistance of the load circuit 21 is made sufficiently small. Sufficient m electrons are injected into the floating gate of the memory cell 11 in a short time. As a result, the characteristics of the memory cell to which data has been written change as shown by the curve in FIG. After writing the data, the difference between the threshold values of characteristic curves C and b is “1”, 0”.
Determine the data.

By the way, the load MO used when writing data
A conventional PR in which only one S transistor is provided and the value of the load resistance of this load circuit is fixed.
In OM, the on-resistance value is reduced in order to perform normal data writing at high speed, so it is possible to control this load MOS transistor and inject a very small amount of electrons into the floating gate of the memory cell. It is difficult.

However, in the above embodiment, since data is written through the negative I:1 MOS transistor 23 which has a large on-resistance value, a very small amount of electrons is transferred to the l'F'a gate of the memory cell. can be easily injected into Furthermore, since the load resistance value in the load circuit 21 is reduced during normal data writing, it is possible to achieve data writing at the same high speed as in the prior art.

It goes without saying that this invention is not limited to the embodiments described in - above, and that various modifications are possible. For example, in the above embodiment, during the reliability test 1-, the load circuit 21
The explanation has been made regarding the case where only the MOS transistor 23 in the load circuit 21 is turned on, and both the MO3+- transistors 22 and 23 in the load circuit 21 are turned on during normal data writing. may be set as shown in FIG. That is, in the example shown in FIG. 4, only the control signal D2 is set to the "1" level to turn on only the MOS transistor 23 during a reliability test, and only the data D1 is set to the "1" level to turn on the MOS transistor 23 when writing data.
In this case, only 2 is turned on.

In this way, with the PROM of Example 1, it is possible to perform reliability tests even on one-time PROMs whose structure can only be irradiated with ultraviolet rays, thereby significantly improving reliability. It's now possible.

[Effects of the Invention] As explained above, according to the present invention, a highly reliable non-volatile semiconductor memory device is provided by adding means for testing reliability to a one-time PROM. I can do it.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram schematically showing a data writing circuit portion of the circuit of the embodiment, and FIGS. 4 is a timing chart showing different operations of the above embodiment circuit, FIG. 5 is a circuit diagram schematically showing the data writing circuit section of a conventional storage device, and FIG. 6 is a diagram showing the embodiment device and the conventional device described in -. It is a characteristic curve diagram for explaining. 11 memory cell, 12... row line, 13... column line,
14... Row decoder, 15... MOS transistor for column line selection, 16... Data detection note, 17... Column decoder, 18... Column selection line, 19... Sense amplifier,
20...Negative 4 when reading data: MO8+- transistor for engineering use, 21...Load circuit, 22, 23...MOS transistor for load when writing data, 24...
・Data input circuit. Applicant's representative Patent attorney Takehiko Suzue vp vp VSS Vss Fig. 1 yp vp VSS Fig. 2 11]=Tfu, 17H -111 Rinshi---01 -TI, T2- 3rd 1゜D1=====7TT0 11゛'' P V'ss Figure 5 V G Figure 6

Claims (2)

[Claims] (1) A memory cell consisting of a MOS transistor with a floating gate, in which data is programmed depending on whether or not electrons are injected into the floating gate, and a load when electrons are injected into the floating gate of the memory cell. 1. A nonvolatile semiconductor memory device, comprising: a load circuit, wherein the load circuit is configured to have a resistance value that changes according to a control signal. (2) The load circuit is composed of at least two MOS transistors connected in parallel, and the resistance value is determined by selectively controlling conduction of one of the two MOS transistors according to the control signal. A nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is configured to vary.