JPS6243505A - Method and instrument for detecting defect of pattern - Google Patents

Abstract

PURPOSE:To enable the automatic inspection and the high speed inspection of a multilayer pattern by correcting a change in the speed of an X-Y stage to detect a specific region on the pattern to be inspected and positioning the pattern with a high accuracy. CONSTITUTION:The position of an X-Y stage 11 in an X direction is detected by a position detector, which produces a timing signal for every displacement of the stage 11 by a constant distance and the timing signal is supplied to an irradiated light quantity storing type image sensor 17 as a start signal. At this time, though the period of the start signals is changed by the effect of a change in the speed of the X-Y stage, since the period is equal to an incident light quantity storing time of the sensor 17, a gradational image from which the effect of a change in speed is removed by normalizing the output of the sensor 17 by said time is detected in synchronism with the position of stage 11. Thus, a specific pattern on a chip is detected and a timing for taking in the detected pattern into an image memory 21 is controlled. As a result, a chip arrangement error in an X-Y direction is corrected and the gradational image in synchronism with the position of the chip is stored in the image memory 21. Thus, a multilayer pattern is detected with a high accuracy and a visual inspection is automated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a technology for inspecting the appearance of multilayer patterns of semiconductor devices such as LSI wafers.
The present invention relates to a method and apparatus for detecting pattern defects using a dimensional image sensor.

[Background of the invention]

Integrated circuits such as LSIs are becoming more highly integrated and smaller. In the production of such fine patterns, even if careful attention is paid during the production process, defects often occur in the patterns, and careful inspection is required. The initial inspection is
This was done visually by a large number of inspectors using microscopes, but it was easy for the eyes to get tired and many defects were overlooked, which caused problems in terms of quality control. Additionally, as production volume increases, automating inspections has become an extremely important issue.

First, an LSI wafer to be inspected will be explained using drawings. FIG. 8 is a plan view showing an example of an LSI wafer. LSI wafer 1 is.

A large number of repeated patterns called chips 2 are formed on the surface of a silicon single crystal thin plate with a diameter of about 31 nch to 51 nch or 431 nch and a thickness of about α5.

All of the chips 2 on one LSI wafer 1 have the same circuit pattern, so in order to inspect the circuit patterns in the chip 2, it is necessary to check the same locations 2α and 2b in two adjacent chips 2. It is possible to magnify the image at high magnification using a microscope, compare these images, and identify areas that do not match as defects.

FIG. 9 shows an example of a conventional LSI wafer visual inspection apparatus. Corresponding points 2a, 24 on two adjacent chips 2 on the LSI wafer 1 are illuminated with illumination lights 3α, 54, magnified at high magnification by objective lenses 4m, 44, and photoelectric converters 5α, 5
image on 6. The photoelectric converters 5m and 54 convert the optical images into electrical signals, and the determination circuit 6 compares and determines the two electrical signals. When the circuit pattern to be inspected is normal, the optical images formed on the photoelectric converters 5α and 5A are the same,
Therefore, the photoelectric converter outputs are also the same. If a defect exists, different signals will be generated, and by comparing these signals, it is possible to detect the defect. A one-dimensional image sensor is used as a photoelectric converter, and the XY stage 7 is moved at high speed to detect minute pattern defects.

When inspecting a pattern consisting of a multilayer structure using such equipment, since the amount of f# information is insufficient when the pattern is binarized, it is necessary to convert it into a grayscale image and compare it. 5α.

It is required that the circuit patterns on the two sides detected by 5b be the same even in terms of shading in the normal part of the wafer.

However, in reality, the illumination lights 3α and 5b are non-uniform.

Due to non-uniformity in the characteristics of the photoelectric converters 5a and 5b.

Even if the detected patterns are the same, differences in shading occur, and it is extremely difficult to detect minute defects on multilayer patterns using the above-mentioned apparatus. Also, two sets of optical systems increase the cost of the device.

Therefore, by using only one set of optical systems, the pattern of the chip 2α is detected by the objective lens 4G and the photoelectric converter 5G, and this is stored in a memory (not shown), and the pattern of the chip 2h is detected by the same photoelectric converter. A conceivable method is to read out and compare the 2α pattern stored in the memory when detected by 5a.

A well-known example that describes in detail a method for comparatively inspecting two chips using one set of optical systems and a TV left camera is published in Japanese Patent Application Laid-Open No. 1986-
There are 154003. This is done using the TV left camera.
Since the pattern is detected by moving the Y stage in steps and repeats, there is no problem in detecting defects due to speed fluctuations of the stage. In addition, in order to correct wafer rotation errors, the apex coordinates of the chips are determined and the two chips are aligned, thereby correcting chip alignment errors. However, since this method requires the XY stage to be moved in steps and repeats to detect the pattern, there is a limit to how much throughput can be improved.

[Purpose of the invention]

An object of the present invention is to provide an apparatus and an inspection method for automatically inspecting multilayer patterns, which enable high-speed inspection.

[Summary of the invention]

Since two chips of grayscale images of a multilayer pattern are compared using one optical system, K requires highly accurate alignment so that the two chips correspond accurately. Since the present invention aims to speed up the inspection, the XY stage on which the inspection object is placed is not aligned in a step-and-repeat manner, but is inspected while moving at a constant speed.

At this time, if there is a speed variation of the XY stage, shading will occur in the object to be inspected. Further, if the XY stage moves, for example, in the X direction at a speed higher than a predetermined speed, the pixel size in the X direction becomes large, and conversely, if the stage moves at a low speed, the pixel size becomes small. The influence of speed fluctuations cannot be ignored even if the pattern to be inspected is a repeating pattern with an interval of several μm or in a region close to each other on the wafer.

In order to detect very fine pattern defects, it is essential for the XY stage to move at a constant speed.
Variation in the speed of the Y stage causes a difference in density between the two chips being compared, which impedes defect detection performance.Furthermore, a slight alignment error in the pattern on the wafer ((L
In the course of developing the present invention, it was found that air flow (approximately 5μ wind) also causes a difference in density and becomes an obstacle to detection.

Therefore, in the present invention, speed fluctuations of the XY stage are corrected by using an irradiation light accumulation type image sensor such as a COD image sensor, and on the other hand, a specific area on the pattern to be inspected, such as a scribe area, is detected, A configuration is adopted that increases the precision of alignment of repeated patterns by controlling the timing of input to the image memory.

In detail, t) The X-direction position (sub-scanning direction position) of the XY stage is detected by a position detector, and a timing signal is generated every time the xY stage moves a certain amount in the X direction, and the Give it to the image sensor as a start signal.

At this time, the period of the start signal fluctuates due to the influence of speed fluctuations of the XY stage, but since this period is the incident light amount accumulation time of the image sensor, it is possible to normalize the image sensor output using this period. The configuration is such that a grayscale image from which the influence of speed fluctuations has been removed is detected in synchronization with the XY stage position.

2) By detecting a specific pattern on the chip, control the timing of loading the detected pattern into the image memory. As a result, the configuration is such that the chip arrangement error in the XY directions is corrected and a grayscale image synchronized with the chip position is stored in the image memory.

[Embodiments of the invention]

In order to automate the visual inspection of multilayer patterns on LSI wafers, it is necessary to compare two chips of gray scale images, as described above. This is because the target is a multilayer pattern, which makes it difficult to binarize, and it is necessary to compare the shading as it is. This is also because comparison of grayscale images is advantageous for detecting minute defects.

In order to realize two-chip comparison of grayscale images, the grayscale images must be detected with high precision, aligned, and compared. Moreover, as the turns on the LSI Ueno 1 become finer, the defects to be detected are also becoming finer, and inspection must be performed at high magnification, so there is no need to consider increasing the detection speed.

For this purpose, pattern detection is performed by continuously moving the XY stage at high speed using a one-dimensional image sensor.1. Ta.

Hereinafter, the present invention will be explained using FIGS. 1 to 7. g
In Figure 1, the pattern of the LSI wafer mounted on the
The image is formed through an imaging lens (not shown). A speed command 8 is given to a motor driver 9, a motor 10 is driven, and the XY stage 1 is caused to scan in the X direction (sub-scanning direction). The rotational speed of the motor is detected by a rotary encoder 12 directly connected to the shaft of the motor IO, and fed back to the motor driver 9 to keep the rotational speed of the motor constant. Due to this feedback mechanism, Tanabata 10 tries to rotate at a certain constant speed, but
There are still speed fluctuations in the moving speed of Y stage 1.

A position detector 13 is attached to the XY stage 1, and a timing signal 14 is generated each time the XY stage moves a certain amount in the X direction. The timing signal 14 is given as a start signal to the image sensor 17, and the image sensor is
Synchronize with the movement of the Y stage. The image sensor 17 is internally scanned in the Y direction (main scanning direction) by the clock generated by the clock generation circuit 18, and the XY stage 1
] to obtain a two-dimensional image signal.

The timing signal 14 is assumed to be a signal representing the pixel interval. The interval T between the timing signals 14 is measured by an accumulation time counter 19, and the output of the image sensor 17 is corrected by a sensitivity correction circuit 20. The corrected image sensor output is written into the image memory 21 and at the same time is sent to the comparison/judgment circuit n together with the already written data. The comparison/judgment circuit 22 compares these image data and determines a mismatch as a defect. The image memory is controlled by an X coordinate counter 15 and a Y coordinate counter 16. The X coordinate counter counts the timing signal 14, and the Y coordinate counter controls the address of the image memory by counting the clocks. The Y coordinate counter is set to a constant value, which will be explained later, when the timing signal 14 is received. The positional deviation detection circuit 23 detects the arrangement error of the chips and controls the X coordinate counter 15 and the Y coordinate counter 16 according to the amount of one positional deviation.
The image memory 21 stores corresponding portions of repeated turns at the same coordinates.

Next, the operation of each part will be explained.

Ideally, the moving speed of the XY stage l in the X direction is a speed at which it moves by one pixel dimension in the internal scanning period of the image sensor 17, but in reality, that speed deviates from the ideal speed. is normal. As shown in FIG. 2, the position detector 13 attached to the XY stage 17 has a regularly marked scale. By reading the position of the %xY stage using this scale and driving the image sensor 17, the speed of the XY stage can be determined. Presence or absence of fluctuation,
Chip patterns can be regularly sampled at equal intervals regardless of size.

The speed fluctuation of the XY stage l appears as a fluctuation in the incident light amount accumulation time (exposure time) of the image sensor 17,
Because of this IL, the brightness of the image signal from the image sensor also fluctuates.

FIG. 3 shows this situation with the same pattern in the main scanning direction. As shown in the figure, the image signal exposed and accumulated in the interval Ti is transmitted to the image sensor 17 in the next interval Ti+1.
However, the interval T&.

If the magnitude of Ti+1 is different, the signal level will be different even if the image signals are for the same pattern. Therefore, in order to obtain an image signal with a correct signal level, it is necessary to correct the signal level of the image signal from the image sensor 17 according to the incident light amount accumulation time. The image signal 〆t is converted into i k □ i . Here k is a constant.

The positional deviation detector port detects the alignment error of the chip 2. X
The alignment error pressure in the direction is corrected by detecting the left end turn of the chip within nine predetermined areas as shown in FIG.

That is, each time the leftmost pattern of the X-coordinate number 15 is detected, it is cleared to zero. However, when the XY stage l] moves in the opposite direction to the direction shown in the figure, the X coordinate counter 15 is cleared to zero each time a pattern at the right end of the chip is detected. Regarding the chip arrangement error in the Y direction, the amount of positional deviation Y shown in the figure can be calculated as shown in Figure 4 (
In the first sub-scanning indicated by Al, the pattern of the upper end of the chip is detected in advance in the predetermined area of FIG. 4(α). Then, after the II2 sub-scan, the X coordinate counter 16 counts #- for the chip 2α.
An offset is provided by a certain constant value α pixel, and the detected pattern is written into the image memory 21. For chip 2b, writing is performed with an offset of α-ΔY pixels. Offset α considers the possible range of alignment error in the Y direction, and α≧
Let ΔYyo. Here, ΔYyo is the maximum value of the alignment error in the X direction. As a result, the patterns of the chips 2a and 2h are aligned in the X and Y directions on the image memo 1) 21, and the corresponding patterns inside the chips 2α and 24 are placed at the same location. It is sufficient if the chip 2cL or 2 has a capacity sufficient to store the range scanned by the image sensor 17. Figure t45 shows how the image is stored in the image memory. In the figure, the shaded area is the area written into the image memory.

IFE indicates a write signal to the memory, and BE indicates a read 1 signal from the memory. That is, the image memory 21 has (st
After address y)=(o+α), the pattern of the chip 2a is written from the left end of the chip.

When the left edge of the pattern of chip 2b is detected, the image memo IJ 21 contains the chip 2b from address (0, α-ΔY) onwards.
At the same time as the pattern is written, the pattern data of the chip 2a is read out from the image memory. Reading of image data is performed before writing image data to the same address. The detected pattern of the chip 2h and the pattern of the chip 2d read out from the image memory 21 are sent to a comparison/judgment circuit n,
Determine the discrepancy as a defect.

FIG. 6 shows the edge detection operation by the positional deviation detector n. In FIG. 6(α), for example, the pattern shown in FIG. Apply the edge operator and
Detect edges as shown in IK. From this figure 6 (
A histogram of edges in the Y direction within a predetermined range XFI as shown in C1 is created, and the position of the X coordinate with the highest frequency is detected as the edge position. Edge positions of the pattern in the X direction can also be detected in the same manner as shown in FIG. The chip alignment error can be determined from the detected edge position.

To correct the alignment errors in the X and Y directions, the patterns on the left and top edges of the chip are detected by detecting a specific pattern inside the chip by moving the XY stage and comparing it with design data. It is also possible to replace this by calculating the coordinates of the upper end pattern.

The positional deviation detection circuit n operates when the position detector 13 detects the coordinates of the left end and upper end patterns, and controls the X coordinate counter 15 and the X coordinate counter 16.

With this configuration, even if the scale length of the position detector 13 changes due to temperature fluctuations, there will be no difference between the two chips being compared, resulting in extremely high accuracy. Comparative tests can be done.

〔Effect of the invention〕

According to the present invention, it is possible to detect a multilayer pattern of an LSI wafer with high precision, and to automate the visual inspection thereof. That is, it is possible to accurately detect a grayscale image of a pattern regardless of speed fluctuations of the XY stage or alignment errors of repetitive patterns, and ultrafine defects can be detected with high throughput and sharpness by comparing two chips of grayscale images.

[Brief explanation of the drawing]

wE1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the positional relationship between a position detector, an image sensor, and a chip,
Figure 3 is a diagram showing the relationship between the incident light amount accumulation time of the image sensor and the image signal, Figure 4 (4) and Figure 4 (A) are diagrams showing an example of positional deviation detection, and the ms diagram is a diagram of writing to the image memory. Figure 6 shows an example of edge detection in positional deviation detection, Figure 7 shows an example of an edge operator, Figure 8 shows an example of LSI Weno. 9
The figure shows an example of a conventional LSI wafer appearance inspection apparatus, and FIG. 1O shows an example of chip arrangement error. 1...LSI wafer 2...chip 1]...
xY stage 13...Position detector 15...X
Coordinate counter 16...Y coordinate counter 17...
Image sensor 18... Clock generation circuit 19.
・・1 performance time counter 2o・・sensitivity correction circuit 21・
...Face edge memory η...Comparison judgment circuit n...
Positional deviation detection circuit

Claims (1)

[Claims] 1. An image of the pattern is obtained by performing sub-scanning by moving the pattern in a certain direction, and by main-scanning a one-dimensional image sensor arranged in a direction orthogonal to the certain direction. In the method of detecting and comparatively inspecting, each time the inspection object moves by a certain amount, a signal is given to a one-dimensional image sensor to produce a corrected gray scale image,
In addition, by controlling the timing of storing image signals by detecting a specific pattern of the repetitive pattern, errors in the repetitive pattern arrangement in both the X and Y directions can be corrected, and a grayscale image can be stored in synchronization with the repetitive pattern. A method for detecting pattern defects, comprising: reading out a grayscale image of a repeated pattern, and comparing the grayscale image with the grayscale image to detect a defect. 2. In the pattern defect detection method according to claim 1, the corrected grayscale image is created by normalizing the grayscale image based on the time required for the movement each time the detection target moves by a certain amount. A method for detecting pattern defects obtained by 3. means for moving the pattern in a certain direction; a one-dimensional imaging device disposed in a direction perpendicular to the certain direction; and means for applying a signal to the one-dimensional imaging device each time the inspection object moves by a certain amount. , a means for storing a grayscale image of a repetitive pattern on the inspection object inputted from the image sensor; and a means for controlling the timing of storing the grayscale image by detecting a specific pattern on the repetitive pattern, and controlling the timing of storing the grayscale image in both the X and Y directions. A pattern comprising: means for correcting a repeating pattern arrangement error; and means for storing a grayscale image of the repeating pattern in synchronization with the repeating pattern, and reading a previously stored grayscale image of the repeating pattern and comparing the grayscale images. Defect detection equipment. 4. In the pattern defect detection device according to claim 3, the signal providing means normalizes the output of the one-dimensional image sensor based on the time required for the inspection object to move a certain amount. A pattern defect detection device including means for detecting a pattern defect. 5. In the pattern defect detection device according to claim 5, the means for correcting the repeating pattern arrangement error corrects the error in the vertical direction by detecting the upper end or the lower end of the repeating pattern in the first sub-scanning. A pattern defect detection device comprising means for calculating the address and writing/reading the address in the storage means by detecting the left end or right end of the repetitive pattern in the second and subsequent sub-scannings.