JPS624333A - Evaluation of semiconductor element - Google Patents

Abstract

PURPOSE:To realize carrier injection by avalanche which is stable with a low pulse voltage by applying a forward bias to the P-N junction of an MIS capacitor. CONSTITUTION:An MIS capacitor is constituted by an N-type Si semiconductor 12, a P-type Si semiconductor 1, an SiO2 film 2, a gate electrode 3 and a facing electrode 13. Avalanche injection of electrons is carried out by connecting switches 4 and 16 to the terminal A side an applying a pulse voltage of the level of a breakdown voltage rapidly by a pulse generator 5. As for characteristic measurement after the injection, the switches 4 and 16 are connected to the terminal B side for measurement through the ohmic contact electrode 13 to form a closed circuit of an electrostatic capacitance meter and a voltage source 7. Then C-V characteristics of the MIS capacitor are measured and trap density in the bulk of the film 2 is evaluated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for evaluating semiconductor devices, and in particular, injects electrons or holes (hereinafter referred to as carriers) into an insulating film to This relates to a method for evaluating the amount of traps.

[Conventional technology]

In order to stabilize the electrical characteristics and increase the reliability of MID (metal-insulator film-semiconductor structure) devices, it is important to evaluate the characteristics of the constituent elements and the interface state. Silicon nitride films (SiOW), silicon nitride films (5lsN4), etc. are often used as insulator films, but the behavior of traps existing in the holes in these insulator films is different from that of MIS devices. Significantly affects operating characteristics. K, which electrically evaluates the trap density, must ionize the traps, and for this purpose it is necessary to inject carriers into the insulator film. The trap that captures and ionizes the injected carriers is the well-known C-Vs property (capacitance) of the canopy that has an MIS structure.
The density is evaluated based on the insulator pressure dependence.

Conventionally, the method of injecting carriers into an insulator film is as follows:
The avalanche injection method has mainly been used.

This injection method has many advantages, such as being able to inject more carriers into the insulator film than other methods, as well as simplifying the structure of the evaluation sample and the configuration of the evaluation test equipment. have

FIG. 3 shows an example of a MIS capacitor for evaluating trap density in an insulator film and an evaluation test apparatus according to a conventional method. , MIS canon is shown in the same figure (a)
As shown in FIG. 1, an insulating film 2 containing traps made of Si0. film is usually formed on a Si substrate (P-Otori) 1 doped with impurities to the extent of lXl0'' to lXl0'Hata/- using an oxide film formation technique. After forming a film to a thickness of about 100 psi, a metal gate electrode 3 made of At is formed to a predetermined thickness by PVD technology so as to be in ohmic contact with this insulating film 2. Note that this configuration example The intermediate carriers injected into the insulator film 2 are minority carrier electrons, and when the carriers to be injected are holes, an n-board Si substrate doped with impurities to the same extent is used.

Then, electron injection and measurement of the C-■ characteristics of the MIS capacitor are performed using the evaluation test apparatus shown in FIG. The method will be specifically explained below. First, MIS
The capacitor is attached to a predetermined position, the changeover switch 4 is connected to the A terminal side, and a closed circuit is formed with the pulse generator 5. Next, a positive pulse voltage is rapidly generated by the nozzle generator 5, and this is applied to the metal gate electrode 3 of the MIS capacitor, and minority carrier electrons are transferred from the pffisl substrate 1 to the psto 7 balancier. ,
Inject into membrane 2.

Here, the process of electron avalanche injection will be explained based on FIG. Before applying the pulse voltage, as shown in the same figure (-), the MIS system is in a thermal equilibrium state, and the Fermi level EFM of the AL gate electrode 3 and the 7-factor Lumi level of the Sll plate, p plate, sl semiconductor) 1 EF8 match, and from the difference in their work functions, pHsi At the surface of the semiconductor 10, the majority carrier holes 11 are repelled, and the minority carriers electrons 8 are slightly induced into the conduction band, and the energy impedance is bent downward. There is.

Although the MIS system is almost depleted in this way,
Since the impurity concentration of the past semiconductor 1 is high, the width of the depletion layer 16 determined by the extrinsic Debye length is narrow.

In addition, trap units are formed by traps 9 in the bulk of the 5ift film 2, but the electrons 8, which are minority carriers of the Sl semiconductor 1, cannot overcome the potential barrier between them and the SiO film 2. , are not injected into the stow film 2, so the trap 9 is electrically neutral. In the figure, 10 indicates an acceptor negatively ionized by electrons, and EC#EV indicates the lower end of the conduction band and the upper end of the valence band of the Sl semiconductor 1, respectively.

Next, on the surface of the Si semiconductor 10, a positive pulse voltage sufficient to cause an anno-9 Rancier is applied to the AL gate electrode 3 with a sweep of K that is so rapid that it is impossible to form an inversion layer, that is, about 10 m5ec· or less. When applied, the same figure (b)
As shown in FIG. 2, a depletion layer 16 spreads on the Si semiconductor 1 side. However, the applied pulse voltage is
Since the voltage applied to this depletion layer is set to about the so-called breakdown voltage, avalanche occurs at the surface of the Si semiconductor 10, and the electric field at this surface is maintained at a constant avalanche electric field. Coupled with the high impurity concentration of 1, the depletion layer 16 only has a certain narrow width. In this way, due to the high electric field in the depletion layer 16, the minority carrier electrons 8 in the conductor are accelerated and have a large kinetic energy. And this accelerated electron 8
collides with bonding electrons existing in the valence band, knocking them out to the conduction band, and this process is repeated cumulatively, and the Si
Avalanche occurs at the surface of the semiconductor 1, and a large number of electrons are injected into the SiO film 2. A portion of the electrons injected by this Anno 9 Rancier are captured by the trap 9. For this reason, trap 9, which was neutral before electron injection,
is negatively charged after implantation and acts as a space charge in the SiO film.

As described above, after injecting electrons into the film 2 using the avalanche, the changeover switch 4 is connected to the B terminal side, and a circuit is configured with the capacitance measuring device 6 and the voltage source 7. The noise voltage dependence (c-V
characteristics). As is well known, if there is a change in the space charge density in the bulk of the insulator film 2, it will cause a change in the C-V@gonadal line voltage of the MIS capacitor, so the density of ionized traps can be determined from this ( Journal of Applied Fixtures Volume 38, Number 12, P4582-P4588 (1967) (J
, Appl, Ph1s, vol 38, N112
F 4582-P4588 (1967)).

[Problem that the invention seeks to solve]

In the conventional method described above, the impurity concentration of the Sl substrate l is
It is limited to a medium to high concentration range of X 101' to I X 10f field/cd. In fact, the impurity concentration of the Si substrate 1 used as the MIS dino chair is
In many cases, the concentration is as low as I X 1 ()s6/- or less.

However, when using a Si substrate 1 with a low impurity concentration, the depletion layer 16 becomes wide at thermal equilibrium because it is determined by the extrinsic Debye length. Until reaching the so-called breakdown voltage where 7-9 Ranciers start, as the pR pulse voltage amplitude increases, the depletion layer 16 becomes S like a stepped p-n junction.
i It spreads widely toward the semiconductor 1 side. The diagram 5 shows this situation, and the impurity concentration of the substrate 1 is about 3 x 10"/-. According to the diagram, the breakdown voltage is as high as about 50 V, and the amplitude of the pulse voltage is higher than that. When this happens, an annolancier occurs on the surface of the Si semiconductor 1, and the surface electric field is maintained at a seven-parancier electric field, so that excessive voltage is applied only to the sio film 2, and the spread of the depletion layer 16 is suppressed. Its width is large, about 4 μm.Furthermore, if the pulse voltage is set higher than the breakdown voltage, the electric field around the metal gate electrode 3 becomes large, causing the so-called peripheral effect, which tends to cause dielectric breakdown.◇In this way, the Si substrate l If the impurity concentration of If it is higher, the electric field strength around the metal gate electrode 3 becomes more likely to cause dielectric breakdown in the insulator I[2.

Therefore, in a MIS capacitor with a conventional configuration, when a low impurity concentration OSi substrate 1 is used, a high pulse voltage is required for avalanche implantation. There is a problem if it cannot be done.

The present invention eliminates the problem of not being able to perform sufficient avalanche implantation when using a Si substrate with a low impurity concentration, as described above, and provides a wide range of selectivity in the impurity concentration of the Si substrate.7)9 Rancier implantation method The purpose of this study is to provide a method for evaluating semiconductor devices using .

[Means for Solving All Problems] The method for evaluating a semiconductor element having an MIS structure according to the present invention is based on a method for evaluating a semiconductor element having an MIS structure, which is based on a p-type Si semiconductor that forms a p-n junction, and an nm Si semiconductor, The p-n
A step of applying a pulse voltage to the metal gate electrode so as to provide a forward bias to the junction, and a depletion layer formed on the surface of the upper layer Si semiconductor by applying the pulse voltage to the p-n layer. At the same time, the majority carriers in the lower Si semiconductor are diffused through the potential barrier of the p-n junction to cause anolancier, and the carriers are injected into the insulator film to form the insulator. The amount of traps in the insulator film includes a step of ionizing traps in the film, and a step of measuring the ionized traps as an amount of charge change in the insulator film using the metal gate electrode and the counter electrode as measurement terminals. This is an evaluation of the following.

[For production]

In this invention, since the S1 semiconductor of the MIS capacitor has a p-n junction, in avalanche injection,
When applying a pulse voltage to the metal gate electrode, the upper layer Sl
Although the depletion layer formed on the surface of the semiconductor extends to this p-n junction, the width of the depletion layer is kept constant, and therefore a high electric field is maintained within this depletion layer.

In addition, by applying the above pulse voltage to the p-n junction, the majority carriers in the lower Si semiconductor are p-
It diffuses into the depletion layer through the potential barrier at the n-junction, is accelerated, and causes a large impact ionization effect, which easily causes anoranciers, so it is recommended to set the breakdown voltage at a low pulse voltage. I can do it.

Furthermore, when measuring the amount of traps in an insulator film ionized by avalanche injection of carriers as a change in charge, a metal gate electrode and a counter electrode are used as measurement terminal electrodes, so a semiconductor measurement thread and a normal It can be configured as an MIS system.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained based on the drawings.
The figure shows a configuration example of a MIS capacitor for evaluating trap density in an insulator film and an evaluation test apparatus according to the present invention. As shown in the figure (a), the MIS capacitor is made of an n-type Si semiconductor 1 having a predetermined impurity concentration ND.
2. A past semiconductor 1 having an impurity concentration of about K, I x 10f'/cII or less is deposited to a film thickness of about 1 to 3 μm by vapor phase epitaxy, MBE, etc. to form a Si substrate part. do. Next, an insulator film 2 made of a Si film is formed to a predetermined thickness using an oxide film formation technique on this Si substrate portion, and then A
The metal gate electrode 3 consisting of t and the counter electrode 13,
MI by forming ohmic contact with each
An S capacitor is configured. Note that in the Sl substrate portion, the impurity concentration ND of the nff18i semiconductor 12 is
The impurity concentration of pffis1 semiconductor 1 is higher than that of 8 people.

Next, referring to FIG. 2, the avalanche electron injection process when using this MIS capacitor will be explained. Before the pulse voltage is applied, M
The IS system is in a thermal equilibrium state, and in the Sl substrate, the upper pffisi semiconductor 1 and the lower n-type Si semiconductor 12 have a 7-luminium level that coincides with EF8, and this and At
The Fermi level KPM of the gate electrode 3 matches.

In the past semiconductor, since the impurity concentration is low, electrons are hardly excited to the conduction band and the minority carrier density is sufficiently low.On the other hand, at the surface, the first A depletion layer 16 is formed, and the energy band is curved downward. Note that the metal gate electrode 3 and p!
1Si If there is no work function difference between semiconductors 1, the 10th
There is no depletion layer and the energy band becomes a flat band state. Also, on the n-type Si semiconductor 12 side, the impurity concentration N
Since D is high, electrons are excited from the donor level in the conduction band to form majority carriers 14, and some positively ionized donors 15 exist in the donor level near the lower end Ec of the conduction band.

A second depletion layer is formed at the p-n junction 17 between the p-temperature Si semiconductor 1 and the n-board S1 semiconductor 12, and a potential barrier exists due to the work function difference between the two.

In this way, the minority carrier (electron) density on the pffisi semiconductor 1 side is sufficiently low, and the nWS1 semiconductor 12
In this state, the majority carriers (electrons) on the side cannot diffuse due to the presence of a potential barrier, so in this state the electrons are
! Nothing is injected into the membrane 2.

Next, when a positive pulse voltage with a small amplitude ° is rapidly applied to the At gate electrode 3 by a sweep of about 10 m5ec or less, the nozzle voltage is lower than that of the 5iO1 film 2, as shown in Figure (b). , the energy band slopes downward because it is applied to the first (16) and second depletion layers.

At this time, on the PffiSi semiconductor 1 side, as is well known, the time constant of electron induction at the surface is 0.1 to 1.0.
sec, so no inversion layer is formed due to accumulation of electrons. In addition, the holes 11 as majority carriers are repelled to the second depletion layer side, and the first depletion layer 16
becomes wider. Then, since a weak sequential bias is applied to the pn junction 17, the width of the second depletion layer is slightly narrowed, the potential barrier is lowered somewhat, and a few electrons 14 are transferred to the pffiSi.
Although it diffuses into the semiconductor 1, the first depletion layer 16
Since the electric field strength within the 5IO1 film 2 is weak and almost no avalanche occurs at the surface, electrons are not injected into the 5IO1 film 2 as desired.

When a higher pulse voltage is applied, 51
The voltage drop increases in the 01 film 2 and the first (16) and second depletion layers, and the energy band tilts further downward as shown in FIG. In this case, p ust semiconductor 1
On the side, the first depletion layer 16 forms a p-n junction 17
The energy band also bends to this junction. The majority carrier holes 11 diffuse into the n-type S1 semiconductor 12 over the potential barrier on the valence band side, which is lowered by forward bias. Note that in this state, p-type and nl
Since the p-n junction 17 is maintained due to the difference in the energy distribution occupied by electrons on the semiconductor 1° 12 side, the first depletion layer 16 does not extend beyond this.

Therefore, the width of the first depletion layer 16 is a constant width of about 1 to 3 μm in the film thickness of the pffiSi semiconductor 1, and it will not widen to the extent that anoranciers occur as in the conventional example explained in FIG. Therefore, a constant high electric field strength is maintained within the first depletion layer 16.

Furthermore, on the n-type Si semiconductor 12 side, a forward bias is further applied to the p-n junction 17 and the potential barrier is lowered, so the majority carrier electrons 14 pass through this to the p-type Si semiconductor 12.
It diffuses into the semiconductor 1.

These diffused electrons are accelerated by the high electric field in the first depletion layer 16, cause collision ionization with electrons in the valence band, and generate anoranciers at the surface, so that a large number of electrons are
in, injected into the membrane 2. Then, some of the injected electrons are captured by traps, and the traps are negatively ionized and become space charges.

As described above, when applying a pulse voltage approximately equal to the breakdown voltage, the spread of the first depletion layer 16 is limited to approximately the thickness of the thin p-Si semiconductor 1.
A constant voltage is applied to 6, and the remaining voltage is sio, membrane 2,
and is added to the second depletion layer.

Therefore, according to this embodiment, a high electric field strength is maintained within the PUSI semiconductor 1, and the majority carrier electrons 14 are easily diffused from the lower layer NP semiconductor 12. It does not require as high a voltage as in the case of , and Ano-Rancier injection can be performed stably.

The above-mentioned avalanche injection of electrons is carried out using the evaluation test apparatus shown in FIG. and generate this in MI
This is done by applying voltage to the S capacitor. In the characteristic measurement after implantation, in order to make the sample into a normal MIS capacitor structure, an ohmic electrode made of red was used as a substitute for the electrode terminal of the n-type S1 semiconductor in the lower layer of the Sl substrate, which was used when applying one pulse voltage. The changeover switches 4 and 16 are respectively connected to the B terminal side so that the opposite electrode 13 side of the contact becomes the measurement terminal, and a closed circuit between the capacitance measuring device 6 and the voltage source 7 is formed. Then, the C-■ characteristic of this MIS capacitor is measured, and the amount of change in space charge due to ionized traps is determined from the amount of voltage fluctuation of the characteristic curve.
Trap sealing in the insulator film 2-nork consisting of the sto film and the sto film is evaluated.

In this example, the p-board S in the upper layer of the Si substrate part is
1 The case where the impurity concentration of the semiconductor 1 is low impurity concentration of about I can also be applied. That is,
As mentioned above, when the impurity concentration is high, the spread of the depletion layer on the pffisi semiconductor side becomes narrower when a pulse voltage is applied.
By forming the layer thin enough to suppress the spread of the depletion layer,
Ano-Rancier implantation can be performed with a lower Norse voltage than conventional methods.

In this case, it is desirable that the impurity concentration of the lower layer n-Si semiconductor is higher than that of the upper layer pffisi semiconductor.

When injecting holes into the insulator film, the MIS canister reverses the stacking positional relationship of the p-type Si semiconductor and the nWsi semiconductor, and also increases the impurity concentration of the lower p-star Sl semiconductor to be lower than that of the upper layer. In addition, it is necessary to apply a negative voltage to the metal gate electrode.

Note that in this case, the traps are positively ionized by hole injection.

Furthermore, as the insulating film for the MIS canister, the above-mentioned Si0. Of course, in addition to the film, an insulating film such as a Si sN4 film can also be applied.

〔Effect of the invention〕

As described in detail above, in this invention, since a p-n junction is formed in the Sl semiconductor of the MIS capacitor as the evaluation sample, when a pulse voltage is rapidly applied during avalanche injection of carriers, the upper layer 8i semiconductor The depletion layer (first depletion layer) formed on the surface of (pm) is
Since it spreads to the -n junction and has a constant width, a high electric field is maintained within this depletion layer. Therefore, when applying a pulse voltage,
When using a Si semiconductor with a low impurity concentration (approximately I x 10"/cd or less), which has the characteristic of greatly expanding the depletion layer width, it is possible to use a low Norse voltage, and also to avoid the problem of the peripheral area of the electrode, which has been a problem in the past. This has the effect that the effect is sufficiently suppressed and stable carrier injection can be performed using Ano9 Rancier.

Furthermore, in the present invention, unlike the conventional method which relies on minority carriers, the carriers contributing to the impact ionization effect of the avalanche 5 are majority carriers (which diffuse from the lower layer Sl semiconductor (n-type) by forward bias). When a nozzle voltage is applied to the MIS canister, the spread of the depletion layer is small and medium to high impurity concentration (t x i
When using an O8i semiconductor (approximately Coupled with the fact that the layer width is kept constant, the effect of collision ionization of carriers becomes greater, so there is also the effect that avalanche injection can be performed with a lower pulse voltage than in the conventional method.

[Brief explanation of the drawing]

FIG. 1(jL) is a cross-sectional view showing the configuration of an evaluation sample according to the present invention, FIG. 1(b) is a schematic diagram showing the configuration of a similar evaluation test device, and FIG. Energy band diagrams explaining each process of injection; Figure 3-) is a sectional view showing the configuration of a sample for evaluation in the conventional method; Figures 3-) are schematic diagrams showing the configuration of a similar evaluation test device; The figure is an energy band diagram explaining each process of similar avalanche injection, and Figure 5 shows the Si of the evaluation sample in the same conventional method.
FIG. 3 is a substrate (p-type) depletion layer width-pulse voltage characteristic diagram. 1...p-type S1 semiconductor, 2...insulator film (Slat
), 3...metal gate electrode (AA), 4,16...
Selector switch, 5... Rezorus generator, 6...
Capacitance measuring device, 7... Voltage source, 9... Trap,
10...Acceptor in p-type Si semiconductor, 11...
Majority carriers (holes) in p-type Sl semiconductor, 12...
n-type Si semiconductor, 13... counter electrode (At), 14.
...Majority carriers (electrons) in n-type Si semiconductor, 15.
... Donor in n-type Si semiconductor, 16... Depletion layer (first
depletion layer), 17...p-n junction section. Patent applicant Oki Electric Industry Co., Ltd. Figure 1 Figure 3 ji! 4fi Pulse voltage (v) Ishiba coming) Yun 1 Reike SSi Jin 4 and (? da) Shi Mimayoki's Hawasis voltage dependence No. 9 is Figure e Figure 5 Procedural amendment July 18, 1985 Japan Patent Office Commissioner's Office Ill Shizumasu-dono 1, Indication of the case 1985 Patent Application No. 142591 2, Name of the invention Method for evaluating semiconductor devices & Relationship with the person making the amendment Patent Applicant (029) Oki Electric Kogyo Co., Ltd. 4, Agent 5, Date of amendment order: Showa, Month, Day (Voluntary) 6, Corrected to ``Silicole nitride film'' subject of amendment.

Claims (1)

[Claims] (1) In a method for evaluating a semiconductor device having an MIS structure, (a) an insulator film having a laminated structure on the upper surface of either a p-type Si semiconductor or an n-type Si semiconductor forming a p-n junction; and a step of applying a pulse voltage to the metal gate electrode of the MIS capacitor formed by forming a metal gate electrode and a counter electrode so as to provide a forward bias to the p-n junction; (b) by applying the pulse voltage; The depletion layer formed on the surface of the upper Si semiconductor is expanded to the p-n junction, and the majority carriers of the lower Si semiconductor are diffused through the potential barrier of the p-n junction to cause avalanche. death,
Injecting carriers into the insulator film to ionize traps in the insulator film; (c) After the carrier injection by the avalanche, the metal gate electrode and the counter electrode are used as measurement terminal electrodes, and the ionization A method for evaluating a semiconductor device, comprising the step of measuring the trapped amount as an amount of charge change in the insulating film, and evaluating the amount of traps in the insulating film.