JPS6243229B2 - - Google Patents

Info

Publication number
JPS6243229B2
JPS6243229B2 JP56040801A JP4080181A JPS6243229B2 JP S6243229 B2 JPS6243229 B2 JP S6243229B2 JP 56040801 A JP56040801 A JP 56040801A JP 4080181 A JP4080181 A JP 4080181A JP S6243229 B2 JPS6243229 B2 JP S6243229B2
Authority
JP
Japan
Prior art keywords
data
register
ram
cpu
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56040801A
Other languages
Japanese (ja)
Other versions
JPS57155656A (en
Inventor
Joji Murakami
Takeshi Watabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56040801A priority Critical patent/JPS57155656A/en
Priority to DE8282301445T priority patent/DE3273507D1/en
Priority to EP82301445A priority patent/EP0062431B1/en
Priority to US06/359,818 priority patent/US4467420A/en
Priority to IE662/82A priority patent/IE53423B1/en
Publication of JPS57155656A publication Critical patent/JPS57155656A/en
Publication of JPS6243229B2 publication Critical patent/JPS6243229B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/786Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers) using a single memory module

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Microcomputers (AREA)
  • Debugging And Monitoring (AREA)

Description

【発明の詳細な説明】 本発明は、メモリの内容を外部から簡単にチエ
ツクできるようにしたワンチツプマイクロコンピ
ユータに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a one-chip microcomputer in which the contents of a memory can be easily checked from the outside.

周知のように電子計算機は中央処理装置
(CPU)、命令や処理データを記憶するメモリ、
および入出力装置(I/O)を基本構成要素とし
ている。1970年代初頭のインテル社4004等のプロ
セツサにより始つた所謂マイクロコンピユータも
その例外ではないが、マイクロコンピユータと称
されるデバイスは非常に少数の主としてシリコン
MOS LSIにより構成されている点が特徴となつ
ている。そしてLSIの集積度向上により、マイク
ロコンピユータ出現の当初はCPUの機能を1つ
の半導体チツプ上に実現したものをマイクロプロ
セツサ又はマイクロコンピユータと称していたの
に対し、現在ではRAM,ROMなどのメモリや更
にI/O制御部分も同一チツプ上に実現されるよ
うになつている。かゝる機能の集積化により簡単
な情報処理システムなら、1つ又は少数のLSIと
若干の外付け部品により構成可能となり、著しい
コスト/性能の増大が図られるが、その一方では
設計、試験、使用面で色々な問題も生じている。
As is well known, an electronic computer consists of a central processing unit (CPU), memory that stores instructions and processing data,
The basic components are input/output devices (I/O). The so-called microcomputers that started with processors such as Intel's 4004 in the early 1970s are no exception, but there are very few devices that are called microcomputers, and they are mainly silicon-based.
Its distinctive feature is that it is constructed using MOS LSI. With the increase in the integration of LSIs, when microcomputers first appeared, a device that implemented the functions of a CPU on a single semiconductor chip was called a microprocessor or microcomputer, but today it has become possible to use memory such as RAM or ROM. Furthermore, the I/O control section is now being implemented on the same chip. Due to the integration of such functions, a simple information processing system can be configured with one or a few LSIs and a few external components, resulting in a significant increase in cost and performance. Various problems have arisen in terms of use.

その1つの問題点はデータ転送である。上述の
ようにICの集積度の向上によりCPU部分とその
処理データ等を格納するRAM部分が同一チツプ
上に搭載される場合が多く、しかもそのRAMの
記憶容量が大になつてくると、該RAMへデータ
を入、出力したいという要求が出てくる。例えば
該RAMと外部のI/O間のデータ授受、該RAM
のある部分チエツクしてマイクロコンピユータの
動作を監視する、等がそれである。
One problem is data transfer. As mentioned above, due to the improvement in IC integration, the CPU part and the RAM part that stores processing data, etc. are often mounted on the same chip, and as the storage capacity of the RAM increases, A request arises to input and output data to RAM. For example, data exchange between the RAM and external I/O, the RAM
Examples include monitoring the operation of a microcomputer by checking a certain part of it.

RAM内容を外部へ取出す又は外部からRAMへ
データを書込むことは、CPUを介してなら現在
の装置でも何ら改変することなく実行できる。し
かしこの方法ではCPUに大きな負担を負わせる
ことになり、スループツトが悪くなる。また
RAMを内蔵しているマイクロコンピユータは命
令シーケンス(プログラム)をROMに内蔵して
いる場合が多く、外部からはチツプの動作状態が
分らず、制御困難という問題もある。これらは、
CPUを介さずにメモリとI/Oとの間でデータ
授受を行なうDMA方式をとると改善できる。し
かしDMA方式では一般にコモンバスを利用した
並列転送方式をとるが、マイクロコンピユータで
かゝる方式をとると多数の(データをバイト単位
で送るならデータ転送用だけでも8個の)端子ピ
ンを必要とするので問題である。しかもデバツグ
目的でRAM内容を外部へ取出すような場合は開
発が済んで量産に移る時点ではこれらのDMA用
端子ピン群は不要となつてしまう。
Extracting the contents of RAM to the outside or writing data to RAM from the outside can be performed with current devices without any modification if the CPU is used. However, this method places a heavy burden on the CPU, resulting in poor throughput. Also
Microcomputers with built-in RAM often have instruction sequences (programs) built into the ROM, making it difficult to control the operating state of the chip because it is difficult to tell from the outside. these are,
This can be improved by using a DMA method that exchanges data between memory and I/O without going through the CPU. However, the DMA method generally uses a parallel transfer method using a common bus, but if such a method is used in a microcomputer, a large number of terminal pins (eight for data transfer alone if data is sent in bytes) are required. This is a problem. Moreover, if the contents of the RAM are to be exported for debugging purposes, these DMA terminal pins will become unnecessary when development is completed and mass production begins.

本発明はかゝる点に鑑みてなされたもので、
CPUに負担をかけず、少数の端子ピン使用で済
んで簡単にRAM内容を外部へ取出せる方式を案
出した。即ち本発明は半導体チツプに中央処理装
置およびランダムアクセスメモリを搭載したワン
チツプマイクロコンピユータにおいて、該チツプ
にレジスタおよびその制御装置を設けて該レジス
タへも、中央処理装置がランダムアクセスメモリ
に書込む所定の種類のデータを書込むようにし、
そして中央処理装置が該制御装置に信号を送ると
き該制御装置が該レジスタの内容を外部へ逐次直
列伝送させるようにしてなることを特徴とする
が、次に実施例を参照しながらこれを説明する。
The present invention has been made in view of the above points, and
We devised a method that allows the contents of RAM to be easily exported externally without placing any burden on the CPU and using a small number of terminal pins. That is, the present invention provides a one-chip microcomputer in which a central processing unit and a random access memory are mounted on a semiconductor chip. write the type of data,
The present invention is characterized in that when the central processing unit sends a signal to the control device, the control device sequentially and serially transmits the contents of the register to the outside.This will be explained below with reference to embodiments. do.

第1図は本発明の第1の実施例を示す。10は
半導体チツプであり、これにCPU12、RAM1
4、種々の機能回路16、CPUの処理内容等を
クロツクにより声分割的に送受するシリアルI/
O18、およびその送信レジスタ20などが搭載
されてマイクロコンピユータが構成される。本発
明ではRAM内容からCPUの動作等を監視するた
めに、該監視に好適なデータを書込むメモリ領域
14aをRAM14内に定め、また該メモリ領域
14aと同じデータを書込むレジスタ22および
その制御回路24を設ける。本例ではメモリ領域
14aの記憶容量は1バイト分とし、レジスタ2
2も同様に1バイト容量とする。CPUの機能チ
エツクにはこの程度の容量で間に合うことが多い
が、勿論該容量を2バイト、3バイト……など大
容量のものとしてもよい。
FIG. 1 shows a first embodiment of the invention. 10 is a semiconductor chip, which includes a CPU 12 and a RAM 1.
4. Various functional circuits 16, a serial I/I/
A microcomputer is configured by mounting the O18, its transmission register 20, and the like. In the present invention, in order to monitor the operation of the CPU from the RAM contents, a memory area 14a is defined in the RAM 14 in which data suitable for the monitoring is written, and a register 22 in which the same data as that of the memory area 14a is written and its control A circuit 24 is provided. In this example, the storage capacity of the memory area 14a is 1 byte, and the register 2
Similarly, 2 has a capacity of 1 byte. Although this amount of capacity is often sufficient for checking the functions of the CPU, it is of course possible to use a larger capacity such as 2 bytes, 3 bytes, etc.

この装置ではCPUが演算などを行なつてその
処理結果の予め選択された種類のものをRAM1
4の領域14aに書込むとき、当該データを制御
装置24を介してレジスタ22へも書込む。次の
上記種類のデータが領域14aに書込まれるとき
も同様であり、こうしてレジスタ22は常に更新
されて領域14aと同じ内容を保持する。上記種
類のデータを外部へ送出したいときCPUは制御
装置24へDMA(直接メモリアクセス)を指令
する信号を与え、該制御装置はレジスタ22の内
容を送信レジスタ20へ移し、かつシリアルI/
O18で使用するクロツクと同じクロツクでレジ
スタ22の内容を逐次読出し、外部へ直列伝達す
る。勿論この場合上記操作がレジスタ22への新
データ書込み及びシリアルI/Oから外部へのデ
ータ送出とかち合つてはならないが、かゝるタイ
ミングの制御はCPUが行なう。
In this device, the CPU performs arithmetic operations, and the preselected types of the processing results are stored in the RAM 1.
When writing to the area 14a of No. 4, the data is also written to the register 22 via the control device 24. The same holds true when the next type of data is written to area 14a, and thus register 22 is constantly updated to hold the same contents as area 14a. When it is desired to send the above type of data to the outside, the CPU gives a signal instructing DMA (direct memory access) to the control device 24, and the control device transfers the contents of the register 22 to the transmission register 20, and also transfers the contents of the register 22 to the transmit register 20, and
The contents of the register 22 are sequentially read out using the same clock as used in O18 and serially transmitted to the outside. Of course, in this case, the above operation must not coincide with writing new data to the register 22 and sending data from the serial I/O to the outside, but the CPU controls such timing.

この方式によればCPUは制御装置24へDMA
指令を与えるだけでRAM特定領域の記憶内容の
外部への送出が可能となり、逐次RAMを読出す
などの操作は不必要なのでCPU負担が増加せ
ず、また迅速なデータ送出が可能となる。使用端
子ピン数は直列伝送なので1つで済み、しかもシ
リアルI/Oが設けられる場合はそのデータ送受
用の端子ピンを利用でき、好都合である。プログ
ラムをデバツグする目的でRAM内容を読出す場
合は当該LSIの開発段階が終了して量産に入ると
レジスタ22および制御装置は不要となる。従つ
てこれらは機能停止させてもよいが、勿論残存さ
せてもよく、この場合は稼動中などのLSIの機能
チエツクに利用できる。
According to this method, the CPU sends DMA to the control device 24.
It is possible to send the stored contents of a specific RAM area to the outside by simply giving a command, and since operations such as sequentially reading RAM are not required, the CPU load does not increase and data can be sent quickly. Since serial transmission is used, only one terminal pin is required, and if a serial I/O is provided, the terminal pin for data transmission and reception can be used, which is convenient. When reading the contents of the RAM for the purpose of debugging a program, the register 22 and the control device become unnecessary once the development stage of the LSI is completed and mass production begins. Therefore, although these may be disabled, they may of course be allowed to remain, in which case they can be used to check the functionality of the LSI while it is in operation.

第2図は本発明の第2の実施例を示す。第1図
ではRAM14内の特定の1ないし複数バイトの
データを外部へ取出すようにしたが、第2図では
8個またはその整数倍のデータ群の先頭ビツトの
みを外部へ取出すようにする。レジスタ22の記
憶容量は従つてやはり1ないし複数バイト分であ
り、CPU12はRAM14へ予め選択された種類
のデータを書込む毎にその先頭1ビツトを領域1
4aへ書込むと共にレジスタ22へも書込む。こ
の結果レジスタ22の内容はRAM14の先頭ビ
ツト記憶領域14aの内容と同じになり、常に更
新されている。読出しは第1図と同様で、CPU
12が制御装置24へDMA指令を与えることに
より行なう。データの先頭ビツトは当該データの
種類などを示しているものがあり、これらを監視
すればCPU等の機能監視が行なえる。
FIG. 2 shows a second embodiment of the invention. In FIG. 1, one or more specific bytes of data in the RAM 14 are taken out to the outside, but in FIG. 2, only the first bit of a data group of 8 or an integral multiple thereof is taken out to the outside. The storage capacity of the register 22 is therefore one or more bytes, and each time the CPU 12 writes a preselected type of data to the RAM 14, the first bit is stored in area 1.
4a and also writes to the register 22. As a result, the contents of the register 22 become the same as the contents of the first bit storage area 14a of the RAM 14, and are constantly updated. Reading is the same as in Figure 1, and the CPU
12 issues a DMA command to the control device 24. The first bit of data may indicate the type of data, and by monitoring these, it is possible to monitor the functions of the CPU, etc.

RAM14内の多数のデータ群を外部へ送出す
るには第3図に示すようにRAM14から読出し
ながら送出する様にすれば、大容量のシフトレジ
スタ22を必要としないが、この場合はRAM1
4の領域14aを読出すためのアドレスカウンタ
26、RAM14に対するCPU12からのアクセ
スとアドレスカウンタ26によるアクセスとの競
合を避けるための制御回路28が必要になる。な
お30は20と同種の送信用レジスタで、領域1
4aのデータ送出用である。
In order to send a large number of data groups in the RAM 14 to the outside, it is possible to read them from the RAM 14 while sending them out as shown in FIG. 3, which eliminates the need for a large capacity shift register 22.
An address counter 26 for reading out the area 14a of No. 4, and a control circuit 28 for avoiding conflict between accesses from the CPU 12 to the RAM 14 and accesses by the address counter 26 are required. Note that 30 is the same type of transmission register as 20, and is in area 1.
This is for data transmission of 4a.

以上説明したように本発明によればワンチツプ
マイクロコンピユータのRAMの特定データを、
CPUを煩わさずに、そして多数の端子ピンなど
を要することなく外部へ送出することができ、甚
だ有効である。
As explained above, according to the present invention, specific data in the RAM of a one-chip microcomputer can be
It is extremely effective because it can be sent to the outside without bothering the CPU or requiring a large number of terminal pins.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は本発明の実施例を説明す
る図、第3図は考えられる他の例を示す説明図で
ある。 図面で10は半導体チツプ、12は中央処理装
置、14はランダムアクセスメモリ、22はレジ
スタ、24はその制御装置である。
FIG. 1 and FIG. 2 are diagrams for explaining an embodiment of the present invention, and FIG. 3 is a diagram for explaining another possible example. In the drawing, 10 is a semiconductor chip, 12 is a central processing unit, 14 is a random access memory, 22 is a register, and 24 is its control unit.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体チツプに中央処理装置およびランダム
アクセスメモリを搭載したワンチツプマイクロコ
ンピユータにおいて、該チツプにレジスタおよび
その制御装置を設けて該レジスタへも、中央処理
装置がランダムアクセスメモリに書込む所定の種
類のデータを書込むようにし、そして中央処理装
置が該制御装置に信号を送るとき該制御装置が該
レジスタの内容を外部へ逐次直列伝送させるよう
にしてなることを特徴とするワンチツプマイクロ
コンピユータ。
1. In a one-chip microcomputer in which a central processing unit and a random access memory are mounted on a semiconductor chip, the chip is provided with a register and its control device, and the register is also used to store a predetermined type of information that the central processing unit writes to the random access memory. A one-chip microcomputer characterized in that data is written and when the central processing unit sends a signal to the control device, the control device serially transmits the contents of the register to the outside.
JP56040801A 1981-03-20 1981-03-20 One-chip microcomputer Granted JPS57155656A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP56040801A JPS57155656A (en) 1981-03-20 1981-03-20 One-chip microcomputer
DE8282301445T DE3273507D1 (en) 1981-03-20 1982-03-19 A one chip microcomputer
EP82301445A EP0062431B1 (en) 1981-03-20 1982-03-19 A one chip microcomputer
US06/359,818 US4467420A (en) 1981-03-20 1982-03-19 One-chip microcomputer
IE662/82A IE53423B1 (en) 1981-03-20 1982-03-22 A one chip microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56040801A JPS57155656A (en) 1981-03-20 1981-03-20 One-chip microcomputer

Publications (2)

Publication Number Publication Date
JPS57155656A JPS57155656A (en) 1982-09-25
JPS6243229B2 true JPS6243229B2 (en) 1987-09-11

Family

ID=12590728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56040801A Granted JPS57155656A (en) 1981-03-20 1981-03-20 One-chip microcomputer

Country Status (1)

Country Link
JP (1) JPS57155656A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57182855A (en) * 1981-05-07 1982-11-10 Toshiba Corp Operation confirming system for one-chip microcomputer

Also Published As

Publication number Publication date
JPS57155656A (en) 1982-09-25

Similar Documents

Publication Publication Date Title
US4099236A (en) Slave microprocessor for operation with a master microprocessor and a direct memory access controller
US4698753A (en) Multiprocessor interface device
US5761458A (en) Intelligent bus bridge for input/output subsystems in a computer system
KR102413593B1 (en) Methods and circuits for deadlock avoidance
EP1196842A1 (en) Methods and apparatus for combining a plurality of memory access transactions
US5903912A (en) Microcontroller configured to convey data corresponding to internal memory accesses externally
US7434103B2 (en) Program processing device
US5168559A (en) Emulation system capable of complying with microcomputers having different on-chip memory capacities
US4479178A (en) Quadruply time-multiplex information bus
EP0026648B1 (en) Digital data transfer apparatus
EP0522582A2 (en) Memory sharing for communication between processors
US6742142B2 (en) Emulator, a data processing system including an emulator, and method of emulation for testing a system
JPS6243229B2 (en)
CN101169767B (en) Access control device and access control method
JPH03668B2 (en)
KR100223096B1 (en) Method and apparatus for observing internal memory-mapped registers
JPH0227696B2 (en) JOHOSHORISOCHI
EP0117837B1 (en) User programmable bus configuration for microcomputers
JP2020140380A (en) Semiconductor device and debugging system
JP2819329B2 (en) Program storage device
JP2001236305A (en) Semiconductor integrated circuit and data processor
JP2558902B2 (en) Semiconductor integrated circuit device
JPS6014435B2 (en) Storage device
JP2928036B2 (en) Logic semiconductor integrated circuit
JP2000076199A (en) Multiprocessor device provided with debugging terminal