JPS6242528B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention provides automatic gain control (hereinafter referred to as this invention) in an amplitude locked detection device using a phase locked loop.
The purpose of the present invention is to eliminate unstable operation of the device, especially when the phase-locked loop is out of synchronization. AGC in a video intermediate frequency (hereinafter abbreviated as VIF) circuit of a television receiver will be explained below as an example.

FIG. 1, which shows a conventional example, shows that a variable gain VIF amplifier 1 and a synchronous detector 2 to which this output and a carrier wave CW are supplied are connected in cascade. The AGC voltage generation circuit (hereinafter abbreviated as AGC circuit) includes a first low-pass filter LPF 3 for removing high frequency components in the output signal of the synchronous detector 2;
It consists of an AGC detector 4 and a second low-pass filter 5 for obtaining the DC AGC voltage.
By controlling the gain of the VIF amplifier 1, the input or output signal level of the synchronous detector 2 is made constant, and this configuration is usually used in many receivers. In a normal radio receiver, the first low-pass filter 3 is used to prevent thermal noise generated when receiving a weak signal from causing malfunction of the AGC circuit. It also has the function of preventing the AGC circuit from malfunctioning due to the intercarrier audio signal (4.5MHz beat signal in Japan) generated at the output terminal of device 2. In a conventional device with such a configuration, when the input signal supplied to the synchronous detector 2 and the carrier wave no longer maintain a predetermined phase relationship (a relative phase difference of π/2 rad), in other words, When the phase-locked loop becomes asynchronous, the beat signal generated at the output terminal of the synchronous detector 2 is attenuated by the first low-pass filter 3, so the AGC circuit is connected to the VIF amplifier 1. The operation is performed to increase the gain. Such an increase in the gain of the VIF amplifier becomes larger as the frequency of the beat signal becomes higher, and may bring the VIF amplifier 1 or the synchronous detector 2 into an unstable region, which causes the increase in the gain of the low-pass filter 3. There was a drawback that the constant could not be made large enough.

The AGC circuit according to the present invention has a beat detection circuit 6 placed on the output side of the synchronous detector 2, as shown in FIG.
a first low-pass filter 3 constituting the AGC circuit 7;
It has a configuration in which either the AGC detector 4, the second low-pass filter 5, etc. is controlled individually, or a plurality of them are controlled in parallel. In a special application of this invention, it is possible to directly control the AGC circuit with the pulse signal that can be obtained from the beat detection circuit described above. Each embodiment will be described below based on the drawings.

In FIG. 3, the beat detection circuit 6 is composed of a beat detector 8 and a low-pass filter 9, and its output is
This configuration is such that the input end and output end of the low-pass filter 3 of the AGC circuit 7 are short-circuited. The beat detector 8 compares the reference voltage with the output signal of the synchronous detector in order to detect beats in the white direction that exceed the zero carrier level of the input signal in an amplitude-separated manner.The details of this operation are provided by the applicant. Unexamined Japanese Patent Publication 1973-
This is also shown in Publication No. 78153. A low-pass filter 9 converts the output of the beat detector 8 into a DC signal,
Switch connected between input and output of low-pass filter 3
Open/close SW. When the aforementioned phase-locked loop is in a synchronous state, the beat detector 8 is cut off by the reference voltage, so that the switch SW remains open. In this state, all components that are undesirable for the AGC circuit, such as thermal noise and intercarrier audio signals, are removed from the input signal of the AGC detector 4 by the low-pass filter 3, so when receiving a weak signal, The AGC circuit 7 also operates normally.

On the other hand, when the phase-locked loop becomes asynchronous, the DC voltage generated at the output terminal of the low-pass filter 9 is switched
Short-circuit SW. In this state, the low-pass filter 3 no longer has a filtering effect, so that the AGC circuit 7 has a wide band. Therefore, AGC circuit 7 is AGC detector 4
The synchronous detector 2 operates so that the peak level is constant regardless of the state of the input signal (beat or not) or the frequency of the beat signal.
Alternatively, the VIF amplifier 1 is prevented from receiving excessive input and bringing the device into an unstable region. In the configuration of the above embodiment, the characteristics of the low-pass filter 3 do not require any consideration for the beat signal generated when the phase-locked loop is in an asynchronous state, so the AGC circuit 7 is always operated in an optimal state. Constants can be set.

In the embodiment shown in FIG. 4, like the one in FIG. 3, the beat detection circuit 6 is composed of a beat detector 8 and a low-pass filter 9, and its output is used to detect the reference DC voltage of the AGC detector 4. It is something to control. normal condition,
That is, when the phase-locked loop is in a synchronous state, no DC voltage is generated at the output of the low-pass filter 9, so the AGC detector 4 has a normal detection function. On the other hand, the beat signal generated at the output of the synchronous detector 2 is converted into a DC voltage by the low-pass filter 9, where the beat detector 8 in the embodiment shown in FIG.
The activation level of is selected under somewhat different conditions than in FIG. That is, in the embodiment shown in FIG. 3, the beat detector 8 uses a reference voltage near the zero carrier level in order to detect the presence or absence of a signal component in the white direction that exceeds the zero carrier level in the signal output from the synchronous detector 2. In contrast, in the embodiment of FIG. 4, the zero carrier level is used as shown in FIG.
When V ₀ and the peak level of the synchronizing signal in the black direction are V ₂ , the reference voltage V ₁ of the beat detector 8 is set to V ₁ ≦V ₂ +2 (V ₀ −V ₂ ). Therefore, under operating conditions where the frequency of the beat signal is low and there is no attenuation by the low-pass filter 3, the AGC detector 4 operates to keep the black synchronization signal peak level _V2 constant. Therefore, the peak level of the synchronization signal in the white direction of the beat signal supplied to the beat detector 8 is V ₂ +2 (V ₀ −
V ₂ ), so the beat detector 8 essentially maintains a cut-off state for the input beat signal that is approximately equal to the reference voltage, so the output of the low-pass filter 9
No signal is generated to control the AGC detector 4. Next, when the beat signal reaches a high frequency that is attenuated by the low-pass filter 3, the amplitude of the beat signal increases corresponding to the amount of attenuation by the low-pass filter 3, so the beat signal Detector 8 begins its operation. The output of the beat detector 8, which is converted into a DC voltage by the low-pass filter 9, changes in accordance with the beat frequency, which exactly corresponds to the frequency characteristics of the low-pass filter 3. On the other hand, by changing the reference DC voltage of the AGC detector 4 in the direction of decreasing the amplitude of the beat signal output from the low-pass filter 9, the amplitude of the beat signal output from the synchronous detector 2 is kept constant regardless of its frequency. It can be done. For example, low-pass filter 3
has an attenuation of 6 dB at beat frequency ₁ , the reference DC level of the AGC detector 4 is changed to reduce the input or output level of the synchronous detector 2 by 6 dB, and the control operation is linear. Just set it.

Next, a third embodiment of the present invention will be described with reference to FIG. This embodiment shows that the low-pass filter 5 is controlled by the output of the beat detection circuit 6.
The low-pass filter 5 converts the output of the AGC detector 4 into a DC voltage, and usually includes a smoothing capacitor. Since the beat detector 8 sets the reference DC voltage under the same conditions as explained in FIG. 4, the output DC voltage of the beat detection circuit 6 in this application also corresponds accurately to the frequency characteristics of the low-pass filter 3. do.

Now, the so-called reverse AGC in which the gain of VIF amplifier 1 increases when the output of low-pass filter 5 increases
Assuming that, when the output of the beat detection circuit 6 is controlled to discharge the charge of the smoothing capacitor of the low-pass filter 5, the operation of the AGC circuit 7 is changed to correct the discharge of the charge. i.e.
The discharged charge is compensated for by reducing the amplitude of the beat signal at the input of the AGC detector 4, which equivalently means reducing the beat signal at the output of the synchronous detector. The control of the low-pass filter 5 is also set to perform linear operation as in FIG. 4, and by appropriately selecting the control amount, the amplitude can be made constant regardless of the frequency of the beat.

In the embodiment shown in FIG. 5, the beat detection circuit 6 includes a low-pass filter 9, but it can also be directly controlled by the output of the beat detector 8 as shown in FIG. In this case, since the output of the beat detector 8 becomes a pulse signal, when this signal is used, the discharging operation of the smoothing capacitor is performed intermittently. Therefore, by setting the integral value to be the same as in the embodiment shown in FIG. 5, the amplitude of the beat signal can be made constant regardless of its frequency as in FIG. 5.

As described above, in the AGC device according to the present invention configured to control the AGC voltage generation circuit with the output of the beat detection circuit, the input signal level of the synchronous detector can be substantially controlled regardless of whether the phase-locked loop is synchronous or asynchronous. Since it can be kept constant, it is possible to always keep the operation of the device in a stable range. Therefore, the performance of the low-pass filter can be improved,
Since all undesirable noise and signal components can be sufficiently removed from the signal supplied to the AGC detector, the performance of the AGC device can be further improved, which has great effects.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional AGC device.
FIG. 2 is a block diagram showing the basic configuration of an AGC device according to the present invention, and FIGS. 3, 4, 5, and 6 are block diagrams showing one embodiment of the present invention, respectively.
FIG. 7 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 4. 1...VIF amplifier, 2...synchronous detector, 3...low-pass filter, 4...AGC detector, 5...low-pass filter, 6...
Beat detection circuit, 7...AGC circuit, 8...beat detector, 9...low-pass filter.

Claims (1)

[Claims] 1. An amplitude locked detector using a phase locked loop;
an AGC voltage generation circuit for maintaining the output level of the amplitude synchronous detector at a predetermined value; and an AGC voltage generation circuit arranged on the output side of the amplitude synchronous detector, which has a detection polarity substantially different from the detection polarity of the amplitude synchronous detector. and a beat detection circuit for controlling the AGC voltage generation circuit, the AGC voltage generation circuit having a first low-pass filter to which the output of the amplitude synchronous detector is supplied, and the output thereof as input. An AGC device comprising an AGC detector and a second low-pass filter to which the detected output is applied. 2. The beat detection circuit includes a beat detector coupled to the output of an amplitude synchronous detector and a third low-pass filter disposed on the output side of the beat detector,
2. The AGC device according to claim 1, wherein the control output of the third low-pass filter makes the signal pass band of the first low-pass filter wide. 3. The beat detection circuit includes a beat detector coupled to the output of an amplitude synchronous detector and a third low-pass filter disposed on the output side of the beat detector,
The AGC according to claim 1, wherein the reference DC voltage of the AGC detector is controlled by the output of the third low-pass filter, and the output signal level of the amplitude synchronous detector is reduced. Device. 4. The beat detection circuit includes a beat detector coupled to the output of the amplitude synchronous detector and a third low-pass filter disposed on the output side of the detector, and the third low-pass filter The AGC device according to claim 1, wherein the output DC voltage of the second low-pass filter is controlled by the output of the filter to reduce the output signal level of the amplitude synchronous detector. . 5. The beat detection circuit is comprised of a beat detector coupled to an output end of an amplitude synchronous detector, and the output DC voltage of the second low-pass filter is controlled by the output of the beat detector. An AGC device according to claim 1.