JPS6241453Y2 - - Google Patents

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Publication number
JPS6241453Y2
JPS6241453Y2 JP1980138471U JP13847180U JPS6241453Y2 JP S6241453 Y2 JPS6241453 Y2 JP S6241453Y2 JP 1980138471 U JP1980138471 U JP 1980138471U JP 13847180 U JP13847180 U JP 13847180U JP S6241453 Y2 JPS6241453 Y2 JP S6241453Y2
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Japan
Prior art keywords
resistor
input
positive
voltage
amplifier
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Expired
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JP1980138471U
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Japanese (ja)
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JPS5760415U (en
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Priority to JP1980138471U priority Critical patent/JPS6241453Y2/ja
Publication of JPS5760415U publication Critical patent/JPS5760415U/ja
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Publication of JPS6241453Y2 publication Critical patent/JPS6241453Y2/ja
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  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Description

【考案の詳細な説明】 本考案は不感帯発生回路の改良に関する。[Detailed explanation of the idea] The present invention relates to an improvement of a dead zone generating circuit.

一般に不感帯発生回路は、第1図に示すように
ある領域NSでは入力電圧VINに対し出力電圧VO
が零となり、前記領域NS以外のとき入力電圧VI
に対し出力電圧VOが入力電圧に比例して出力す
る関係を有する回路であつて、従来、この種回路
として、第2図のようなダイオード構成のもの
と、第3図のような演算増幅器を用いたものとが
ある。
In general, a dead zone generating circuit has an output voltage V O with respect to an input voltage V IN in a certain region NS as shown in Fig. 1.
becomes zero and the input voltage V I is outside the above region NS
This is a circuit in which the output voltage V O outputs in proportion to the input voltage with respect to N. Conventionally, this type of circuit has a diode configuration as shown in Figure 2, and a calculation type as shown in Figure 3. Some use an amplifier.

第2図の不感帯発生回路は、予め各ダイオード
D1〜D4に逆バイアス電圧を与えておくことによ
り、各ダイオードD1〜D4がオンとなる電圧に幅
をもたせ、かくして不感帯を形成する様になされ
ている。しかし、この種の不感帯発生回路は、そ
の回路素子としてのダイオードの特性に基因し
て、ダイオードの順方向降下電圧が温度に対して
依存性を有する為に温度依存性を有し、又各ダイ
オードの立上り特性がリニアではない為に、第4
図に示す如く、不感帯を脱するときの折点に於け
る立上り特性がなまることを避け得ない欠点を有
する。尚第4図に於て、折点の値はR/RB,R
/RB となり、リニア部分の勾配はR/R,R/Rとな
る。
The dead zone generation circuit in Figure 2
By applying a reverse bias voltage to D 1 to D 4 , the voltage at which each diode D 1 to D 4 is turned on has a width, thus forming a dead zone. However, this type of dead zone generation circuit has temperature dependence because the forward drop voltage of the diode is dependent on temperature due to the characteristics of the diode as a circuit element, and each diode has temperature dependence. Since the rise characteristic of is not linear, the fourth
As shown in the figure, the disadvantage is that the rise characteristics at the break point when exiting the dead zone are unavoidably blunted. In addition, in FIG. 4, the value of the break point is R 2 /R 1 V B ,R
4
/R 3 V B , and the slope of the linear portion becomes R/R 2 and R/R 4 .

この折点における立上り特性のなまりを改善し
たものが第3図に示す不感帯発生回路である。こ
の回路は正の入力電圧範囲を分担する第1の演算
増幅器A1と、負の入力電圧範囲を分担する第2
の演算増幅器A2と、これ等第1及び第2の演算
出力を加算する加算用演算増幅器A3とを有す
る。増幅器A1の入力端は正のバイアス電圧+VB
にてバイアスされ、これにより入力端子TINに正
の入力電圧VINが到来したとき、増幅器A1の入
力端に正の電圧が与えられることにより出力端に
負の電圧が生ずることを利用して増幅器A1の入
出力端間に並列に接続されたダイオードD1をオ
ン、出力端に直列に接続されたダイオードD2
オフとし、かくして増幅器A1の出力端の出力電
圧をOVとし、これに対して入力端子TINに負の
入力電圧が到来しかつバイアス電圧VBより大き
くなつたとき、ダイオードD1をオフ、ダイオー
ドD2をオンとし、かくして増幅器A1の出力端に
O=R/RIN−R/RBの正の電圧を出力する
様に なされている。
The dead zone generating circuit shown in FIG. 3 improves the roundness of the rise characteristic at this corner point. The circuit consists of a first operational amplifier A1 that shares the positive input voltage range and a second operational amplifier A1 that shares the negative input voltage range.
, and an addition operational amplifier A 3 for adding the first and second operational outputs. The input terminal of amplifier A1 has a positive bias voltage +V B
When a positive input voltage V IN arrives at the input terminal T IN , a positive voltage is applied to the input terminal of the amplifier A1 , and a negative voltage is generated at the output terminal. turns on the diode D 1 connected in parallel between the input and output terminals of the amplifier A 1 and turns off the diode D 2 connected in series to the output terminal, thus making the output voltage at the output terminal of the amplifier A 1 OV, On the other hand, when a negative input voltage arrives at the input terminal T IN and becomes greater than the bias voltage V B , the diode D 1 is turned off and the diode D 2 is turned on, thus causing V O to appear at the output terminal of the amplifier A 1 . It is designed to output a positive voltage of =R/ R1VIN - R/ R2VB .

一方増幅器A2は、入力端のバイアス電圧を−
Bとし、又増幅器A2に並列のダイオードD3及び
直列のダイオードD4の接続方向を増幅器A1の場
合とは逆にしたことを除いて、増幅器A1につい
ての構成と同様となされ、かくして入力端子TIN
に負の入力電圧が到来したとき増幅器A2の出力
端の出力電圧をOVとし、これに対して入力端子
INに正の入力電圧VINが到来しバイアス電圧V
Bより大きくなつたとき、増幅器A2の出力端にV
O=−(R/RIN−R/RB)の負の電圧を出力
する様 になされている。
On the other hand, amplifier A 2 has a bias voltage at the input terminal of -
V B , and the configuration is the same as that for the amplifier A 1 , except that the connection direction of the diode D 3 in parallel and the diode D 4 in series with the amplifier A 2 is reversed from that of the amplifier A 1 , Thus, the input terminal T IN
When a negative input voltage arrives at the input terminal, the output voltage at the output terminal of the amplifier A2 becomes OV, whereas a positive input voltage V IN arrives at the input terminal T IN , and the bias voltage V
When the voltage becomes larger than B , V is applied to the output terminal of amplifier A2 .
It is designed to output a negative voltage of O =-(R/ R3VIN - R/ R4VB ).

増幅器A1及びA2の演算出力は加算用演算増幅
器A3にて加算反転され、その結果増幅器A3の出
力端にて、第5図に示す如き不感帯特性を呈する
出力電圧VOが得られる。尚、第5図に於て、折
点の値は+R/RB,−R/RBとなり、リニア
部分の 勾配はR/R,R/Rとなるが、通常はR1=R2=R3
=R4 =Rに選択される。
The operational outputs of amplifiers A1 and A2 are added and inverted by addition operational amplifier A3 , and as a result, an output voltage V O exhibiting dead band characteristics as shown in FIG. 5 is obtained at the output terminal of amplifier A3 . . In Fig. 5, the values of the break points are +R/R 4 V B and -R/R 2 V B , and the gradients of the linear part are R/R 3 and R/R 1 , but normally R1 = R2 = R3
=R 4 =R is selected.

ところで第2図及び第3図に示す基本回路を有
する不感帯発生回路を実際の機器に応用しようと
する場合、その取扱い操作の点及び精度の点から
考えると、第1に不感帯幅の調整を入力電圧VIN
の正及び負の両方の範囲に共通の1個の調整素子
(例えば可変抵抗)によつてなし得る様にするこ
と、第2に高精度を必要とする場合は、儀性を保
持する為に必要な精密抵抗器の数を出来るだけ少
なくすることが不可欠である。
By the way, when trying to apply the dead zone generation circuit having the basic circuit shown in Figures 2 and 3 to actual equipment, from the viewpoint of handling operation and accuracy, the first step is to input the dead zone width adjustment. Voltage V IN
One adjustment element (for example, a variable resistor) common to both the positive and negative ranges of It is essential to minimize the number of precision resistors required.

第1の要求を満足させるべく従来は、第6図
(第2図に対応する)及び第7図(第3図に対応
する)に示す様な構成が採用されていた。しか
し、この構成に依れば、第2図及び3図の構成
に、比較的複雑な構成の不感帯調整回路K1及び
K2を夫々附加しなければならないうえに、更に
精密抵抗器として、第6図の場合5個(抵抗R,
R1,R2,R3及びR4)、第7図の場合7個(抵抗
R,R1及びR3)を少くとも必要とするを避け得
ず、このため上述の第2の要求を十分に満足させ
得なかつた。
In order to satisfy the first requirement, conventionally, configurations as shown in FIG. 6 (corresponding to FIG. 2) and FIG. 7 (corresponding to FIG. 3) have been adopted. However, according to this configuration, in addition to the configurations shown in FIGS. 2 and 3, dead band adjustment circuits K 1 and
In addition to having to add K 2 to each, five precision resistors (resistors R, R,
R 1 , R 2 , R 3 and R 4 ) , and in the case of FIG. I couldn't satisfy you enough.

本考案は上記実情にかんがみてなされたもので
あつて、抵抗精度に全く依存しない簡易な構成な
がら精度の高い回路を実現し、さらにフローテイ
ングの電源を加えることにより1個の調整素子に
より不感帯幅を正負同時に調整可能にする不感帯
発生回路を提供するものである。
The present invention has been developed in view of the above circumstances, and has realized a highly accurate circuit with a simple configuration that does not depend on resistance accuracy at all. Furthermore, by adding a floating power supply, the dead band width can be reduced using a single adjustment element. The present invention provides a dead band generation circuit that allows positive and negative adjustments to be made at the same time.

以下、本考案の一実施例について第8図を参照
して説明する。
An embodiment of the present invention will be described below with reference to FIG.

第8図に示す不感帯発生回路にあつては、入力
端子TINに到来した入力電圧VINを受ける入力バ
ツフア回路A1と、この回路A1の出力部に負入力
に対する不感帯設定の抵抗R1を介して負電圧を
出力する為の片極性回路を構成する演算増幅器
A2と、同じく回路A1の出力部に正入力に対する
不感帯設定の抵抗R2を介して正電圧を出力する
為の片極性回路を構成する演算増幅器A3とを有
する。この演算増幅器A2の出力部にはダイオー
ドD1のカソード側が接続され、そのアノード側
は増幅器A2の反転入力部に接続されている。ま
た、演算増幅器A3の出力部には、ダイオードD2
のアノード側が接続され、他方のカソード側は増
幅器A3の反転入力部に持続されている。ダイオ
ードD1のアノード側とダイオードD2のカソード
側は出力端子TOに接続され、さらにROを介して
接地されている。
The dead zone generation circuit shown in FIG. 8 includes an input buffer circuit A1 that receives the input voltage V IN that has arrived at the input terminal T IN , and a resistor R1 that sets the dead zone for negative input at the output section of this circuit A1 . An operational amplifier that configures a unipolar circuit to output negative voltage through
A 2 and an operational amplifier A 3 forming a unipolar circuit for outputting a positive voltage via a resistor R 2 with a dead band setting for the positive input at the output section of the circuit A 1 . The cathode side of a diode D1 is connected to the output part of this operational amplifier A2 , and the anode side thereof is connected to the inverting input part of the amplifier A2 . In addition, a diode D 2 is connected to the output section of the operational amplifier A 3 .
The anode side of the amplifier A3 is connected and the other cathode side is connected to the inverting input of the amplifier A3 . The anode side of the diode D 1 and the cathode side of the diode D 2 are connected to the output terminal T O and further grounded via R O .

また演算増幅器A2の非反転入力部には定電流
を流入せしめる定電流源I1が接続され、前記演算
増幅器A3の非反転入力部には定電流を流出せし
める定電流源I2が接続されている。
Further, a constant current source I 1 that causes a constant current to flow in is connected to the non-inverting input portion of the operational amplifier A 2 , and a constant current source I 2 that causes a constant current to flow out to the non-inverting input portion of the operational amplifier A 3 . has been done.

次に、以上のように構成する不感帯発生回路の
作用を説明する。入力端子TINに入力電圧VIN
供給すると、増幅器A1を介して抵抗R1出力側つ
まり演算増幅器A2の非反転入力部にはVIN+R1I1
の電圧が得られ、また演算増幅器A3の非反転入
力部にはVIN−R2I2の電圧が得られる。従つて、
入力電圧VINが−R1I1より大きくR2I2より小さい
範囲では、演算増幅器A2の入力電圧は正となる
のでダイオードD1はオフとなり、また演算増幅
器A3の入力電圧は負となるのでダイオードD2
オフとなり、出力電圧VOはOVとなる。入力電圧
が−R1I1より小さい範囲では、演算増幅器A2及び
A3の入力電圧は負なのでダイオードD1のみがオ
ンとなり、出力電圧VOはVIN+R1I1となる。入
力電圧がR2I2より大きい範囲では、増幅器A2及び
A3の入力電圧は正なのでダイオードD2のみオン
となり、出力電圧VOはVIN−R2I2となる。
Next, the operation of the dead zone generating circuit configured as above will be explained. When input voltage V IN is supplied to input terminal T IN , V IN +R 1 I 1 is applied to the output side of resistor R 1 through amplifier A 1 , that is, to the non-inverting input of operational amplifier A 2 .
A voltage of V IN -R 2 I 2 is obtained at the non-inverting input of the operational amplifier A 3 . Therefore,
In the range where the input voltage V IN is greater than -R 1 I 1 and less than R 2 I 2 , the input voltage of operational amplifier A 2 is positive, so diode D 1 is turned off, and the input voltage of operational amplifier A 3 is negative. Therefore, the diode D 2 is turned off and the output voltage V O becomes OV. In the range where the input voltage is less than −R 1 I 1 , the operational amplifier A 2 and
Since the input voltage of A 3 is negative, only diode D 1 is turned on, and the output voltage V O becomes V IN +R 1 I 1 . In the range where the input voltage is greater than R 2 I 2 , the amplifier A 2 and
Since the input voltage of A 3 is positive, only diode D 2 is turned on, and the output voltage V O becomes V IN −R 2 I 2 .

従つて、入力電圧VINと出力電圧VOとの関係
は、第9図に示すように、折点の電圧が−R1I1
R2I2で、リニア部分の勾配が1であるような出力
電圧VOが得られる。
Therefore, as shown in FIG. 9, the relationship between the input voltage V IN and the output voltage V O is such that the voltage at the break point is -R 1 I 1 .
R 2 I 2 yields an output voltage V O such that the slope of the linear part is 1.

なお、本考案は上記実施例に限定されるもので
はない。例えば第10図のように定電流電源の代
りに、演算増幅器A2及びA3の両非反転入力部間
にフローテイングの可変電源VFを用いれば、1
個の調整素子によつて正負の不感帯幅を同時に変
えることが可能である。
Note that the present invention is not limited to the above embodiments. For example, if a floating variable power supply V F is used between both non-inverting inputs of operational amplifiers A 2 and A 3 instead of a constant current power supply as shown in FIG.
It is possible to simultaneously change the positive and negative dead band widths using individual adjustment elements.

以上詳記したように本考案によれば、簡単な構
成をとりながら抵抗の精度に依存することなく不
感帯と感帯とを峻別させて信号を出力できる不感
帯発生回路を提供できる。
As described in detail above, according to the present invention, it is possible to provide a dead zone generation circuit which has a simple configuration and can output a signal by clearly distinguishing between a dead zone and a sensitive zone without depending on the precision of the resistor.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は不感帯発生回路によつて得るべき不感
帯特性を示す特性曲線図、第2図および第3図は
従来の不感帯発生回路を示す接続図、第4図およ
び第5図はそれらの回路の特性を示す特性曲線
図、第6図および第7図は第2図および第3図の
実際の機器に適用する場合に使用される従来の構
成を示す接続図、第8図は本考案に係る不感帯発
生回路の一実施例を示す接続図、第9図はその特
性を示す特性曲線図、第10図は本考案の他の例
を示す接続図である。 A1〜A3……演算増幅器、R0,R1,R2……抵
抗、D1,D2……ダイオード、I1,I2……定電流
源、VE……フローテイングの可変電源。
Fig. 1 is a characteristic curve diagram showing dead band characteristics to be obtained by a dead band generating circuit, Figs. 2 and 3 are connection diagrams showing conventional dead band generating circuits, and Figs. 4 and 5 are diagrams of those circuits. A characteristic curve diagram showing the characteristics, FIGS. 6 and 7 are connection diagrams showing the conventional configuration used when applied to the actual equipment shown in FIGS. 2 and 3, and FIG. 8 is a connection diagram according to the present invention. FIG. 9 is a connection diagram showing one embodiment of the dead zone generating circuit, FIG. 9 is a characteristic curve diagram showing its characteristics, and FIG. 10 is a connection diagram showing another example of the present invention. A 1 to A 3 ... operational amplifier, R 0 , R 1 , R 2 ... resistance, D 1 , D 2 ... diode, I 1 , I 2 ... constant current source, V E ... floating variable power supply.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 正負入力信号の供給されるバツフア増幅器と、
このバツフア増幅器の出力部に一端が接続される
負入力に対する不感帯設定用の第1の抵抗および
正入力に対する不感帯設定用の第2の低抗と、こ
の第1の抵抗の他端が非反転入力端子に接続され
るとともに出力部に負入力で動作す第1のダイオ
ードの一端が接続された第1の演算増幅器と、前
記第2の抵抗の他端が非反転入力端子に接続され
るとともに出力部に正入力で動作する第2のダイ
オードの一端が接続された第2の演算増幅器と、
これら第1および第2の演算増幅器の各入力部の
非反転入力端子に接続されたそれぞれ極性の異な
る定電流源又は電圧の信号発生源と、前記第1お
よび第2のダイオードの他端を共通接続して前記
第1および第2の演算増幅器の各反転入力端子に
接続するとともに前記共通接続端と零電位との間
に介挿した第3の抵抗とを具備し、不感帯幅が前
記第1および第2の抵抗により設定されるととも
にリニア部分が前記第1、第2および第3の抵抗
の影響を受けない前記正負入力信号の比例したも
のとなることを特徴とする不感帯発生回路。
a buffer amplifier to which positive and negative input signals are supplied;
A first resistor for setting a dead band for the negative input, one end of which is connected to the output section of the buffer amplifier, and a second low resistor for setting the dead zone for the positive input, and the other end of the first resistor is the non-inverting input. a first operational amplifier connected to the terminal and having one end of a first diode connected to the output section that operates with a negative input, and the other end of the second resistor being connected to the non-inverting input terminal and outputting. a second operational amplifier to which one end of a second diode that operates with a positive input is connected;
A constant current source or voltage signal generation source of different polarity connected to the non-inverting input terminal of each input section of these first and second operational amplifiers and the other ends of the first and second diodes are common. a third resistor connected to each inverting input terminal of the first and second operational amplifiers and interposed between the common connection end and zero potential, the third resistor having a dead band width equal to or less than the first resistor; and a second resistor, and the linear portion is proportional to the positive and negative input signals that are not affected by the first, second and third resistors.
JP1980138471U 1980-09-29 1980-09-29 Expired JPS6241453Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1980138471U JPS6241453Y2 (en) 1980-09-29 1980-09-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1980138471U JPS6241453Y2 (en) 1980-09-29 1980-09-29

Publications (2)

Publication Number Publication Date
JPS5760415U JPS5760415U (en) 1982-04-09
JPS6241453Y2 true JPS6241453Y2 (en) 1987-10-23

Family

ID=29498502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1980138471U Expired JPS6241453Y2 (en) 1980-09-29 1980-09-29

Country Status (1)

Country Link
JP (1) JPS6241453Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4534808B2 (en) * 2005-03-11 2010-09-01 横河電機株式会社 Amplifier circuit with current limiter

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3851259A (en) * 1973-03-30 1974-11-26 Bendix Corp Deadzone circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3851259A (en) * 1973-03-30 1974-11-26 Bendix Corp Deadzone circuit

Also Published As

Publication number Publication date
JPS5760415U (en) 1982-04-09

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