JPS6240427Y2 - - Google Patents

Description

[Detailed explanation of the invention] This invention is a capacitor with improved reliability.
In particular, it relates to small, low voltage, large capacity semiconductor capacitors.

Conventionally, there has been a method in which a plurality of completed ceramic plates with opposing electrodes are simply stacked, the electrodes on one side are soldered to a lead wire, and the electrodes on the other side are soldered to another lead wire. When stacked, the space between opposing electrodes is filled with solder.

However, with this structure, stress due to solder shrinkage is applied to the ceramic board, increasing the breakdown voltage (BVD).
This resulted in a decline in reliability and reliability. Also,
It is difficult to completely fill the space between opposing electrodes with solder when stacked, and the presence of voids between the electrodes has the unavoidable drawback, which is difficult to avoid during humid load tests, humid storage tests, and actual use. It becomes a place where water droplets accumulate, reducing reliability.

Therefore, the method of manufacturing a multilayer capacitor by stacking fired ceramic plates is extremely difficult and has not yet been realized.

In this idea, when dielectric sheets such as ceramics with electrodes are stacked alternately, the dielectric sheets are joined with adhesive double-sided tape that has a mechanical buffering effect, and the opposite electrodes are connected via the tape. By electrically connecting them, stress due to shrinkage of the bonding material such as solder is not applied to the dielectric sheet such as ceramic, and voids are also prevented from forming between adjacent electrodes.

Examples of this invention will be described below with reference to the drawings.

Resist ink is applied to the main plane of a sintered semiconductor ceramic sheet 2 of a certain length where electrodes are not to be formed, and then electrodes are plated. Then, partial electrodes 3 and 4 are provided on the opposing main planes of the sheet 2, and extraction electrodes 5 and 6 are provided on the side surfaces of the sheet 2 integrally connected thereto.

As shown in FIG. 2, such capacitor units 1 are stacked and fixed with heat-resistant double-sided polyimide adhesive tape 7 having a thickness of about 10 to 20 (μ). In this case, the extraction electrodes 5 and 6 of each sheet 2 are located on the same side surface with the same number, such as the extraction electrode 5 on the left side of the drawing and the extraction electrode 6 on the right side.
Then cut according to the required capacitance value.

As shown in FIG. 3, the extraction electrodes 5 of each sheet 2 are connected to each other by an extraction lead 8, and the extraction electrodes 6 are connected to each other by an extraction lead 9 using solder. In order not to run out of exterior resin, the eight corners of the hexahedron formed by stacking each sheet 2 are cut off as necessary, and then the depth coating is applied.

4 shows a modified example in which reinforcing metal U-shaped electrodes 10, 11 are brought into contact with the lead electrodes 5, 6, respectively, and soldered through windows 12 provided in the electrodes 10, 11. With this structure, it can be used practically as a chip capacitor.

Ceramic materials are not limited to the semiconductor ceramics described above.

The tape is not limited to polyimide tape as long as it has enough heat resistance to not melt or soften during soldering, and for example, polycarbonate tape may be used.

The capacitor electrode and the lead electrode may be formed by a method other than plating.

As is clear from the above examples, according to this invention, when stacking dielectric sheets provided with electrodes, adhesive double-sided adhesive tape is used to achieve mutual mechanical fixation, and then electrical Since the connection is made, there is no solder or void between the dielectric sheets, resulting in a lower yield rate.
BVD, improved reliability can be achieved, e.g.
(μF) 12 (V), 5 (μF) 6 (V), 10 (μF)
A small, low-voltage, large-capacity semiconductor ceramic capacitor of F) 3 (V) was realized.

[Brief explanation of the drawing]

FIG. 1 is a perspective view of an embodiment of the present invention, FIG. 2 is a side view, FIG. 3 is a perspective view, and FIG. 4 is a perspective view. DESCRIPTION OF SYMBOLS 1... Capacitor unit, 2... Ceramic sheet, 3, 4... Counter electrode, 5, 6... Outgoing electrode, 7... Double-sided adhesive tape, 8, 9... Outgoing lead, 10, 11... U-shape electrode.

Claims (1)

[Scope of utility model registration request] A multilayer capacitor characterized in that a plurality of dielectric sheets provided with electrodes are stacked with double-sided adhesive tape interposed, and the electrodes on one side are electrically connected to each other, and the electrodes on the other side are electrically connected to each other.